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DE60320057D1 - System und Verfahren zur Schaltungsprüfung - Google Patents

System und Verfahren zur Schaltungsprüfung

Info

Publication number
DE60320057D1
DE60320057D1 DE60320057T DE60320057T DE60320057D1 DE 60320057 D1 DE60320057 D1 DE 60320057D1 DE 60320057 T DE60320057 T DE 60320057T DE 60320057 T DE60320057 T DE 60320057T DE 60320057 D1 DE60320057 D1 DE 60320057D1
Authority
DE
Germany
Prior art keywords
circuit testing
testing
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60320057T
Other languages
English (en)
Other versions
DE60320057T2 (de
Inventor
George E Barbera
David C Crohn
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Broadcom Corp
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Publication of DE60320057D1 publication Critical patent/DE60320057D1/de
Application granted granted Critical
Publication of DE60320057T2 publication Critical patent/DE60320057T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318594—Timing aspects
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318541—Scan latches or cell details

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE60320057T 2002-03-01 2003-03-03 System und Verfahren zur Schaltungsprüfung Expired - Lifetime DE60320057T2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US36100402P 2002-03-01 2002-03-01
US361004P 2002-03-01
US10/187,116 US6968488B2 (en) 2002-03-01 2002-06-28 System and method for testing a circuit
US187116 2002-06-28

Publications (2)

Publication Number Publication Date
DE60320057D1 true DE60320057D1 (de) 2008-05-15
DE60320057T2 DE60320057T2 (de) 2009-05-20

Family

ID=27737031

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60320057T Expired - Lifetime DE60320057T2 (de) 2002-03-01 2003-03-03 System und Verfahren zur Schaltungsprüfung

Country Status (3)

Country Link
US (2) US6968488B2 (de)
EP (1) EP1340991B1 (de)
DE (1) DE60320057T2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6968488B2 (en) * 2002-03-01 2005-11-22 Broadcom Corporation System and method for testing a circuit
US7240260B2 (en) * 2002-12-11 2007-07-03 Intel Corporation Stimulus generation
US9432020B2 (en) 2014-06-25 2016-08-30 Stmicroelectronics S.R.L. Communication cell for an integrated circuit operating in contact and contactless mode, electronic chip comprising the communication cell, electronic system including the chip, and test apparatus
US9678154B2 (en) 2014-10-30 2017-06-13 Qualcomm Incorporated Circuit techniques for efficient scan hold path design
KR20220142212A (ko) * 2021-04-14 2022-10-21 삼성전자주식회사 멀티 비트 플립플롭 및 이를 포함하는 집적회로

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03252569A (ja) 1990-02-26 1991-11-11 Advanced Micro Devicds Inc スキャンパス用レジスタ回路
JP2811872B2 (ja) 1990-02-26 1998-10-15 富士電機株式会社 半導体装置の保護回路
US5329167A (en) * 1992-09-25 1994-07-12 Hughes Aircraft Company Test flip-flop with an auxillary latch enabling two (2) bits of storage
JP3229164B2 (ja) * 1994-07-28 2001-11-12 インターナショナル・ビジネス・マシーンズ・コーポレーション ラッチ回路
JP3363691B2 (ja) * 1996-03-13 2003-01-08 シャープ株式会社 半導体論理集積回路
US5642364A (en) * 1996-06-28 1997-06-24 Hughes Electronics Contactless testing of inputs and outputs of integrated circuits
US5907562A (en) 1996-07-31 1999-05-25 Nokia Mobile Phones Limited Testable integrated circuit with reduced power dissipation
US5886901A (en) 1997-01-07 1999-03-23 Lsi Logic Corporation Flip-flop for scan test chain
US5896046A (en) * 1997-01-27 1999-04-20 International Business Machines Corporation Latch structure for ripple domino logic
US5887004A (en) * 1997-03-28 1999-03-23 International Business Machines Corporation Isolated scan paths
US6708303B1 (en) * 1998-03-06 2004-03-16 Texas Instruments Incorporated Method and apparatus for controlling a seperate scan output of a scan circuit
US6389566B1 (en) * 1998-06-02 2002-05-14 S3 Incorporated Edge-triggered scan flip-flop and one-pass scan synthesis methodology
US6272654B1 (en) * 1999-03-04 2001-08-07 International Business Machines Corporation Fast scannable output latch with domino logic input
JP2003518631A (ja) * 1999-12-24 2003-06-10 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 低電力スキャンフリップフロップ
US6377098B1 (en) * 2000-04-21 2002-04-23 International Business Machines Corporation CMOS latch having a selectable feedback path
US6775116B2 (en) * 2001-11-01 2004-08-10 Agilent Technologies, Inc. Method and apparatus for preventing buffers from being damaged by electrical charges collected on lines connected to the buffers
US7039843B2 (en) * 2001-11-13 2006-05-02 Sun Microsystems, Inc. Modeling custom scan flops in level sensitive scan design
US6968488B2 (en) * 2002-03-01 2005-11-22 Broadcom Corporation System and method for testing a circuit
US6925590B2 (en) * 2002-04-22 2005-08-02 Broadcom Corporation Scan interface
US6904554B2 (en) * 2002-06-26 2005-06-07 Lsi Logic Corporation Logic built-in self test (BIST)
JP2004301661A (ja) * 2003-03-31 2004-10-28 Hitachi Ltd 半導体集積回路

Also Published As

Publication number Publication date
EP1340991B1 (de) 2008-04-02
EP1340991A2 (de) 2003-09-03
EP1340991A3 (de) 2004-09-15
US6968488B2 (en) 2005-11-22
US20050216807A1 (en) 2005-09-29
US20030167430A1 (en) 2003-09-04
DE60320057T2 (de) 2009-05-20
US7836365B2 (en) 2010-11-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition