[go: up one dir, main page]

DE60320745D1 - Verfahren und MBISR (Memory Built-In Self Repair) zum Reparieren eines Speichers - Google Patents

Verfahren und MBISR (Memory Built-In Self Repair) zum Reparieren eines Speichers

Info

Publication number
DE60320745D1
DE60320745D1 DE60320745T DE60320745T DE60320745D1 DE 60320745 D1 DE60320745 D1 DE 60320745D1 DE 60320745 T DE60320745 T DE 60320745T DE 60320745 T DE60320745 T DE 60320745T DE 60320745 D1 DE60320745 D1 DE 60320745D1
Authority
DE
Germany
Prior art keywords
repair
memory
mbisr
self
built
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60320745T
Other languages
English (en)
Inventor
Ronza Mario Di
Yannick Martelloni
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Application granted granted Critical
Publication of DE60320745D1 publication Critical patent/DE60320745D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/72—Masking faults in memories by using spares or by reconfiguring with optimized replacement algorithms
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/81—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a hierarchical redundancy scheme
DE60320745T 2003-02-12 2003-02-12 Verfahren und MBISR (Memory Built-In Self Repair) zum Reparieren eines Speichers Expired - Lifetime DE60320745D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP03002698A EP1447813B9 (de) 2003-02-12 2003-02-12 Verfahren und MBISR (Memory Built-In Self Repair) zum Reparieren eines Speichers

Publications (1)

Publication Number Publication Date
DE60320745D1 true DE60320745D1 (de) 2008-06-19

Family

ID=32668951

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60320745T Expired - Lifetime DE60320745D1 (de) 2003-02-12 2003-02-12 Verfahren und MBISR (Memory Built-In Self Repair) zum Reparieren eines Speichers

Country Status (3)

Country Link
US (1) US7627792B2 (de)
EP (2) EP1447813B9 (de)
DE (1) DE60320745D1 (de)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6937531B2 (en) * 2003-07-21 2005-08-30 Infineon Technologies Ag Memory device and method of storing fail addresses of a memory cell
EP1517334B1 (de) 2003-09-16 2010-10-27 Infineon Technologies AG On-chip Diagnose-Vefahren und -Block zur Speicherreparatur mit gemischter Redundanz ("IO" Redundanz und "Word-register" Redundanz)
US7350119B1 (en) * 2004-06-02 2008-03-25 Advanced Micro Devices, Inc. Compressed encoding for repair
TWI252397B (en) * 2004-09-17 2006-04-01 Ind Tech Res Inst Method and apparatus of built-in self-diagnosis and repair in a memory with syndrome identification
US7644323B2 (en) * 2004-11-30 2010-01-05 Industrial Technology Research Institute Method and apparatus of build-in self-diagnosis and repair in a memory with syndrome identification
JP2006236551A (ja) * 2005-01-28 2006-09-07 Renesas Technology Corp テスト機能を有する半導体集積回路および製造方法
JP2006286141A (ja) * 2005-04-04 2006-10-19 Toshiba Corp 半導体記憶装置
KR100745403B1 (ko) * 2005-08-25 2007-08-02 삼성전자주식회사 반도체 메모리 장치 및 그 셀프 테스트 방법
US7768847B2 (en) 2008-04-09 2010-08-03 Rambus Inc. Programmable memory repair scheme
JP5554476B2 (ja) * 2008-06-23 2014-07-23 ピーエスフォー ルクスコ エスエイアールエル 半導体記憶装置および半導体記憶装置の試験方法
US7839707B2 (en) * 2008-09-09 2010-11-23 Vitesse Semiconductor Corporation Fuses for memory repair
US8010847B2 (en) * 2008-09-30 2011-08-30 Infineon Technologies Ag Memory repair
US8127184B2 (en) * 2008-11-26 2012-02-28 Qualcomm Incorporated System and method including built-in self test (BIST) circuit to test cache memory
US8446161B2 (en) * 2009-03-17 2013-05-21 Taiwan Semiconductor Manufacturing Company, Ltd. Method of self monitoring and self repair for a semiconductor IC
US11119857B2 (en) * 2012-09-18 2021-09-14 Mosys, Inc. Substitute redundant memory
US8719648B2 (en) 2011-07-27 2014-05-06 International Business Machines Corporation Interleaving of memory repair data compression and fuse programming operations in single fusebay architecture
US8467260B2 (en) 2011-08-05 2013-06-18 International Business Machines Corporation Structure and method for storing multiple repair pass data into a fusebay
US8484543B2 (en) 2011-08-08 2013-07-09 International Business Machines Corporation Fusebay controller structure, system, and method
US8537627B2 (en) 2011-09-01 2013-09-17 International Business Machines Corporation Determining fusebay storage element usage
US9734921B2 (en) * 2012-11-06 2017-08-15 Rambus Inc. Memory repair using external tags
US10198314B2 (en) 2013-05-23 2019-02-05 Rambus Inc. Memory device with in-system repair capability
KR20160022097A (ko) 2014-08-19 2016-02-29 삼성전자주식회사 재구성 차단 기능을 가지는 반도체 메모리 장치 및 메모리 모듈
US10153055B2 (en) 2015-03-26 2018-12-11 International Business Machines Corporation Arbitration for memory diagnostics
US10204698B2 (en) 2016-12-20 2019-02-12 Ampere Computing Llc Method to dynamically inject errors in a repairable memory on silicon and a method to validate built-in-self-repair logic
US10950325B2 (en) * 2019-04-04 2021-03-16 Marvell Asia Pte., Ltd. Memory built-in self test error correcting code (MBIST ECC) for low voltage memories
TWI736252B (zh) * 2020-05-08 2021-08-11 大陸商珠海南北極科技有限公司 記憶體電路及其記憶體修補方法
WO2021244917A1 (de) 2020-05-30 2021-12-09 Oerlikon Textile Gmbh & Co. Kg Zahnradpumpe zum dosierten fördern von farblacken
CN115877171A (zh) * 2021-09-28 2023-03-31 紫光同芯微电子有限公司 一种芯片测试方法和装置
CN116246685A (zh) * 2021-12-08 2023-06-09 三星电子株式会社 输出测试结果的存储器件及测试其的方法

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5153880A (en) * 1990-03-12 1992-10-06 Xicor, Inc. Field-programmable redundancy apparatus for memory arrays
US5161157A (en) * 1990-03-12 1992-11-03 Xicor, Inc. Field-programmable redundancy apparatus for memory arrays
US6026505A (en) * 1991-10-16 2000-02-15 International Business Machines Corporation Method and apparatus for real time two dimensional redundancy allocation
US5588115A (en) * 1993-01-29 1996-12-24 Teradyne, Inc. Redundancy analyzer for automatic memory tester
GB2292236A (en) * 1995-04-04 1996-02-14 Memory Corp Plc Improved partial memory engine
US5808945A (en) * 1996-02-21 1998-09-15 Sony Corporation Semiconductor memory having redundant memory array
US6011734A (en) * 1998-03-12 2000-01-04 Motorola, Inc. Fuseless memory repair system and method of operation
TW446955B (en) * 1998-10-30 2001-07-21 Siemens Ag The read/write memory with self-testing device and its associated test method
JP4204685B2 (ja) * 1999-01-19 2009-01-07 株式会社ルネサステクノロジ 同期型半導体記憶装置
US6141267A (en) * 1999-02-03 2000-10-31 International Business Machines Corporation Defect management engine for semiconductor memories and memory systems
US6181614B1 (en) * 1999-11-12 2001-01-30 International Business Machines Corporation Dynamic repair of redundant memory array
US6640321B1 (en) * 2000-04-14 2003-10-28 Lsi Logic Corporation Built-in self-repair of semiconductor memory with redundant row testing using background pattern
JP2001358296A (ja) * 2000-06-14 2001-12-26 Mitsubishi Electric Corp 半導体集積回路装置
FR2811464B1 (fr) * 2000-07-05 2005-03-25 St Microelectronics Sa Circuit memoire comportant des cellules de secours
US6795942B1 (en) * 2000-07-06 2004-09-21 Lsi Logic Corporation Built-in redundancy analysis for memories with row and column repair
KR100374636B1 (ko) * 2000-10-18 2003-03-04 삼성전자주식회사 결함 테스트 및 분석 회로를 구비하는 반도체 장치 및 결함 분석 방법
US20020108073A1 (en) * 2001-02-02 2002-08-08 Hughes Brian William System for and method of operating a programmable column fail counter for redundancy allocation
US7178072B2 (en) * 2001-06-08 2007-02-13 Renesas Technology America, Inc. Methods and apparatus for storing memory test information
US6862703B2 (en) * 2001-08-13 2005-03-01 Credence Systems Corporation Apparatus for testing memories with redundant storage elements
US6973604B2 (en) * 2002-03-08 2005-12-06 Hewlett-Packard Development Company, L.P. Allocation of sparing resources in a magnetoresistive solid-state storage device
US6879530B2 (en) * 2002-07-18 2005-04-12 Micron Technology, Inc. Apparatus for dynamically repairing a semiconductor memory
US7003704B2 (en) * 2002-11-12 2006-02-21 International Business Machines Corporation Two-dimensional redundancy calculation
DE10256487B4 (de) * 2002-12-03 2008-12-24 Infineon Technologies Ag Integrierter Speicher und Verfahren zum Testen eines integrierten Speichers
US20040123181A1 (en) * 2002-12-20 2004-06-24 Moon Nathan I. Self-repair of memory arrays using preallocated redundancy (PAR) architecture
US7188274B2 (en) * 2003-02-14 2007-03-06 Logicvision, Inc. Memory repair analysis method and circuit
US6928377B2 (en) * 2003-09-09 2005-08-09 International Business Machines Corporation Self-test architecture to implement data column redundancy in a RAM

Also Published As

Publication number Publication date
EP1447813B1 (de) 2008-05-07
EP1447813A1 (de) 2004-08-18
EP1447813B9 (de) 2008-10-22
US20040225912A1 (en) 2004-11-11
EP1465204A3 (de) 2005-03-30
EP1465204A2 (de) 2004-10-06
US7627792B2 (en) 2009-12-01

Similar Documents

Publication Publication Date Title
DE60320745D1 (de) Verfahren und MBISR (Memory Built-In Self Repair) zum Reparieren eines Speichers
ATE548564T1 (de) Verfahren zum betreiben eines windparks und windpark
DE50305588D1 (de) Biosensor-array und verfahren zum betreiben eines biosensor-arrays
DE60326760D1 (de) Verfahren zum verbinden
DE10393558D2 (de) Verfahren und Einrichtung zum Stabilisieren eines Gespanns
DE60222798D1 (de) Verfahren zum garantierten mediumzugriff in einen drahtlosen netzwerk
ATE471435T1 (de) Verfahren zum einstellen, fertigstellen und aufwältigen eines bohrlochs
DE50312744D1 (de) Verfahren zum betreiben eines verdichters
DE602004010430D1 (de) Verfahren zum kooperativen sps- und pps-betrieb
DE50304673D1 (de) Strömungsmaschine und Verfahren zum Herstellen eines Leitgitters
DE602004009264D1 (de) Sprachgesteuertes Gerät zum Editieren eines Roboterlehrprogrammes
DE502005000727D1 (de) Batteriesensor und verfahren zum betreiben eines batteriesensors
DE60316197D1 (de) Verfahren und System zum Teilen eines Speichermoduls
DE602005013755D1 (de) Verfahren zum Zugriff eines einmal programmierbaren Speicher
DE60332926D1 (de) Verfahren zum trocknen eines wabenförmigen körpers
DE602004000726D1 (de) Vorrichtung zum Ballastieren eines Krans
DE502004006428D1 (de) Verfahren zum abbremsen eines fahrzeugs
DE602004005696D1 (de) Aufweitsystem zum schrittweisen aufweiten eines röhrenförmigen elements
DE602005018280D1 (de) Verfahren und Vorrichtung zum Schreiben in ein Speicheretikett
DE10393560D2 (de) Verfahren und Einrichtung zum Stabilisieren eines Gespanns
DE60206223D1 (de) Verfahren und Anordnung zum Schreiben eines Speichers
DE60317024D1 (de) Methode zum Setzen der Konfigurationsinformationen eines Speichergerätes
DE60317121D1 (de) Verfahren zum Falten eines Gassackes
DE602005009464D1 (de) Verfahren und Vorrichtung zum Programmieren eines nichtflüchtigen Speichers
ATA222005A (de) Verfahren und anordnung zum schützen von geldausgabeautomaten

Legal Events

Date Code Title Description
8364 No opposition during term of opposition