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DE60317963D1 - Verfahren zur Herstellung eines Halbleiterbauelements - Google Patents

Verfahren zur Herstellung eines Halbleiterbauelements

Info

Publication number
DE60317963D1
DE60317963D1 DE60317963T DE60317963T DE60317963D1 DE 60317963 D1 DE60317963 D1 DE 60317963D1 DE 60317963 T DE60317963 T DE 60317963T DE 60317963 T DE60317963 T DE 60317963T DE 60317963 D1 DE60317963 D1 DE 60317963D1
Authority
DE
Germany
Prior art keywords
producing
semiconductor component
semiconductor
component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60317963T
Other languages
English (en)
Other versions
DE60317963T2 (de
Inventor
David Russell Evans
Sheng Teng Hsu
Bruce Dale Ulrich
Douglas James Tweet
Lisa H Stecker
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Publication of DE60317963D1 publication Critical patent/DE60317963D1/de
Application granted granted Critical
Publication of DE60317963T2 publication Critical patent/DE60317963T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H10W10/011—
    • H10D64/01342—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0151—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H10W10/014—
    • H10W10/10—
    • H10W10/17—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/975—Substrate or mask aligning feature
DE60317963T 2002-03-29 2003-03-10 Verfahren zur Herstellung eines Halbleiterbauelements Expired - Lifetime DE60317963T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US112014 1993-08-25
US10/112,014 US6627510B1 (en) 2002-03-29 2002-03-29 Method of making self-aligned shallow trench isolation

Publications (2)

Publication Number Publication Date
DE60317963D1 true DE60317963D1 (de) 2008-01-24
DE60317963T2 DE60317963T2 (de) 2008-11-27

Family

ID=28453218

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60317963T Expired - Lifetime DE60317963T2 (de) 2002-03-29 2003-03-10 Verfahren zur Herstellung eines Halbleiterbauelements

Country Status (6)

Country Link
US (1) US6627510B1 (de)
EP (1) EP1353369B1 (de)
KR (1) KR100515181B1 (de)
CN (1) CN1278407C (de)
DE (1) DE60317963T2 (de)
TW (1) TWI235450B (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5037766B2 (ja) * 2001-09-10 2012-10-03 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
DE10301291B3 (de) * 2003-01-15 2004-08-26 Infineon Technologies Ag Verfahren zum Einbringen von eine unterschiedliche Dimensionierung aufweisenden Strukturen in ein Substrat
US6716691B1 (en) * 2003-06-25 2004-04-06 Sharp Laboratories Of America, Inc. Self-aligned shallow trench isolation process having improved polysilicon gate thickness control
KR100514173B1 (ko) * 2004-01-15 2005-09-09 삼성전자주식회사 반도체 장치의 게이트 형성 방법.
US7012021B2 (en) * 2004-01-29 2006-03-14 Taiwan Semiconductor Mfg Method for end point detection polysilicon chemical mechanical polishing in an anti-fuse memory device
US8039339B2 (en) * 2007-04-23 2011-10-18 Freescale Semiconductor, Inc. Separate layer formation in a semiconductor device
CN102468212B (zh) * 2010-11-15 2014-03-12 中芯国际集成电路制造(上海)有限公司 浅沟槽隔离结构形成方法
CN102339746B (zh) * 2011-09-28 2016-04-06 上海华虹宏力半导体制造有限公司 形成平坦介质层的方法
US9330959B2 (en) * 2014-04-13 2016-05-03 Texas Instruments Incorporated Isolated semiconductor layer in bulk wafer by localized silicon epitaxial seed formation
US10811320B2 (en) * 2017-09-29 2020-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Footing removal in cut-metal process
CN119767779A (zh) * 2025-03-06 2025-04-04 合肥晶合集成电路股份有限公司 一种半导体器件的制备方法及半导体器件

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5238859A (en) * 1988-04-26 1993-08-24 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
JPH0370180A (ja) * 1989-08-09 1991-03-26 Fujitsu Ltd 半導体装置の製造方法
US5202277A (en) * 1989-12-08 1993-04-13 Matsushita Electric Industrial Co., Ltd. Method of fabricating a semiconductor device
JP3174786B2 (ja) * 1991-05-31 2001-06-11 富士通株式会社 半導体装置の製造方法
JP3057882B2 (ja) * 1992-03-09 2000-07-04 日本電気株式会社 半導体装置の製造方法
JP3202460B2 (ja) * 1993-12-21 2001-08-27 株式会社東芝 半導体装置およびその製造方法
US6069081A (en) * 1995-04-28 2000-05-30 International Buiness Machines Corporation Two-step chemical mechanical polish surface planarization technique
JP2790084B2 (ja) * 1995-08-16 1998-08-27 日本電気株式会社 半導体装置の製造方法
DE19538005A1 (de) * 1995-10-12 1997-04-17 Fraunhofer Ges Forschung Verfahren zum Erzeugen einer Grabenisolation in einem Substrat
US5665202A (en) * 1995-11-24 1997-09-09 Motorola, Inc. Multi-step planarization process using polishing at two different pad pressures
US6091129A (en) * 1996-06-19 2000-07-18 Cypress Semiconductor Corporation Self-aligned trench isolated structure
JPH10125637A (ja) * 1996-10-15 1998-05-15 Toshiba Corp 半導体装置の製造方法
US6103592A (en) * 1997-05-01 2000-08-15 International Business Machines Corp. Manufacturing self-aligned polysilicon fet devices isolated with maskless shallow trench isolation and gate conductor fill technology with active devices and dummy doped regions formed in mesas
JP3519579B2 (ja) * 1997-09-09 2004-04-19 株式会社ルネサステクノロジ 半導体装置及びその製造方法
WO1999046081A1 (en) * 1998-03-11 1999-09-16 Strasbaugh Multi-step chemical mechanical polishing process and device
US6326309B2 (en) * 1998-06-30 2001-12-04 Fujitsu Limited Semiconductor device manufacturing method
US6146975A (en) * 1998-07-10 2000-11-14 Lucent Technologies Inc. Shallow trench isolation
KR20010004309A (ko) * 1999-06-28 2001-01-15 김영환 웨이퍼 정렬키 형성방법
KR100318270B1 (ko) * 1999-12-16 2001-12-24 박종섭 반도체 소자의 오버레이 버어니어 형성방법
US6417072B2 (en) * 2000-02-10 2002-07-09 International Business Machines Corporation Method of forming STI oxide regions and alignment marks in a semiconductor structure with one masking step
JP3503888B2 (ja) * 2000-09-01 2004-03-08 沖電気工業株式会社 アライメントマーク及びその形成方法
US6713884B2 (en) * 2001-12-20 2004-03-30 Infineon Technologies Ag Method of forming an alignment mark structure using standard process steps for forming vertical gate transistors

Also Published As

Publication number Publication date
EP1353369A2 (de) 2003-10-15
US6627510B1 (en) 2003-09-30
EP1353369B1 (de) 2007-12-12
US20030186503A1 (en) 2003-10-02
KR20030078637A (ko) 2003-10-08
TW200304686A (en) 2003-10-01
CN1457090A (zh) 2003-11-19
DE60317963T2 (de) 2008-11-27
KR100515181B1 (ko) 2005-09-16
CN1278407C (zh) 2006-10-04
EP1353369A3 (de) 2004-05-06
TWI235450B (en) 2005-07-01

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