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DE60314969D1 - Hochleistungskontaktlöcher für vertikale Packung integrierter Schaltungen - Google Patents

Hochleistungskontaktlöcher für vertikale Packung integrierter Schaltungen

Info

Publication number
DE60314969D1
DE60314969D1 DE60314969T DE60314969T DE60314969D1 DE 60314969 D1 DE60314969 D1 DE 60314969D1 DE 60314969 T DE60314969 T DE 60314969T DE 60314969 T DE60314969 T DE 60314969T DE 60314969 D1 DE60314969 D1 DE 60314969D1
Authority
DE
Germany
Prior art keywords
integrated circuits
high performance
contact holes
vertical packaging
performance contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60314969T
Other languages
English (en)
Other versions
DE60314969T2 (de
Inventor
Gershon Akerling
James M Anderson
Eric L Upton
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Northrop Grumman Systems Corp
Original Assignee
Northrop Grumman Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Northrop Grumman Corp filed Critical Northrop Grumman Corp
Publication of DE60314969D1 publication Critical patent/DE60314969D1/de
Application granted granted Critical
Publication of DE60314969T2 publication Critical patent/DE60314969T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H10W20/20—
    • H10W20/0234—
    • H10W20/2125—
    • H10W90/00—
    • H10W72/07227—
    • H10W72/90—
    • H10W72/952—
    • H10W90/20—
    • H10W90/288—
    • H10W90/297—
    • H10W90/722—
    • H10W90/724—
DE60314969T 2002-12-11 2003-08-04 Hochleistungskontaktlöcher für vertikale Packung integrierter Schaltungen Expired - Lifetime DE60314969T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US317680 2002-12-11
US10/317,680 US6936913B2 (en) 2002-12-11 2002-12-11 High performance vias for vertical IC packaging

Publications (2)

Publication Number Publication Date
DE60314969D1 true DE60314969D1 (de) 2007-08-30
DE60314969T2 DE60314969T2 (de) 2008-04-10

Family

ID=32325947

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60314969T Expired - Lifetime DE60314969T2 (de) 2002-12-11 2003-08-04 Hochleistungskontaktlöcher für vertikale Packung integrierter Schaltungen

Country Status (4)

Country Link
US (1) US6936913B2 (de)
EP (1) EP1429388B1 (de)
JP (1) JP3845403B2 (de)
DE (1) DE60314969T2 (de)

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* Cited by examiner, † Cited by third party
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US6841883B1 (en) * 2003-03-31 2005-01-11 Micron Technology, Inc. Multi-dice chip scale semiconductor components and wafer level methods of fabrication
JP4353845B2 (ja) * 2004-03-31 2009-10-28 富士通株式会社 半導体装置の製造方法
US7394158B2 (en) * 2004-10-21 2008-07-01 Siliconix Technology C.V. Solderable top metal for SiC device
US7812441B2 (en) 2004-10-21 2010-10-12 Siliconix Technology C.V. Schottky diode with improved surge capability
US9419092B2 (en) * 2005-03-04 2016-08-16 Vishay-Siliconix Termination for SiC trench devices
US7834376B2 (en) 2005-03-04 2010-11-16 Siliconix Technology C. V. Power semiconductor switch
US7371676B2 (en) * 2005-04-08 2008-05-13 Micron Technology, Inc. Method for fabricating semiconductor components with through wire interconnects
US7393770B2 (en) * 2005-05-19 2008-07-01 Micron Technology, Inc. Backside method for fabricating semiconductor components with conductive interconnects
US7589406B2 (en) * 2005-06-27 2009-09-15 Micron Technology, Inc. Stacked semiconductor component
US20070070311A1 (en) * 2005-09-23 2007-03-29 Asml Netherlands B.V. Contacts to microdevices
US8368165B2 (en) * 2005-10-20 2013-02-05 Siliconix Technology C. V. Silicon carbide Schottky diode
US7307348B2 (en) 2005-12-07 2007-12-11 Micron Technology, Inc. Semiconductor components having through wire interconnects (TWI)
US7990727B1 (en) * 2006-04-03 2011-08-02 Aprolase Development Co., Llc Ball grid array stack
US7659612B2 (en) 2006-04-24 2010-02-09 Micron Technology, Inc. Semiconductor components having encapsulated through wire interconnects (TWI)
US7569920B2 (en) * 2006-05-10 2009-08-04 Infineon Technologies Ag Electronic component having at least one vertical semiconductor power transistor
EP2047514A4 (de) 2006-07-31 2010-12-01 Vishay Siliconix MOLYBDÄNSPERRMETALL FÜR SiC-SCHOTTKYDIODE UND HERSTELLUNGSVERFAHREN
US8569876B2 (en) 2006-11-22 2013-10-29 Tessera, Inc. Packaged semiconductor chips with array
TWI351751B (en) * 2007-06-22 2011-11-01 Ind Tech Res Inst Self-aligned wafer or chip structure, self-aligned
EP2075828A1 (de) * 2007-12-27 2009-07-01 Interuniversitair Microelektronica Centrum (IMEC) Halbleitervorrichtung und Verfahren zur Ausrichtung und Bindung zweier Elemente zur Herstellung einer Halbleitervorrichtung
US7973416B2 (en) * 2008-05-12 2011-07-05 Texas Instruments Incorporated Thru silicon enabled die stacking scheme
JP4601686B2 (ja) * 2008-06-17 2010-12-22 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
US7846772B2 (en) * 2008-06-23 2010-12-07 Headway Technologies, Inc. Layered chip package and method of manufacturing same
US7767494B2 (en) * 2008-06-30 2010-08-03 Headway Technologies, Inc. Method of manufacturing layered chip package
US7868442B2 (en) * 2008-06-30 2011-01-11 Headway Technologies, Inc. Layered chip package and method of manufacturing same
US7872332B2 (en) 2008-09-11 2011-01-18 Micron Technology, Inc. Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods
US8049319B2 (en) * 2008-10-24 2011-11-01 Electronics And Telecommunications Research Institute Ultra wideband system-on-package
EP2273545B1 (de) * 2009-07-08 2016-08-31 Imec Verfahren zur Einsatzverbindung sowie Montagekit zur Verwendung in dem Verfahren
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
US8736066B2 (en) 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US8587126B2 (en) * 2010-12-02 2013-11-19 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
MY204053A (en) * 2018-10-29 2024-08-05 Intel Corp Plane-less voltage reference interconnects
CN110400787B (zh) * 2019-06-26 2023-04-28 中国电子科技集团公司第三十八研究所 一种硅基垂直互联结构及制备方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3761782A (en) 1971-05-19 1973-09-25 Signetics Corp Semiconductor structure, assembly and method
US4807021A (en) 1986-03-10 1989-02-21 Kabushiki Kaisha Toshiba Semiconductor device having stacking structure
US5229647A (en) 1991-03-27 1993-07-20 Micron Technology, Inc. High density data storage using stacked wafers
WO1996013062A1 (en) 1994-10-19 1996-05-02 Ceram Incorporated Apparatus and method of manufacturing stacked wafer array
US6219254B1 (en) 1999-04-05 2001-04-17 Trw Inc. Chip-to-board connection assembly and method therefor
JP3736607B2 (ja) * 2000-01-21 2006-01-18 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
JP3951091B2 (ja) 2000-08-04 2007-08-01 セイコーエプソン株式会社 半導体装置の製造方法
US6674161B1 (en) * 2000-10-03 2004-01-06 Rambus Inc. Semiconductor stacked die devices

Also Published As

Publication number Publication date
EP1429388B1 (de) 2007-07-18
DE60314969T2 (de) 2008-04-10
US6936913B2 (en) 2005-08-30
JP3845403B2 (ja) 2006-11-15
JP2004193557A (ja) 2004-07-08
EP1429388A1 (de) 2004-06-16
US20040113264A1 (en) 2004-06-17

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