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DE60303168D1 - Verfahren zur langlaufenden Analyse eines Schaltkreisentwurfs - Google Patents

Verfahren zur langlaufenden Analyse eines Schaltkreisentwurfs

Info

Publication number
DE60303168D1
DE60303168D1 DE60303168T DE60303168T DE60303168D1 DE 60303168 D1 DE60303168 D1 DE 60303168D1 DE 60303168 T DE60303168 T DE 60303168T DE 60303168 T DE60303168 T DE 60303168T DE 60303168 D1 DE60303168 D1 DE 60303168D1
Authority
DE
Germany
Prior art keywords
long
circuit design
term analysis
analysis
term
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60303168T
Other languages
English (en)
Other versions
DE60303168T2 (de
Inventor
Chee Hong Eric Liau
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qimonda AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of DE60303168D1 publication Critical patent/DE60303168D1/de
Application granted granted Critical
Publication of DE60303168T2 publication Critical patent/DE60303168T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation
    • G01R31/318357—Simulation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318371—Methodologies therefor, e.g. algorithms, procedures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/20—Design optimisation, verification or simulation

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Tests Of Electronic Circuits (AREA)
DE60303168T 2003-09-30 2003-09-30 Verfahren zur langlaufenden Analyse eines Schaltkreisentwurfs Expired - Lifetime DE60303168T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP03021995A EP1521093B1 (de) 2003-09-30 2003-09-30 Verfahren zur langlaufenden Analyse eines Schaltkreisentwurfs

Publications (2)

Publication Number Publication Date
DE60303168D1 true DE60303168D1 (de) 2006-04-06
DE60303168T2 DE60303168T2 (de) 2006-08-17

Family

ID=34306789

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60303168T Expired - Lifetime DE60303168T2 (de) 2003-09-30 2003-09-30 Verfahren zur langlaufenden Analyse eines Schaltkreisentwurfs

Country Status (3)

Country Link
US (1) US7210086B2 (de)
EP (1) EP1521093B1 (de)
DE (1) DE60303168T2 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8341880B2 (en) 2004-09-16 2013-01-01 Cropdesign N.V. Root evaluation
US20060195744A1 (en) * 2005-02-11 2006-08-31 Broadcom Corporation Method and apparatus to simulate automatic test equipment
KR100809598B1 (ko) * 2006-06-20 2008-03-04 삼성전자주식회사 가상 테스트가 가능한 반도체 테스트 시스템 및 그것의반도체 테스트 방법
WO2010031780A1 (en) * 2008-09-16 2010-03-25 Basf Plant Science Gmbh Method for improved plant breeding
US8350586B2 (en) * 2009-07-02 2013-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus of deembedding
US8661293B2 (en) 2011-06-30 2014-02-25 International Business Machines Corporation Test architecture based on intelligent test sequence
US20150052616A1 (en) * 2013-08-14 2015-02-19 L-3 Communications Corporation Protected mode for securing computing devices
IN2013DE02948A (de) * 2013-10-04 2015-04-10 Unisys Corp
US9552449B1 (en) 2016-01-13 2017-01-24 International Business Machines Corporation Dynamic fault model generation for diagnostics simulation and pattern generation
CN111105839B (zh) * 2018-10-26 2022-04-15 长鑫存储技术有限公司 芯片测试方法、装置、电子设备及计算机可读介质

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5867505A (en) * 1996-08-07 1999-02-02 Micron Technology, Inc. Method and apparatus for testing an integrated circuit including the step/means for storing an associated test identifier in association with integrated circuit identifier for each test to be performed on the integrated circuit
US5935264A (en) * 1997-06-10 1999-08-10 Micron Technology, Inc. Method and apparatus for determining a set of tests for integrated circuit testing
US6098186A (en) * 1998-05-29 2000-08-01 Hewlett-Packard Company Test permutator
US6070260A (en) * 1998-09-17 2000-05-30 Xilinx, Inc. Test methodology based on multiple skewed scan clocks
US6651202B1 (en) * 1999-01-26 2003-11-18 Lsi Logic Corporation Built-in self repair circuitry utilizing permanent record of defects
US20050024074A1 (en) * 2003-08-01 2005-02-03 Gary Benjamin Method and apparatus for characterizing an electronic circuit

Also Published As

Publication number Publication date
US20050108608A1 (en) 2005-05-19
US7210086B2 (en) 2007-04-24
EP1521093A1 (de) 2005-04-06
DE60303168T2 (de) 2006-08-17
EP1521093B1 (de) 2006-01-11

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: QIMONDA AG, 81739 MUENCHEN, DE