DE602008000687D1 - Steuervorrichtung - Google Patents

Steuervorrichtung

Info

Publication number: DE602008000687D1
Authority: DE; Germany
Prior art keywords: control device; control
Prior art date: 2007-06-22
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Active

Application number

DE602008000687T

Other languages

English (en)

Inventor

Hiroshi Nakatani

Yoshito Sameda

Akira Sawada

Jun Takehara

Kouichi Takene

Hiroyuki Nishikawa

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Toshiba Corp

Original Assignee

Toshiba Corp

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

2007-06-22

Filing date

2008-06-20

Publication date

2010-04-08

2008-06-20 Application filed by Toshiba Corp filed Critical Toshiba Corp

2010-04-08 Publication of DE602008000687D1 publication Critical patent/DE602008000687D1/de

Status Active legal-status Critical Current

2028-06-21 Anticipated expiration legal-status Critical

Classifications

- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318555—Control logic
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318572—Input/Output interfaces
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors

Landscapes

Engineering & Computer Science (AREA)
General Engineering & Computer Science (AREA)
Physics & Mathematics (AREA)
General Physics & Mathematics (AREA)
Theoretical Computer Science (AREA)
Computer Hardware Design (AREA)
Quality & Reliability (AREA)
Tests Of Electronic Circuits (AREA)
Test And Diagnosis Of Digital Computers (AREA)

DE602008000687T 2007-06-22 2008-06-20 Steuervorrichtung Active DE602008000687D1 (de)

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
JP2007165288A JP5095273B2 (ja)	2007-06-22	2007-06-22	制御装置

Publications (1)

Publication Number	Publication Date
DE602008000687D1 true DE602008000687D1 (de)	2010-04-08

Family

ID=39737087

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
DE602008000687T Active DE602008000687D1 (de)	2007-06-22	2008-06-20	Steuervorrichtung

Country Status (6)

Country	Link
US (1)	US7870429B2 (de)
EP (1)	EP2006697B1 (de)
JP (1)	JP5095273B2 (de)
KR (1)	KR100989084B1 (de)
CN (1)	CN101329621B (de)
DE (1)	DE602008000687D1 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US7827515B2 (en) *	2007-03-15	2010-11-02	Oracle America, Inc.	Package designs for fully functional and partially functional chips
CN101865976A (zh) *	2009-04-14	2010-10-20	鸿富锦精密工业（深圳）有限公司	边界扫描测试系统及测试方法
DE102010002460A1 (de) *	2010-03-01	2011-09-01	Robert Bosch Gmbh	Verfahren zum Testen eines integrierten Schaltkreises
KR20130031022A (ko) *	2011-09-20	2013-03-28	삼성전자주식회사	Ｄｕｔ 테스트 방법, ｄｕｔ 및 이에 의한 반도체 소자 테스트 시스템
US8538558B1 (en) *	2012-03-01	2013-09-17	Texas Instruments Incorporated	Systems and methods for control with a multi-chip module with multiple dies
JP5873401B2 (ja) *	2012-07-06	2016-03-01	株式会社ケーヒン	電子制御装置及びデータ書換えシステム
JP2015106226A (ja) *	2013-11-29	2015-06-08	三菱電機株式会社	二重化システム
JP6496562B2 (ja) *	2014-04-11	2019-04-03	ルネサスエレクトロニクス株式会社	半導体装置、診断テスト方法及び診断テスト回路
CN106918750A (zh) *	2015-12-24	2017-07-04	英业达科技有限公司	适用于内存插槽的测试电路板
US9791505B1 (en) *	2016-04-29	2017-10-17	Texas Instruments Incorporated	Full pad coverage boundary scan
CN108363615B (zh) *	2017-09-18	2019-05-14	清华大学	用于可重构处理系统的任务分配方法和系统
TWI831410B (zh) *	2022-10-11	2024-02-01	鯨鏈科技股份有限公司	用於晶圓堆疊結構之嵌入式晶片測試裝置

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JPS56149652A (en) *	1980-04-21	1981-11-19	Fujitsu Ltd	Diagnosing system
GB2228114B (en)	1989-02-13	1993-02-10	Westinghouse Brake & Signal	A system comprising a processor
JPH095400A (ja)	1995-06-22	1997-01-10	Matsushita Electric Ind Co Ltd	電子機器
JPH1011319A (ja) *	1996-06-25	1998-01-16	Hitachi Ltd	マルチプロセッサシステムの保守方法
US6115763A (en) *	1998-03-05	2000-09-05	International Business Machines Corporation	Multi-core chip providing external core access with regular operation function interface and predetermined service operation services interface comprising core interface units and masters interface unit
JP2000206202A (ja)	1999-01-20	2000-07-28	Pfu Ltd	簡易型バウンダリスキャン制御装置
US6587979B1 (en) *	1999-10-18	2003-07-01	Credence Systems Corporation	Partitionable embedded circuit test system for integrated circuit
US6557096B1 (en) *	1999-10-25	2003-04-29	Intel Corporation	Processors with data typer and aligner selectively coupling data bits of data buses to adder and multiplier functional blocks to execute instructions with flexible data types
JP2001306343A (ja)	2000-04-21	2001-11-02	Fujitsu I-Network Systems Ltd	Ｆｐｇａを有する装置のためのシステム
JP2002107425A (ja) *	2000-09-29	2002-04-10	Hitachi Ltd	半導体集積回路
US7036064B1 (en) *	2000-11-13	2006-04-25	Omar Kebichi	Synchronization point across different memory BIST controllers
US7139947B2 (en) *	2000-12-22	2006-11-21	Intel Corporation	Test access port
KR20030027989A (ko) *	2001-09-27	2003-04-08	삼성전자주식회사	칩 테스트 장치
KR100405595B1 (ko)	2001-10-31	2003-11-14	엘지전자 주식회사	소자 퓨징 장치
KR100448706B1 (ko) *	2002-07-23	2004-09-13	삼성전자주식회사	단일 칩 시스템 및 이 시스템의 테스트/디버그 방법
US7080283B1 (en) *	2002-10-15	2006-07-18	Tensilica, Inc.	Simultaneous real-time trace and debug for multiple processing core systems on a chip
JP4274806B2 (ja) *	2003-01-28	2009-06-10	株式会社リコー	半導体集積回路およびスキャンテスト法
KR100880832B1 (ko)	2004-02-10	2009-01-30	삼성전자주식회사	코-디버깅 기능을 지원하는 반도체 집적회로 및 반도체집적회로 테스트 시스템
US7685487B1 (en) *	2005-03-22	2010-03-23	Advanced Micro Devices, Inc.	Simultaneous core testing in multi-core integrated circuits
US7536597B2 (en) *	2005-04-27	2009-05-19	Texas Instruments Incorporated	Apparatus and method for controlling power, clock, and reset during test and debug procedures for a plurality of processor/cores
US7475309B2 (en) *	2005-06-30	2009-01-06	Intel Corporation	Parallel test mode for multi-core processors
JP4847734B2 (ja) *	2005-10-31	2011-12-28	ルネサスエレクトロニクス株式会社	半導体集積回路装置、それのデバッグシステム及びデバッグ方法。
US7665002B1 (en) *	2005-12-14	2010-02-16	Advanced Micro Devices, Inc.	Multi-core integrated circuit with shared debug port
US7627794B2 (en) *	2006-05-25	2009-12-01	Mips Technologies, Inc.	Apparatus and method for discrete test access control of multiple cores

2007
- 2007-06-22 JP JP2007165288A patent/JP5095273B2/ja not_active Expired - Fee Related
2008
- 2008-06-18 US US12/141,365 patent/US7870429B2/en not_active Expired - Fee Related
- 2008-06-19 KR KR1020080057702A patent/KR100989084B1/ko not_active Expired - Fee Related
- 2008-06-20 EP EP08011280A patent/EP2006697B1/de not_active Not-in-force
- 2008-06-20 DE DE602008000687T patent/DE602008000687D1/de active Active
- 2008-06-20 CN CN2008101253365A patent/CN101329621B/zh not_active Expired - Fee Related

Also Published As

Publication number	Publication date
JP5095273B2 (ja)	2012-12-12
EP2006697B1 (de)	2010-02-24
CN101329621B (zh)	2010-09-08
JP2009003775A (ja)	2009-01-08
US7870429B2 (en)	2011-01-11
KR100989084B1 (ko)	2010-10-25
EP2006697A1 (de)	2008-12-24
CN101329621A (zh)	2008-12-24
US20080320331A1 (en)	2008-12-25
KR20080112960A (ko)	2008-12-26

Publication	Publication Date	Title
EP2174837A4 (de)	2015-06-03	Betätigungsvorrichtung
EP2206905A4 (de)	2015-10-21	Steuervorrichtung
DK2176504T3 (da)	2019-09-23	Multifunktionelt brøndeftersynsapparat
BRPI0810906A2 (pt)	2014-10-29	Dispositivo baseado em personalidade
DE602008004981D1 (de)	2011-03-31	Fernsteuerungsvorrichtung
BRPI0814324A2 (pt)	2015-01-20	Dispositivo
BRPI0822034A2 (pt)	2015-07-21	Dispositivo
DE112008000048B8 (de)	2019-08-14	Fahrzeugsteuervorrichtung
DE602007014004D1 (de)	2011-06-01	Steuereinheit
HRP20180887T1 (hr)	2018-07-27	Kontrola ektoparazita
DE602008000687D1 (de)	2010-04-08	Steuervorrichtung
IT1393170B1 (it)	2012-04-11	Dispositivo di controllo di contropunta.
DE502008001742D1 (de)	2010-12-23	Kabelbearbeitungseinrichtung
SE0950812L (sv)	2009-12-23	Styrsystem
DE112009000311A5 (de)	2011-03-03	Thermostatische Regeleinrichtung
EP2206603A4 (de)	2010-12-01	Belagsvorrichtung
DE602008003962D1 (de)	2011-01-27	Bediengerät
EP2292495A4 (de)	2014-05-14	Steuergerät
EP2184164A4 (de)	2010-12-01	Überlappungsvorrichtung
DE502007005671D1 (de)	2010-12-30	Schaltvorrichtung
FI20070120A0 (fi)	2007-02-12	Ohjauspuomi
DK2156009T3 (da)	2012-09-17	Forbedret aktiveringsanordning
EP2184166A4 (de)	2010-12-01	Überlappungsvorrichtung
NO20084644L (no)	2010-05-05	Styringsinnretning
ES1065582Y (es)	2007-12-16	Dispositivo de cubrimiento

Legal Events

Date	Code	Title	Description
2011-03-17	8364	No opposition during term of opposition