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DE602007008043D1 - Mehrschichtiges Keramiksubstrat - Google Patents

Mehrschichtiges Keramiksubstrat

Info

Publication number
DE602007008043D1
DE602007008043D1 DE200760008043 DE602007008043T DE602007008043D1 DE 602007008043 D1 DE602007008043 D1 DE 602007008043D1 DE 200760008043 DE200760008043 DE 200760008043 DE 602007008043 T DE602007008043 T DE 602007008043T DE 602007008043 D1 DE602007008043 D1 DE 602007008043D1
Authority
DE
Germany
Prior art keywords
ceramic substrate
multilayer ceramic
multilayer
substrate
ceramic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE200760008043
Other languages
English (en)
Inventor
Yasuharu Miyauchi
Toshiyuki Suzuki
Masaharu Hirakawa
Tomoko Nakamura
Toshinobu Miyakoshi
Kiyoshi Hatanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Corp
Original Assignee
TDK Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TDK Corp filed Critical TDK Corp
Publication of DE602007008043D1 publication Critical patent/DE602007008043D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H10W70/685—
    • H10W70/692—
    • H10W99/00—
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/017—Glass ceramic coating, e.g. formed on inorganic substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1163—Chemical reaction, e.g. heating solder by exothermic reaction
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/30—Details of processes not otherwise provided for in H05K2203/01 - H05K2203/17
    • H05K2203/308—Sacrificial means, e.g. for temporarily filling a space for making a via or a cavity or for making rigid-flexible PCBs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/31504—Composite [nonstructural laminate]
    • Y10T428/31678—Of metal

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
DE200760008043 2006-12-26 2007-12-20 Mehrschichtiges Keramiksubstrat Active DE602007008043D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006350628A JP4279869B2 (ja) 2006-12-26 2006-12-26 多層セラミックス基板

Publications (1)

Publication Number Publication Date
DE602007008043D1 true DE602007008043D1 (de) 2010-09-09

Family

ID=39282678

Family Applications (1)

Application Number Title Priority Date Filing Date
DE200760008043 Active DE602007008043D1 (de) 2006-12-26 2007-12-20 Mehrschichtiges Keramiksubstrat

Country Status (7)

Country Link
US (1) US7662477B2 (de)
EP (1) EP1940210B1 (de)
JP (1) JP4279869B2 (de)
KR (1) KR100922079B1 (de)
CN (1) CN101209929B (de)
DE (1) DE602007008043D1 (de)
TW (1) TW200843603A (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9420707B2 (en) 2009-12-17 2016-08-16 Intel Corporation Substrate for integrated circuit devices including multi-layer glass core and methods of making the same
US8207453B2 (en) 2009-12-17 2012-06-26 Intel Corporation Glass core substrate for integrated circuit devices and methods of making the same
JP5644945B2 (ja) * 2011-06-29 2014-12-24 株式会社村田製作所 多層セラミック基板およびその製造方法
US9445496B2 (en) 2012-03-07 2016-09-13 Intel Corporation Glass clad microelectronic substrate
US9001520B2 (en) 2012-09-24 2015-04-07 Intel Corporation Microelectronic structures having laminated or embedded glass routing structures for high density packaging
JP6624282B2 (ja) * 2016-04-28 2019-12-25 株式会社村田製作所 多層セラミック基板
CN115745577B (zh) * 2022-10-19 2023-09-22 中国建筑材料科学研究总院有限公司 一种超薄低温烧结陶瓷基板的制备方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3322079A1 (de) 1983-06-20 1984-12-20 Cassella Ag, 6000 Frankfurt Tetrahydropyridazinonderivate, verfahren zu ihrer herstellung und ihre verwendung
JPH06237081A (ja) 1993-02-10 1994-08-23 Matsushita Electric Ind Co Ltd 多層セラミック基板の製造方法
JPH09221375A (ja) 1996-02-14 1997-08-26 Sumitomo Metal Ind Ltd セラミックス基板及びその製造方法
JPH11135899A (ja) 1997-10-30 1999-05-21 Kyocera Corp セラミック回路基板
JP2001028474A (ja) 1999-05-12 2001-01-30 Tdk Corp 電子部品及びその製造方法
JP3680684B2 (ja) * 2000-03-06 2005-08-10 株式会社村田製作所 絶縁体磁器、セラミック多層基板、セラミック電子部品及び積層セラミック電子部品
JP3680713B2 (ja) * 2000-07-21 2005-08-10 株式会社村田製作所 絶縁体磁器、セラミック多層基板、セラミック電子部品及び積層セラミック電子部品
JP2002338341A (ja) 2001-05-14 2002-11-27 Ngk Spark Plug Co Ltd 低温焼成磁器及びその製造方法並びに配線基板
JP2003277852A (ja) 2002-03-25 2003-10-02 Kyocera Corp 銅メタライズ組成物およびセラミック配線基板
KR100506731B1 (ko) * 2002-12-24 2005-08-08 삼성전기주식회사 저온 소성 유전체 조성물, 적층 세라믹 커패시터 및세라믹 전자부품
JP2005216998A (ja) 2004-01-28 2005-08-11 Kyocera Corp セラミック回路基板及びその製造方法
JP3929989B2 (ja) 2004-03-29 2007-06-13 京都エレックス株式会社 導電性ペースト及びその導電性ペーストを用いたセラミック多層回路基板。
JP4699769B2 (ja) * 2005-02-02 2011-06-15 日本特殊陶業株式会社 セラミック多層基板の製造方法

Also Published As

Publication number Publication date
CN101209929A (zh) 2008-07-02
KR20080060184A (ko) 2008-07-01
US7662477B2 (en) 2010-02-16
JP4279869B2 (ja) 2009-06-17
EP1940210A3 (de) 2009-07-08
KR100922079B1 (ko) 2009-10-16
US20080152928A1 (en) 2008-06-26
JP2008166307A (ja) 2008-07-17
TWI358982B (de) 2012-02-21
EP1940210A2 (de) 2008-07-02
CN101209929B (zh) 2012-09-05
EP1940210B1 (de) 2010-07-28
TW200843603A (en) 2008-11-01

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