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DE602007006195D1 - Mechanismus zur Erkennung von Datenbusdetektion - Google Patents

Mechanismus zur Erkennung von Datenbusdetektion

Info

Publication number
DE602007006195D1
DE602007006195D1 DE602007006195T DE602007006195T DE602007006195D1 DE 602007006195 D1 DE602007006195 D1 DE 602007006195D1 DE 602007006195 T DE602007006195 T DE 602007006195T DE 602007006195 T DE602007006195 T DE 602007006195T DE 602007006195 D1 DE602007006195 D1 DE 602007006195D1
Authority
DE
Germany
Prior art keywords
data bus
detecting data
bus detection
detection
detecting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602007006195T
Other languages
English (en)
Inventor
Raymond A Bertram
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Via Technologies Inc
Original Assignee
Via Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Via Technologies Inc filed Critical Via Technologies Inc
Publication of DE602007006195D1 publication Critical patent/DE602007006195D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/02—Comparing digital values
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/607—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers number-of-ones counters, i.e. devices for counting the number of input lines set to ONE among a plurality of input lines, also called bit counters or parallel counters

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Computational Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Bus Control (AREA)
  • Debugging And Monitoring (AREA)
  • Manipulation Of Pulses (AREA)
DE602007006195T 2007-09-19 2007-10-12 Mechanismus zur Erkennung von Datenbusdetektion Active DE602007006195D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/857,503 US7668988B2 (en) 2007-09-19 2007-09-19 Data bus inversion detection mechanism

Publications (1)

Publication Number Publication Date
DE602007006195D1 true DE602007006195D1 (de) 2010-06-10

Family

ID=38963239

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602007006195T Active DE602007006195D1 (de) 2007-09-19 2007-10-12 Mechanismus zur Erkennung von Datenbusdetektion

Country Status (5)

Country Link
US (1) US7668988B2 (de)
EP (1) EP2040173B1 (de)
CN (1) CN101241482B (de)
DE (1) DE602007006195D1 (de)
TW (1) TWI358031B (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8581755B2 (en) * 2010-01-20 2013-11-12 Rambus Inc. Multiple word data bus inversion
US8458501B2 (en) * 2010-07-27 2013-06-04 International Business Machines Corporation Measuring data switching activity in a microprocessor
US8677211B2 (en) 2010-12-23 2014-03-18 International Business Machines Corporation Data bus inversion using spare error correction bits
JP5898409B2 (ja) * 2011-03-24 2016-04-06 オリンパス株式会社 データ処理装置およびデータ処理方法
CN102832926B (zh) * 2012-07-17 2015-02-04 宁波大学 一种多位三值低功耗多米诺加法器
JP6050083B2 (ja) * 2012-10-18 2016-12-21 ルネサスエレクトロニクス株式会社 半導体装置
US9058436B1 (en) * 2012-11-20 2015-06-16 Altera Corporation Method and system for reducing the effect of component aging
US10853300B2 (en) * 2017-03-31 2020-12-01 Intel Corporation Low latency statistical data bus inversion for energy reduction
CN112712841B (zh) * 2019-10-25 2024-07-26 长鑫存储技术(上海)有限公司 写操作电路、半导体存储器和写操作方法
CN112181710B (zh) * 2020-09-11 2022-03-29 厦门大学 一种基于比特翻转的固态盘数据存储方法和装置
KR102885357B1 (ko) * 2024-04-11 2025-11-17 광운대학교 산학협력단 pDBI 로직 회로, 이를 포함하는 반도체 장치 및 이를 이용한 pDBI 인코딩 방법

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0444774A3 (de) 1990-01-29 1991-09-11 Raytheon Company Verfahren und Vorrichtung zum Treiben von einem digitalen Bus
US6243779B1 (en) * 1996-11-21 2001-06-05 Integrated Device Technology, Inc. Noise reduction system and method for reducing switching noise in an interface to a large width bus
US6584526B1 (en) 2000-09-21 2003-06-24 Intel Corporation Inserting bus inversion scheme in bus path without increased access latency
US20020156953A1 (en) 2001-02-28 2002-10-24 Beiley Mark A. Dynamic bus inversion method
US6898648B2 (en) 2002-02-21 2005-05-24 Micron Technology, Inc. Memory bus polarity indicator system and method for reducing the affects of simultaneous switching outputs (SSO) on memory bus timing
US20040068594A1 (en) 2002-10-08 2004-04-08 Anthony Asaro Method and apparatus for data bus inversion
US20050132112A1 (en) * 2003-12-10 2005-06-16 Pawlowski J. T. I/O energy reduction using previous bus state and I/O inversion bit for bus inversion
US7406608B2 (en) 2004-02-05 2008-07-29 Micron Technology, Inc. Fast and compact circuit for bus inversion
US7411840B2 (en) 2004-03-02 2008-08-12 Via Technologies, Inc. Sense mechanism for microprocessor bus inversion
US7869525B2 (en) 2005-08-01 2011-01-11 Ati Technologies, Inc. Dynamic bus inversion method and system
KR100643498B1 (ko) 2005-11-21 2006-11-10 삼성전자주식회사 반도체 메모리에서의 데이터 버스 반전 회로 및 데이터버스 반전 방법
US7501963B1 (en) * 2007-10-17 2009-03-10 Micron Technology, Inc. Balanced data bus inversion
US7522073B1 (en) * 2007-11-30 2009-04-21 Qimonda North America Corp. Self-adapted bus inversion

Also Published As

Publication number Publication date
EP2040173A1 (de) 2009-03-25
CN101241482A (zh) 2008-08-13
TWI358031B (en) 2012-02-11
CN101241482B (zh) 2011-07-06
EP2040173B1 (de) 2010-04-28
US20090077286A1 (en) 2009-03-19
US7668988B2 (en) 2010-02-23
TW200915173A (en) 2009-04-01

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