DE602006016256D1 - Verfahren und Anordnung für Cachespeicherverwaltung und entsprechende Prozessorarchitektur - Google Patents
Verfahren und Anordnung für Cachespeicherverwaltung und entsprechende ProzessorarchitekturInfo
- Publication number
- DE602006016256D1 DE602006016256D1 DE602006016256T DE602006016256T DE602006016256D1 DE 602006016256 D1 DE602006016256 D1 DE 602006016256D1 DE 602006016256 T DE602006016256 T DE 602006016256T DE 602006016256 T DE602006016256 T DE 602006016256T DE 602006016256 D1 DE602006016256 D1 DE 602006016256D1
- Authority
- DE
- Germany
- Prior art keywords
- arrangement
- cache management
- processor architecture
- corresponding processor
- architecture
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0877—Cache access modes
- G06F12/0886—Variable-length word access
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP06116248A EP1873648B1 (de) | 2006-06-28 | 2006-06-28 | Verfahren und Anordnung für Cachespeicherverwaltung und entsprechende Prozessorarchitektur |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE602006016256D1 true DE602006016256D1 (de) | 2010-09-30 |
Family
ID=37579709
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE602006016256T Active DE602006016256D1 (de) | 2006-06-28 | 2006-06-28 | Verfahren und Anordnung für Cachespeicherverwaltung und entsprechende Prozessorarchitektur |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US8078804B2 (de) |
| EP (1) | EP1873648B1 (de) |
| DE (1) | DE602006016256D1 (de) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2958765B1 (fr) * | 2010-04-09 | 2012-04-13 | Commissariat Energie Atomique | Memoire cache segmentee. |
| US9772848B2 (en) * | 2014-11-14 | 2017-09-26 | Intel Corporation | Three-dimensional morton coordinate conversion processors, methods, systems, and instructions |
| US9772849B2 (en) | 2014-11-14 | 2017-09-26 | Intel Corporation | Four-dimensional morton coordinate conversion processors, methods, systems, and instructions |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4888679A (en) * | 1988-01-11 | 1989-12-19 | Digital Equipment Corporation | Method and apparatus using a cache and main memory for both vector processing and scalar processing by prefetching cache blocks including vector data elements |
| US5418973A (en) * | 1992-06-22 | 1995-05-23 | Digital Equipment Corporation | Digital computer system with cache controller coordinating both vector and scalar operations |
| US5822606A (en) * | 1996-01-11 | 1998-10-13 | Morton; Steven G. | DSP having a plurality of like processors controlled in parallel by an instruction word, and a control processor also controlled by the instruction word |
| US6496902B1 (en) * | 1998-12-31 | 2002-12-17 | Cray Inc. | Vector and scalar data cache for a vector multiprocessor |
| US6591345B1 (en) * | 2000-11-28 | 2003-07-08 | Hewlett-Packard Development Company, L.P. | Method for ensuring maximum bandwidth on accesses to strided vectors in a bank-interleaved cache |
| ITTO20040415A1 (it) * | 2004-06-22 | 2004-09-22 | St Microelectronics Srl | Architettura di processore multidimensionale |
-
2006
- 2006-06-28 EP EP06116248A patent/EP1873648B1/de active Active
- 2006-06-28 DE DE602006016256T patent/DE602006016256D1/de active Active
-
2007
- 2007-06-26 US US11/768,462 patent/US8078804B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| EP1873648A1 (de) | 2008-01-02 |
| US8078804B2 (en) | 2011-12-13 |
| EP1873648B1 (de) | 2010-08-18 |
| US20080016317A1 (en) | 2008-01-17 |
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