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DE602006000922D1 - Vorrichtung und Verfahren zur Prüfung einer RAM - Google Patents

Vorrichtung und Verfahren zur Prüfung einer RAM

Info

Publication number
DE602006000922D1
DE602006000922D1 DE602006000922T DE602006000922T DE602006000922D1 DE 602006000922 D1 DE602006000922 D1 DE 602006000922D1 DE 602006000922 T DE602006000922 T DE 602006000922T DE 602006000922 T DE602006000922 T DE 602006000922T DE 602006000922 D1 DE602006000922 D1 DE 602006000922D1
Authority
DE
Germany
Prior art keywords
ram
testing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE602006000922T
Other languages
English (en)
Other versions
DE602006000922T2 (de
Inventor
Yoshihiko Satsukawa
Hisashi Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE602006000922D1 publication Critical patent/DE602006000922D1/de
Application granted granted Critical
Publication of DE602006000922T2 publication Critical patent/DE602006000922T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0405—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals comprising complete test loop
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/1208—Error catch memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C2029/3202—Scan chain
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/36—Data generation devices, e.g. data inverters
    • G11C2029/3602—Pattern generator
DE602006000922T 2005-03-25 2006-02-06 Vorrichtung und Verfahren zur Prüfung einer RAM Expired - Lifetime DE602006000922T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005088821A JP4826116B2 (ja) 2005-03-25 2005-03-25 Ｒａｍ試験装置及び試験方法
JP2005088821 2005-03-25

Publications (2)

Publication Number Publication Date
DE602006000922D1 true DE602006000922D1 (de) 2008-05-29
DE602006000922T2 DE602006000922T2 (de) 2009-05-28

Family

ID=36388987

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006000922T Expired - Lifetime DE602006000922T2 (de) 2005-03-25 2006-02-06 Vorrichtung und Verfahren zur Prüfung einer RAM

Country Status (4)

Country Link
US (1) US7536619B2 (de)
EP (1) EP1708205B1 (de)
JP (1) JP4826116B2 (de)
DE (1) DE602006000922T2 (de)

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* Cited by examiner, † Cited by third party
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US7278076B2 (en) * 2004-06-30 2007-10-02 Intel Corporation System and scanout circuits with error resilience circuit
KR20080114359A (ko) * 2007-06-27 2008-12-31 주식회사 하이닉스반도체 반도체 집적 회로 및 그의 불량 경로 검출 방법
JP5014907B2 (ja) * 2007-07-17 2012-08-29 ルネサスエレクトロニクス株式会社 半導体記憶装置及びそのテスト方法
US7719908B1 (en) * 2007-12-21 2010-05-18 Cypress Semiconductor Corporation Memory having read disturb test mode
JP5169597B2 (ja) * 2008-08-01 2013-03-27 富士通セミコンダクター株式会社 集積回路および試験方法
US20090210761A1 (en) * 2008-02-15 2009-08-20 Forlenza Donato O AC Scan Diagnostic Method and Apparatus Utilizing Functional Architecture Verification Patterns
JP2009229135A (ja) * 2008-03-19 2009-10-08 Binteeshisu:Kk テストチップを備えたモジュール
US8627176B2 (en) * 2010-11-30 2014-01-07 Microsoft Corporation Systematic mitigation of memory errors
US9222973B2 (en) 2011-01-20 2015-12-29 International Business Machines Corporation Protecting chip settings using secured scan chains
JP5729148B2 (ja) * 2011-06-07 2015-06-03 東京エレクトロン株式会社 基板搬送容器の開閉装置、蓋体の開閉装置及び半導体製造装置
US8656235B2 (en) * 2011-11-28 2014-02-18 International Business Machines Corporation Verifying and detecting boundary scan cells to input/output mapping
US9081932B2 (en) 2013-02-01 2015-07-14 Qualcomm Incorporated System and method to design and test a yield sensitive circuit
US9460091B2 (en) 2013-11-14 2016-10-04 Elsevier B.V. Computer-program products and methods for annotating ambiguous terms of electronic text documents
US10417363B1 (en) * 2016-12-27 2019-09-17 Cadence Design Systems, Inc. Power and scan resource reduction in integrated circuit designs having shift registers
US10281527B2 (en) * 2017-06-16 2019-05-07 International Business Machines Corporation On-chip hardware-controlled window strobing
US11211136B2 (en) * 2019-06-26 2021-12-28 Micron Technology, Inc. Memory system tester using test pad real time monitoring

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61217839A (ja) * 1985-03-25 1986-09-27 Nec Corp スキヤン方式
KR100234504B1 (ko) * 1995-09-18 1999-12-15 포만 제프리 엘 선택된 고장에 대한 고장정보를 포착하는 집적회로의 테스트 방법 및 내장된 자기 테스트 장치
JPH1139226A (ja) 1997-07-22 1999-02-12 Toshiba Corp 自己テスト回路を内蔵する半導体装置
JP3298621B2 (ja) * 1998-09-02 2002-07-02 日本電気株式会社 組込み自己テスト回路
KR100308621B1 (ko) * 1998-11-19 2001-12-17 윤종용 반도체 메모리 장치를 위한 프로그램 가능한 내장 자기 테스트 시스템
GR990100210A (el) * 1999-06-23 2001-02-28 I.S.D. Ενσωματωμενες δομες αυτοελεγχου και αλγοριθμοι ελεγχου για μνημες τυχαιας προσπελασης
JP2001035196A (ja) * 1999-07-26 2001-02-09 Mitsubishi Electric Corp 故障解析機能を備えた半導体集積回路装置
US6536005B1 (en) * 1999-10-26 2003-03-18 Teradyne, Inc. High-speed failure capture apparatus and method for automatic test equipment
US20020194558A1 (en) * 2001-04-10 2002-12-19 Laung-Terng Wang Method and system to optimize test cost and disable defects for scan and BIST memories
US6988232B2 (en) * 2001-07-05 2006-01-17 Intellitech Corporation Method and apparatus for optimized parallel testing and access of electronic circuits

Also Published As

Publication number Publication date
EP1708205A1 (de) 2006-10-04
US7536619B2 (en) 2009-05-19
DE602006000922T2 (de) 2009-05-28
US20060236178A1 (en) 2006-10-19
EP1708205B1 (de) 2008-04-16
JP4826116B2 (ja) 2011-11-30
JP2006269016A (ja) 2006-10-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE