[go: up one dir, main page]

DE602006009478D1 - Verfahren und vorrichtung für hybride dma-warteschlange und dma-tabelle - Google Patents

Verfahren und vorrichtung für hybride dma-warteschlange und dma-tabelle

Info

Publication number
DE602006009478D1
DE602006009478D1 DE602006009478T DE602006009478T DE602006009478D1 DE 602006009478 D1 DE602006009478 D1 DE 602006009478D1 DE 602006009478 T DE602006009478 T DE 602006009478T DE 602006009478 T DE602006009478 T DE 602006009478T DE 602006009478 D1 DE602006009478 D1 DE 602006009478D1
Authority
DE
Germany
Prior art keywords
dma
hybrid
queue
dma queue
dma table
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE602006009478T
Other languages
English (en)
Inventor
Masakazu Suzuoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Interactive Entertainment Inc
Original Assignee
Sony Computer Entertainment Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Computer Entertainment Inc filed Critical Sony Computer Entertainment Inc
Publication of DE602006009478D1 publication Critical patent/DE602006009478D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
DE602006009478T 2005-02-08 2006-02-07 Verfahren und vorrichtung für hybride dma-warteschlange und dma-tabelle Expired - Lifetime DE602006009478D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/053,509 US7774512B2 (en) 2005-02-08 2005-02-08 Methods and apparatus for hybrid DMA queue and DMA table
PCT/JP2006/302425 WO2006085641A1 (en) 2005-02-08 2006-02-07 Methods and apparatus for hybrid dma queue and dma table

Publications (1)

Publication Number Publication Date
DE602006009478D1 true DE602006009478D1 (de) 2009-11-12

Family

ID=36498754

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006009478T Expired - Lifetime DE602006009478D1 (de) 2005-02-08 2006-02-07 Verfahren und vorrichtung für hybride dma-warteschlange und dma-tabelle

Country Status (6)

Country Link
US (1) US7774512B2 (de)
EP (1) EP1839165B1 (de)
JP (1) JP4421561B2 (de)
CN (1) CN101099140B (de)
DE (1) DE602006009478D1 (de)
WO (1) WO2006085641A1 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7844752B2 (en) * 2005-11-30 2010-11-30 International Business Machines Corporation Method, apparatus and program storage device for enabling multiple asynchronous direct memory access task executions
US20090089515A1 (en) * 2007-10-02 2009-04-02 Qualcomm Incorporated Memory Controller for Performing Memory Block Initialization and Copy
US7827326B2 (en) * 2007-11-26 2010-11-02 Alcatel-Lucent Usa Inc. Method and apparatus for delegation of secure operating mode access privilege from processor to peripheral
JP4542173B2 (ja) * 2008-05-21 2010-09-08 富士通株式会社 ストレージ装置、ディスクコントローラ、及びコマンド発行制御方法
US8352682B2 (en) * 2009-05-26 2013-01-08 Qualcomm Incorporated Methods and apparatus for issuing memory barrier commands in a weakly ordered storage system
US8645589B2 (en) * 2009-08-03 2014-02-04 National Instruments Corporation Methods for data acquisition systems in real time applications
JP5382133B2 (ja) * 2009-11-18 2014-01-08 日本電気株式会社 マルチコアシステム、マルチコアシステムの制御方法及びプログラム
US8495164B2 (en) * 2010-06-07 2013-07-23 Hitachi, Ltd. Data transfer device and data transfer method
US9170954B2 (en) 2012-12-10 2015-10-27 International Business Machines Corporation Translation management instructions for updating address translation data structures in remote processing nodes
US9824004B2 (en) 2013-10-04 2017-11-21 Micron Technology, Inc. Methods and apparatuses for requesting ready status information from a memory
US10108372B2 (en) 2014-01-27 2018-10-23 Micron Technology, Inc. Methods and apparatuses for executing a plurality of queued tasks in a memory
US9454310B2 (en) 2014-02-14 2016-09-27 Micron Technology, Inc. Command queuing
US10552756B2 (en) * 2015-11-12 2020-02-04 University Of Rochester Superconducting system architecture for high-performance energy-efficient cryogenic computing
US10191871B2 (en) * 2017-06-20 2019-01-29 Infineon Technologies Ag Safe double buffering using DMA safe linked lists
US10395698B2 (en) 2017-11-29 2019-08-27 International Business Machines Corporation Address/command chip controlled data chip address sequencing for a distributed memory buffer system
US10534555B2 (en) 2017-11-29 2020-01-14 International Business Machines Corporation Host synchronized autonomous data chip address sequencer for a distributed buffer memory system
US10489069B2 (en) * 2017-11-29 2019-11-26 International Business Machines Corporation Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory system
US10747442B2 (en) 2017-11-29 2020-08-18 International Business Machines Corporation Host controlled data chip address sequencing for a distributed memory buffer system
US11121302B2 (en) 2018-10-11 2021-09-14 SeeQC, Inc. System and method for superconducting multi-chip module
US10606775B1 (en) * 2018-12-28 2020-03-31 Micron Technology, Inc. Computing tile
CN110865953B (zh) * 2019-10-08 2021-01-26 华南师范大学 异步拷贝方法和装置
CN113051199A (zh) * 2019-12-26 2021-06-29 阿里巴巴集团控股有限公司 数据传输方法及装置
US11941131B1 (en) * 2020-12-31 2024-03-26 Meta Platforms Technologies, Llc Isolation of secrets from an operating system

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5717952A (en) * 1994-11-16 1998-02-10 Apple Computer, Inc. DMA controller with mechanism for conditional action under control of status register, prespecified parameters, and condition field of channel command
US5634099A (en) * 1994-12-09 1997-05-27 International Business Machines Corporation Direct memory access unit for transferring data between processor memories in multiprocessing systems
US6154793A (en) * 1997-04-30 2000-11-28 Zilog, Inc. DMA with dynamically assigned channels, flexible block boundary notification and recording, type code checking and updating, commands, and status reporting
US6128674A (en) 1997-08-08 2000-10-03 International Business Machines Corporation Method of minimizing host CPU utilization in driving an adapter by residing in system memory a command/status block a soft interrupt block and a status block queue
CN100440183C (zh) * 2000-09-06 2008-12-03 Nxp股份有限公司 处理器间通信系统
US6874039B2 (en) * 2000-09-08 2005-03-29 Intel Corporation Method and apparatus for distributed direct memory access for systems on chip
US6526491B2 (en) 2001-03-22 2003-02-25 Sony Corporation Entertainment Inc. Memory protection system and method for computer architecture for broadband networks
US6839808B2 (en) * 2001-07-06 2005-01-04 Juniper Networks, Inc. Processing cluster having multiple compute engines and shared tier one caches
CN1246784C (zh) * 2003-02-13 2006-03-22 上海交通大学 带有可重构通道数dma的数字信号处理器
US7200688B2 (en) * 2003-05-29 2007-04-03 International Business Machines Corporation System and method asynchronous DMA command completion notification by accessing register via attached processing unit to determine progress of DMA command
US7243200B2 (en) * 2004-07-15 2007-07-10 International Business Machines Corporation Establishing command order in an out of order DMA command queue

Also Published As

Publication number Publication date
EP1839165B1 (de) 2009-09-30
CN101099140A (zh) 2008-01-02
JP4421561B2 (ja) 2010-02-24
EP1839165A1 (de) 2007-10-03
US7774512B2 (en) 2010-08-10
CN101099140B (zh) 2010-06-16
JP2006221642A (ja) 2006-08-24
WO2006085641A1 (en) 2006-08-17
US20060179179A1 (en) 2006-08-10

Similar Documents

Publication Publication Date Title
DE602006009478D1 (de) Verfahren und vorrichtung für hybride dma-warteschlange und dma-tabelle
DE602006007458D1 (de) Verfahren und vorrichtung zur bohrlochfluidanalyse
DE602007011581D1 (de) Verfahren und vorrichtung für dosenzuschnitt
EP1864032A4 (de) Vorrichtung und verfahren zur kraftumleitung
EP1784931A4 (de) Verfahren und vorrichtung für transparente weiterleitung
EP1973598A4 (de) Verfahren und vorrichtung für lichtaktivierte arzneimitteltherapie
DE602007006380D1 (de) Verfahren und Vorrichtung zur Fahrunterstützung
DE102007039939A8 (de) Verfahren und Vorrichtung zur Einsparung von Diafiltrat
EP2058645A4 (de) Vorrichtung und verfahren zur gasanalyse
DE502007001136D1 (de) Vorrichtung und verfahren zum flexiblen klassieren
DE602006010214D1 (de) Vorrichtung und verfahren für präzisionsbearbeitung
DE602006006454D1 (de) Verfahren und Vorrichtung zur Authentifizierung
DE602007006915D1 (de) Hybrides positionierungsverfahren und vorrichtung
EP1857936A4 (de) Vorrichtung zur informationsverarbeitung und verfahren zur informationsverarbeitung
EP2027252A4 (de) Vorrichtung, system und verfahren für vorortmessungen
DE602007012633D1 (de) Lithographische Vorrichtung und Verfahren
DE502006008563D1 (de) Verfahren und vorrichtung zur fahrerunterstützung
DE112005003619A5 (de) Verfahren und Vorrichtung zur gesundheitlichen Orientierung
DE602007002933D1 (de) Vorrichtung und Verfahren zur Antriebskraftverteilung
DE602006021341D1 (de) Rauchgasnassentschwefelungsvorrichtung und verfahren zur rauchgasnassentschwefelung
DE602006001751D1 (de) Verfahren und Vorrichtung für tiefenbildbasierte Modellierung
DE602006000614D1 (de) Vorrichtung und Verfahren zur Standortbestimmung
DE502006003351D1 (de) Verfahren und vorrichtung zur wankwinkelbestimmung für insassenschutzvorrichtungen
DE602006007206D1 (de) Vorrichtung und Verfahren für eine Benutzerschnittstelle
DE602007001112D1 (de) Verfahren und Vorrichtung zur Formmessung

Legal Events

Date Code Title Description
8364 No opposition during term of opposition