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DE602005006338D1 - Vorrichtung und Verfahren zur Datenübertragungsverarbeitung - Google Patents

Vorrichtung und Verfahren zur Datenübertragungsverarbeitung

Info

Publication number
DE602005006338D1
DE602005006338D1 DE602005006338T DE602005006338T DE602005006338D1 DE 602005006338 D1 DE602005006338 D1 DE 602005006338D1 DE 602005006338 T DE602005006338 T DE 602005006338T DE 602005006338 T DE602005006338 T DE 602005006338T DE 602005006338 D1 DE602005006338 D1 DE 602005006338D1
Authority
DE
Germany
Prior art keywords
data transmission
transmission processing
processing
data
transmission
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE602005006338T
Other languages
English (en)
Other versions
DE602005006338T2 (de
Inventor
Atsushi Kotani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of DE602005006338D1 publication Critical patent/DE602005006338D1/de
Application granted granted Critical
Publication of DE602005006338T2 publication Critical patent/DE602005006338T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
DE602005006338T 2004-04-02 2005-03-31 Vorrichtung und Verfahren zur Datenübertragungsverarbeitung Expired - Fee Related DE602005006338T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004110465 2004-04-02
JP2004110465A JP2005293427A (ja) 2004-04-02 2004-04-02 データ転送処理装置及びデータ転送処理方法

Publications (2)

Publication Number Publication Date
DE602005006338D1 true DE602005006338D1 (de) 2008-06-12
DE602005006338T2 DE602005006338T2 (de) 2009-06-10

Family

ID=34880139

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602005006338T Expired - Fee Related DE602005006338T2 (de) 2004-04-02 2005-03-31 Vorrichtung und Verfahren zur Datenübertragungsverarbeitung

Country Status (4)

Country Link
US (1) US20050223135A1 (de)
EP (1) EP1582989B1 (de)
JP (1) JP2005293427A (de)
DE (1) DE602005006338T2 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7461183B2 (en) * 2004-08-03 2008-12-02 Lsi Corporation Method of processing a context for execution
JP5079342B2 (ja) 2007-01-22 2012-11-21 ルネサスエレクトロニクス株式会社 マルチプロセッサ装置
JP5612807B2 (ja) * 2007-03-13 2014-10-22 セイコーエプソン株式会社 画像送信方式の決定方法、画像供給システム、画像供給装置、プログラム及びコンピュータに読取り可能な記録媒体
JP4909839B2 (ja) * 2007-08-20 2012-04-04 株式会社リコー 画像処理装置及び画像処理方法
US20100169673A1 (en) * 2008-12-31 2010-07-01 Ramakrishna Saripalli Efficient remapping engine utilization
US9569320B2 (en) 2010-12-01 2017-02-14 Seagate Technology Llc Non-volatile memory program failure recovery via redundant arrays
JP5547701B2 (ja) * 2011-09-21 2014-07-16 日立オートモティブシステムズ株式会社 自動車用電子制御装置
US9250666B2 (en) * 2012-11-27 2016-02-02 International Business Machines Corporation Scalable data collection for system management
KR20170056782A (ko) * 2015-11-13 2017-05-24 에스케이하이닉스 주식회사 메모리 시스템 및 메모리 시스템의 동작방법
CN108345551B (zh) * 2017-01-23 2020-05-12 杭州海康威视数字技术股份有限公司 一种存储数据的方法及装置

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0651343B1 (de) * 1988-10-05 2004-04-28 Quickturn Design Systems, Inc. Verfahren zur Verwendung einer elektronisch wiederkonfigurierbaren Gatterfeld-Logik und dadurch hergestelltes Gerät
US4965717A (en) * 1988-12-09 1990-10-23 Tandem Computers Incorporated Multiple processor system having shared memory with private-write capability
US5130981A (en) * 1989-03-22 1992-07-14 Hewlett-Packard Company Three port random access memory in a network bridge
US5852600A (en) * 1995-06-07 1998-12-22 Mci Communications Corporation System and method for resolving substantially simultaneous bi-directional requests of spare capacity
US5781799A (en) * 1995-09-29 1998-07-14 Cirrus Logic, Inc. DMA controller arrangement having plurality of DMA controllers and buffer pool having plurality of buffers accessible to each of the channels of the controllers
US5771359A (en) * 1995-10-13 1998-06-23 Compaq Computer Corporation Bridge having a data buffer for each bus master
JP3712842B2 (ja) * 1997-08-05 2005-11-02 株式会社リコー データ転送制御方法、データ転送制御装置及び情報記録媒体
US6067595A (en) * 1997-09-23 2000-05-23 Icore Technologies, Inc. Method and apparatus for enabling high-performance intelligent I/O subsystems using multi-port memories
US6782465B1 (en) * 1999-10-20 2004-08-24 Infineon Technologies North America Corporation Linked list DMA descriptor architecture
US6862653B1 (en) * 2000-09-18 2005-03-01 Intel Corporation System and method for controlling data flow direction in a memory system
JP3680763B2 (ja) * 2001-05-14 2005-08-10 セイコーエプソン株式会社 データ転送制御装置及び電子機器
US6804741B2 (en) * 2002-01-16 2004-10-12 Hewlett-Packard Development Company, L.P. Coherent memory mapping tables for host I/O bridge
US6922741B2 (en) * 2002-02-01 2005-07-26 Intel Corporation Method and system for monitoring DMA status
DE10214700B4 (de) * 2002-04-03 2006-02-23 Advanced Micro Devices, Inc., Sunnyvale Kombinierter ATA/SATA-Controller als integrierter Schaltkreischip und dazugehöriges Verfahren zum Betreiben
US6981072B2 (en) * 2003-06-05 2005-12-27 International Business Machines Corporation Memory management in multiprocessor system
US8023417B2 (en) * 2004-08-30 2011-09-20 International Business Machines Corporation Failover mechanisms in RDMA operations

Also Published As

Publication number Publication date
DE602005006338T2 (de) 2009-06-10
US20050223135A1 (en) 2005-10-06
EP1582989A1 (de) 2005-10-05
EP1582989B1 (de) 2008-04-30
JP2005293427A (ja) 2005-10-20

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: PANASONIC CORP., KADOMA, OSAKA, JP

8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee