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DE602004009329D1 - Verfahren und system zum selektiven maskieren von testantworten - Google Patents

Verfahren und system zum selektiven maskieren von testantworten

Info

Publication number
DE602004009329D1
DE602004009329D1 DE602004009329T DE602004009329T DE602004009329D1 DE 602004009329 D1 DE602004009329 D1 DE 602004009329D1 DE 602004009329 T DE602004009329 T DE 602004009329T DE 602004009329 T DE602004009329 T DE 602004009329T DE 602004009329 D1 DE602004009329 D1 DE 602004009329D1
Authority
DE
Germany
Prior art keywords
test responses
selectively masking
masking test
responses
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE602004009329T
Other languages
English (en)
Other versions
DE602004009329T2 (de
Inventor
Hendrikus P Vranken
Andreas Glowatz
Friedrich Hapke
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Publication of DE602004009329D1 publication Critical patent/DE602004009329D1/de
Application granted granted Critical
Publication of DE602004009329T2 publication Critical patent/DE602004009329T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G01R31/318547—Data generators or compressors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31719—Security aspects, e.g. preventing unauthorised access during test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318566—Comparators; Diagnosing the device under test

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Investigating Or Analysing Biological Materials (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE602004009329T 2003-09-26 2004-09-20 Verfahren und system zum selektiven maskieren von testantworten Expired - Lifetime DE602004009329T2 (de)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
EP03103575 2003-09-26
EP03103575 2003-09-26
EP04102184 2004-05-18
EP04102184 2004-05-18
PCT/IB2004/051799 WO2005031378A1 (en) 2003-09-26 2004-09-20 Method and system for selectively masking test responses

Publications (2)

Publication Number Publication Date
DE602004009329D1 true DE602004009329D1 (de) 2007-11-15
DE602004009329T2 DE602004009329T2 (de) 2008-07-10

Family

ID=34395292

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004009329T Expired - Lifetime DE602004009329T2 (de) 2003-09-26 2004-09-20 Verfahren und system zum selektiven maskieren von testantworten

Country Status (6)

Country Link
US (1) US7376873B2 (de)
EP (1) EP1671141B1 (de)
JP (1) JP2007506962A (de)
AT (1) ATE374951T1 (de)
DE (1) DE602004009329T2 (de)
WO (1) WO2005031378A1 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7058869B2 (en) * 2003-01-28 2006-06-06 Syntest Technologies, Inc. Method and apparatus for debug, diagnosis, and yield improvement of scan-based integrated circuits
EP1475644A1 (de) * 2003-04-29 2004-11-10 Koninklijke Philips Electronics N.V. Datenkompression
US7032148B2 (en) * 2003-07-07 2006-04-18 Syntest Technologies, Inc. Mask network design for scan-based integrated circuits
US7610527B2 (en) * 2005-03-16 2009-10-27 Nec Laboratories America, Inc. Test output compaction with improved blocking of unknown values
WO2007069098A1 (en) * 2005-11-04 2007-06-21 Nxp B.V. Integrated circuit test method and test apparatus
JP5268656B2 (ja) 2006-02-17 2013-08-21 メンター グラフィックス コーポレイション マルチステージ・テスト応答コンパクタ
JP5034576B2 (ja) * 2006-05-02 2012-09-26 富士通株式会社 半導体集積回路、テストデータ生成装置およびｌｓｉ試験装置
US7788562B2 (en) * 2006-11-29 2010-08-31 Advantest Corporation Pattern controlled, full speed ATE compare capability for deterministic and non-deterministic IC data
WO2008096209A1 (en) * 2007-02-09 2008-08-14 Freescale Semiconductor, Inc. Device and method for testing a circuit
ATE485525T1 (de) * 2007-04-05 2010-11-15 Nxp Bv Prüfbare integrierte schaltung und verfahren zur generierung von testdaten
US7818643B2 (en) * 2008-02-20 2010-10-19 Nec Laboratories America, Inc. Method for blocking unknown values in output response of scan test patterns for testing circuits
US7979763B2 (en) * 2008-10-21 2011-07-12 Synopsys, Inc. Fully X-tolerant, very high scan compression scan test systems and techniques
US8103925B2 (en) * 2008-11-24 2012-01-24 Mentor Graphics Corporation On-chip logic to support compressed X-masking for BIST
US8112686B2 (en) * 2008-12-01 2012-02-07 Mentor Graphics Corporation Deterministic logic built-in self-test stimuli generation
US8898529B2 (en) 2010-05-19 2014-11-25 Universität Potsdam High performance compaction for test responses with many unknowns
US9448282B1 (en) * 2014-02-12 2016-09-20 Cadence Design Systems, Inc. System and method for bit-wise selective masking of scan vectors for X-value tolerant built-in self test
US9599673B2 (en) * 2014-10-15 2017-03-21 Freescale Semiconductor, Inc. Structural testing of integrated circuits
US9470754B1 (en) * 2015-06-11 2016-10-18 Cadence Design Systems, Inc. Elastic compression-optimizing tester bandwidth with compressed test stimuli using overscan and variable serialization
DE102015110144B8 (de) * 2015-06-24 2018-06-28 Infineon Technologies Ag Chip und Verfahren zum Testen einer Verarbeitungskomponente eines Chips
US11422186B1 (en) * 2019-06-20 2022-08-23 Synopsys, Inc. Per-shift X-tolerant logic built-in self-test
US11815555B2 (en) * 2019-09-06 2023-11-14 Siemens Industry Software Inc. Universal compactor architecture for testing circuits
US11320487B1 (en) * 2021-05-26 2022-05-03 Siemens Industry Software Inc. Programmable test compactor for improving defect determination
US11754624B1 (en) 2022-02-24 2023-09-12 Seagate Technology Llc Programmable scan chain debug technique

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2584172B2 (ja) * 1991-08-23 1997-02-19 インターナショナル・ビジネス・マシーンズ・コーポレイション デイジタル試験信号発生回路
US5831992A (en) * 1995-08-17 1998-11-03 Northern Telecom Limited Methods and apparatus for fault diagnosis in self-testable systems
US6311299B1 (en) * 1999-03-01 2001-10-30 Micron Technology, Inc. Data compression circuit and method for testing embedded memory devices
US6557129B1 (en) * 1999-11-23 2003-04-29 Janusz Rajski Method and apparatus for selectively compacting test responses
US7095808B1 (en) * 2000-08-16 2006-08-22 Broadcom Corporation Code puncturing method and apparatus
US7032148B2 (en) * 2003-07-07 2006-04-18 Syntest Technologies, Inc. Mask network design for scan-based integrated circuits
US7210083B2 (en) * 2004-12-16 2007-04-24 Lsi Logic Corporation System and method for implementing postponed quasi-masking test output compression in integrated circuit

Also Published As

Publication number Publication date
JP2007506962A (ja) 2007-03-22
ATE374951T1 (de) 2007-10-15
US7376873B2 (en) 2008-05-20
DE602004009329T2 (de) 2008-07-10
EP1671141B1 (de) 2007-10-03
WO2005031378A1 (en) 2005-04-07
US20070067688A1 (en) 2007-03-22
EP1671141A1 (de) 2006-06-21

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Legal Events

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