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DE602004008911D1 - Verfahren und system um die reihenfolge von paketen mit hilfe eines zwischenspeichers zu gewährleisten - Google Patents

Verfahren und system um die reihenfolge von paketen mit hilfe eines zwischenspeichers zu gewährleisten

Info

Publication number
DE602004008911D1
DE602004008911D1 DE602004008911T DE602004008911T DE602004008911D1 DE 602004008911 D1 DE602004008911 D1 DE 602004008911D1 DE 602004008911 T DE602004008911 T DE 602004008911T DE 602004008911 T DE602004008911 T DE 602004008911T DE 602004008911 D1 DE602004008911 D1 DE 602004008911D1
Authority
DE
Germany
Prior art keywords
packet
sequence
transmitted
packets
received
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE602004008911T
Other languages
English (en)
Other versions
DE602004008911T2 (de
Inventor
Alok Kumar
Raj Yavatkar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE602004008911D1 publication Critical patent/DE602004008911D1/de
Application granted granted Critical
Publication of DE602004008911T2 publication Critical patent/DE602004008911T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/34—Flow control; Congestion control ensuring sequence integrity, e.g. using sequence numbers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/565—Sequence integrity
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding in a switch fabric
    • H04L49/252—Store and forward routing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/55—Prevention, detection or correction of errors
    • H04L49/552—Prevention, detection or correction of errors by ensuring the integrity of packets received through redundant connections

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Security & Cryptography (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Communication Control (AREA)
DE602004008911T 2003-05-28 2004-05-12 Verfahren und system um die reihenfolge von paketen mit hilfe eines zwischenspeichers zu gewährleisten Expired - Lifetime DE602004008911T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US447492 1982-12-06
US10/447,492 US20040240472A1 (en) 2003-05-28 2003-05-28 Method and system for maintenance of packet order using caching
PCT/US2004/014739 WO2004107684A1 (en) 2003-05-28 2004-05-12 Method and system for maintenance of packet order using caching

Publications (2)

Publication Number Publication Date
DE602004008911D1 true DE602004008911D1 (de) 2007-10-25
DE602004008911T2 DE602004008911T2 (de) 2008-06-19

Family

ID=33451244

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004008911T Expired - Lifetime DE602004008911T2 (de) 2003-05-28 2004-05-12 Verfahren und system um die reihenfolge von paketen mit hilfe eines zwischenspeichers zu gewährleisten

Country Status (7)

Country Link
US (1) US20040240472A1 (de)
EP (1) EP1629644B1 (de)
CN (1) CN1306773C (de)
AT (1) ATE373369T1 (de)
DE (1) DE602004008911T2 (de)
TW (1) TWI269163B (de)
WO (1) WO2004107684A1 (de)

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US8176298B2 (en) 2002-10-08 2012-05-08 Netlogic Microsystems, Inc. Multi-core multi-threaded processing systems with instruction reordering in an in-order pipeline
US7961723B2 (en) 2002-10-08 2011-06-14 Netlogic Microsystems, Inc. Advanced processor with mechanism for enforcing ordering between information sent on two independent networks
US9088474B2 (en) 2002-10-08 2015-07-21 Broadcom Corporation Advanced processor with interfacing messaging network to a CPU
US8478811B2 (en) 2002-10-08 2013-07-02 Netlogic Microsystems, Inc. Advanced processor with credit based scheme for optimal packet flow in a multi-processor system on a chip
US8015567B2 (en) 2002-10-08 2011-09-06 Netlogic Microsystems, Inc. Advanced processor with mechanism for packet distribution at high line rate
US8037224B2 (en) 2002-10-08 2011-10-11 Netlogic Microsystems, Inc. Delegating network processor operations to star topology serial bus interfaces
US7924828B2 (en) * 2002-10-08 2011-04-12 Netlogic Microsystems, Inc. Advanced processor with mechanism for fast packet queuing operations
US7984268B2 (en) 2002-10-08 2011-07-19 Netlogic Microsystems, Inc. Advanced processor scheduling in a multithreaded system
US7334086B2 (en) 2002-10-08 2008-02-19 Rmi Corporation Advanced processor with system on a chip interconnect technology
US7346757B2 (en) 2002-10-08 2008-03-18 Rmi Corporation Advanced processor translation lookaside buffer management in a multithreaded system
US7627721B2 (en) 2002-10-08 2009-12-01 Rmi Corporation Advanced processor with cache coherency
US7246205B2 (en) 2004-12-22 2007-07-17 Intel Corporation Software controlled dynamic push cache
GB2427048A (en) 2005-06-09 2006-12-13 Avecho Group Ltd Detection of unwanted code or data in electronic mail
US20070014240A1 (en) * 2005-07-12 2007-01-18 Alok Kumar Using locks to coordinate processing of packets in a flow
CN100459575C (zh) * 2005-11-10 2009-02-04 中国科学院计算技术研究所 一种网络处理器中维护ip分组出入顺序的方法
US9729513B2 (en) 2007-11-08 2017-08-08 Glasswall (Ip) Limited Using multiple layers of policy management to manage risk
GB2444514A (en) 2006-12-04 2008-06-11 Glasswall Electronic file re-generation
US9596324B2 (en) 2008-02-08 2017-03-14 Broadcom Corporation System and method for parsing and allocating a plurality of packets to processor core threads
GB2518880A (en) 2013-10-04 2015-04-08 Glasswall Ip Ltd Anti-Malware mobile content data management apparatus and method
US10193831B2 (en) * 2014-01-30 2019-01-29 Marvell Israel (M.I.S.L) Ltd. Device and method for packet processing with memories having different latencies
CN105227451B (zh) * 2014-06-25 2019-06-21 华为技术有限公司 一种报文处理方法及装置
US9330264B1 (en) 2014-11-26 2016-05-03 Glasswall (Ip) Limited Statistical analytic method for the determination of the risk posed by file based content

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05130141A (ja) * 1991-11-05 1993-05-25 Nec Corp パケツト伝送装置
US5619497A (en) * 1994-12-22 1997-04-08 Emc Corporation Method and apparatus for reordering frames
US5887134A (en) * 1997-06-30 1999-03-23 Sun Microsystems System and method for preserving message order while employing both programmed I/O and DMA operations
CN1125548C (zh) * 2000-01-07 2003-10-22 威盛电子股份有限公司 依序转发包的输出排队方法
US6934280B1 (en) * 2000-05-04 2005-08-23 Nokia, Inc. Multiple services emulation over a single network service
US6862282B1 (en) * 2000-08-29 2005-03-01 Nortel Networks Limited Method and apparatus for packet ordering in a data processing system
US6781992B1 (en) * 2000-11-30 2004-08-24 Netrake Corporation Queue engine for reassembling and reordering data packets in a network
US6751704B2 (en) * 2000-12-07 2004-06-15 International Business Machines Corporation Dual-L2 processor subsystem architecture for networking system
US7327759B2 (en) * 2001-07-25 2008-02-05 International Business Machines Corporation Sequence-preserving deep-packet processing in a multiprocessor system
WO2003021443A1 (en) * 2001-08-31 2003-03-13 Adaptec, Inc. Systems and methods for implementing host-based security in a computer network
US6779050B2 (en) * 2001-09-24 2004-08-17 Broadcom Corporation System and method for hardware based reassembly of a fragmented packet
US7248593B2 (en) * 2001-09-25 2007-07-24 Intel Corporation Method and apparatus for minimizing spinlocks and retaining packet order in systems utilizing multiple transmit queues
EP1454460A1 (de) * 2001-11-13 2004-09-08 Transwitch Corporation Überwindung von zugriffslatenz ineffizienz in speichern für paketvermittelte netzwerke
US7248586B1 (en) * 2001-12-27 2007-07-24 Cisco Technology, Inc. Packet forwarding throughput with partial packet ordering
US20030214949A1 (en) * 2002-05-16 2003-11-20 Nadim Shaikli System for reordering sequenced based packets in a switching network
US6735647B2 (en) * 2002-09-05 2004-05-11 International Business Machines Corporation Data reordering mechanism for high performance networks
US7796602B2 (en) * 2002-11-25 2010-09-14 Intel Corporation In sequence packet delivery without retransmission
US7289508B1 (en) * 2003-03-12 2007-10-30 Juniper Networks, Inc. Systems and methods for processing any-to-any transmissions

Also Published As

Publication number Publication date
ATE373369T1 (de) 2007-09-15
EP1629644B1 (de) 2007-09-12
TWI269163B (en) 2006-12-21
CN1306773C (zh) 2007-03-21
CN1574785A (zh) 2005-02-02
EP1629644A1 (de) 2006-03-01
TW200500858A (en) 2005-01-01
WO2004107684A1 (en) 2004-12-09
DE602004008911T2 (de) 2008-06-19
US20040240472A1 (en) 2004-12-02

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