DE60127524D1 - Cachespeicher für arithmetische Rechneroperationen mit partieller Resultatsausgabe bei partieller Operandenübereinstimmung - Google Patents
Cachespeicher für arithmetische Rechneroperationen mit partieller Resultatsausgabe bei partieller OperandenübereinstimmungInfo
- Publication number
- DE60127524D1 DE60127524D1 DE60127524T DE60127524T DE60127524D1 DE 60127524 D1 DE60127524 D1 DE 60127524D1 DE 60127524 T DE60127524 T DE 60127524T DE 60127524 T DE60127524 T DE 60127524T DE 60127524 D1 DE60127524 D1 DE 60127524D1
- Authority
- DE
- Germany
- Prior art keywords
- partial
- cache
- result output
- arithmetic calculator
- operand match
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Computing Systems (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US757789 | 1991-09-11 | ||
| US09/757,789 US6542963B2 (en) | 2001-01-10 | 2001-01-10 | Partial match partial output cache for computer arithmetic operations |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE60127524D1 true DE60127524D1 (de) | 2007-05-10 |
| DE60127524T2 DE60127524T2 (de) | 2008-01-31 |
Family
ID=25049225
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE60127524T Expired - Lifetime DE60127524T2 (de) | 2001-01-10 | 2001-02-09 | Cachespeicher für arithmetische Rechenoperationen mit partieller Resultatsausgabe bei partieller Operandenübereinstimmung |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US6542963B2 (de) |
| EP (1) | EP1223505B1 (de) |
| JP (1) | JP4574030B2 (de) |
| KR (1) | KR100423893B1 (de) |
| CN (1) | CN1194301C (de) |
| DE (1) | DE60127524T2 (de) |
| TW (1) | TW501026B (de) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050108368A1 (en) * | 2003-10-30 | 2005-05-19 | Aditya Mohan | Method and apparatus for representing data available in a peer-to-peer network using bloom-filters |
| DE102004019967B4 (de) * | 2004-04-23 | 2014-02-13 | Rohde & Schwarz Gmbh & Co. Kg | Signalverarbeitungseinrichtung mit Nachverarbeitung |
| US9189412B2 (en) * | 2013-03-07 | 2015-11-17 | Mips Technologies, Inc. | Apparatus and method for operating a processor with an operation cache |
| US10514928B2 (en) | 2014-04-17 | 2019-12-24 | Arm Limited | Preventing duplicate execution by sharing a result between different processing lanes assigned micro-operations that generate the same result |
| US9933841B2 (en) | 2014-04-17 | 2018-04-03 | Arm Limited | Reuse of results of back-to-back micro-operations |
| US9817466B2 (en) | 2014-04-17 | 2017-11-14 | Arm Limited | Power saving by reusing results of identical micro-operations |
| GB2525263B (en) * | 2014-04-17 | 2021-06-02 | Advanced Risc Mach Ltd | Reuse of results of back-to-back micro-operations |
| US9946331B2 (en) * | 2014-06-27 | 2018-04-17 | Samsung Electronics Co., Ltd. | System and method to process signals having a common component |
| GB2528497B (en) * | 2014-07-24 | 2021-06-16 | Advanced Risc Mach Ltd | Apparatus And Method For Performing Floating-Point Square Root Operation |
| US10261911B2 (en) * | 2016-09-08 | 2019-04-16 | The Johns Hopkins University | Apparatus and method for computational workflow management |
| US11269643B2 (en) | 2017-04-09 | 2022-03-08 | Intel Corporation | Data operations and finite state machine for machine learning via bypass of computational tasks based on frequently-used data values |
| JP7143866B2 (ja) | 2020-03-25 | 2022-09-29 | カシオ計算機株式会社 | キャッシュ管理プログラム、サーバ、キャッシュ管理方法、および情報処理装置 |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4734878A (en) | 1985-10-31 | 1988-03-29 | General Electric Company | Circuit for performing square root functions |
| JP2613223B2 (ja) * | 1987-09-10 | 1997-05-21 | 株式会社日立製作所 | 演算装置 |
| CA2074769C (en) * | 1991-08-09 | 2001-03-20 | International Business Machines Corporation | Formula processor |
| US5260898A (en) * | 1992-03-13 | 1993-11-09 | Sun Microsystems, Inc. | Result cache for complex arithmetic units |
| US5828591A (en) * | 1992-11-02 | 1998-10-27 | Intel Corporation | Method and apparatus for using a cache memory to store and retrieve intermediate and final results |
| US5537560A (en) * | 1994-03-01 | 1996-07-16 | Intel Corporation | Method and apparatus for conditionally generating a microinstruction that selects one of two values based upon control states of a microprocessor |
| US5845103A (en) * | 1997-06-13 | 1998-12-01 | Wisconsin Alumni Research Foundation | Computer with dynamic instruction reuse |
| WO1999045463A1 (fr) * | 1998-03-04 | 1999-09-10 | Hitachi, Ltd. | Processeur de donnees |
| US6253287B1 (en) * | 1998-09-09 | 2001-06-26 | Advanced Micro Devices, Inc. | Using three-dimensional storage to make variable-length instructions appear uniform in two dimensions |
| US6298369B1 (en) * | 1998-09-30 | 2001-10-02 | Stmicroelectronics, Inc. | High speed multiplier |
| US6343359B1 (en) * | 1999-05-18 | 2002-01-29 | Ip-First, L.L.C. | Result forwarding cache |
-
2001
- 2001-01-10 US US09/757,789 patent/US6542963B2/en not_active Expired - Lifetime
- 2001-01-26 KR KR10-2001-0003728A patent/KR100423893B1/ko not_active Expired - Fee Related
- 2001-02-07 JP JP2001031314A patent/JP4574030B2/ja not_active Expired - Fee Related
- 2001-02-09 EP EP01301168A patent/EP1223505B1/de not_active Expired - Lifetime
- 2001-02-09 CN CNB011119861A patent/CN1194301C/zh not_active Expired - Lifetime
- 2001-02-09 DE DE60127524T patent/DE60127524T2/de not_active Expired - Lifetime
- 2001-02-13 TW TW090103096A patent/TW501026B/zh not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR100423893B1 (ko) | 2004-03-24 |
| CN1365049A (zh) | 2002-08-21 |
| EP1223505A2 (de) | 2002-07-17 |
| US6542963B2 (en) | 2003-04-01 |
| EP1223505A3 (de) | 2004-06-16 |
| EP1223505B1 (de) | 2007-03-28 |
| CN1194301C (zh) | 2005-03-23 |
| TW501026B (en) | 2002-09-01 |
| JP2002229775A (ja) | 2002-08-16 |
| KR20020060547A (ko) | 2002-07-18 |
| DE60127524T2 (de) | 2008-01-31 |
| JP4574030B2 (ja) | 2010-11-04 |
| US20020120814A1 (en) | 2002-08-29 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition |