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DE60045416D1 - Verfahren zur behandlung von mikroelektroniksubstraten - Google Patents

Verfahren zur behandlung von mikroelektroniksubstraten

Info

Publication number
DE60045416D1
DE60045416D1 DE60045416T DE60045416T DE60045416D1 DE 60045416 D1 DE60045416 D1 DE 60045416D1 DE 60045416 T DE60045416 T DE 60045416T DE 60045416 T DE60045416 T DE 60045416T DE 60045416 D1 DE60045416 D1 DE 60045416D1
Authority
DE
Germany
Prior art keywords
microelectronic substrates
treating microelectronic
treating
substrates
microelectronic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60045416T
Other languages
English (en)
Inventor
Thierry Barge
Andre Auberton-Herve
Hiroji Aga
Naoto Tate
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Application granted granted Critical
Publication of DE60045416D1 publication Critical patent/DE60045416D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H10P95/90—
    • H10P95/906—
    • H10P50/00—
    • H10P52/402—
    • H10P90/1914—
    • H10W10/181—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/974—Substrate surface preparation
DE60045416T 1999-08-20 2000-08-17 Verfahren zur behandlung von mikroelektroniksubstraten Expired - Lifetime DE60045416D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9910667A FR2797713B1 (fr) 1999-08-20 1999-08-20 Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede
PCT/FR2000/002330 WO2001015215A1 (fr) 1999-08-20 2000-08-17 Procede de traitement de substrats pour la micro-electronique et substrats obtenus par ce procede

Publications (1)

Publication Number Publication Date
DE60045416D1 true DE60045416D1 (de) 2011-02-03

Family

ID=9549260

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60045416T Expired - Lifetime DE60045416D1 (de) 1999-08-20 2000-08-17 Verfahren zur behandlung von mikroelektroniksubstraten

Country Status (9)

Country Link
US (2) US7029993B1 (de)
EP (1) EP1208589B1 (de)
JP (2) JP2003509838A (de)
KR (1) KR100764978B1 (de)
DE (1) DE60045416D1 (de)
FR (1) FR2797713B1 (de)
MY (1) MY133102A (de)
TW (1) TW515000B (de)
WO (1) WO2001015215A1 (de)

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FR2840731B3 (fr) * 2002-06-11 2004-07-30 Soitec Silicon On Insulator Procede de fabrication d'un substrat comportant une couche utile en materiau semi-conducteur monocristallin de proprietes ameliorees
FR2894990B1 (fr) * 2005-12-21 2008-02-22 Soitec Silicon On Insulator Procede de fabrication de substrats, notamment pour l'optique,l'electronique ou l'optoelectronique et substrat obtenu selon ledit procede
US8507361B2 (en) 2000-11-27 2013-08-13 Soitec Fabrication of substrates with a useful layer of monocrystalline semiconductor material
US7883628B2 (en) 2001-07-04 2011-02-08 S.O.I.Tec Silicon On Insulator Technologies Method of reducing the surface roughness of a semiconductor wafer
FR2827078B1 (fr) * 2001-07-04 2005-02-04 Soitec Silicon On Insulator Procede de diminution de rugosite de surface
US7749910B2 (en) 2001-07-04 2010-07-06 S.O.I.Tec Silicon On Insulator Technologies Method of reducing the surface roughness of a semiconductor wafer
FR2827423B1 (fr) 2001-07-16 2005-05-20 Soitec Silicon On Insulator Procede d'amelioration d'etat de surface
US7189606B2 (en) * 2002-06-05 2007-03-13 Micron Technology, Inc. Method of forming fully-depleted (FD) SOI MOSFET access transistor
US6953736B2 (en) 2002-07-09 2005-10-11 S.O.I.Tec Silicon On Insulator Technologies S.A. Process for transferring a layer of strained semiconductor material
EP2190010A2 (de) 2002-08-12 2010-05-26 S.O.I. Tec Silicon on Insulator Technologies Verfahren zur Herstellung einer Dünnschicht aus Halbleitermaterial
FR2845202B1 (fr) * 2002-10-01 2004-11-05 Soitec Silicon On Insulator Procede de recuit rapide de tranches de materiau semiconducteur.
KR100874788B1 (ko) * 2003-01-07 2008-12-18 에스. 오. 이. 떼끄 씰리꽁 오 냉쉴라또흐 떼끄놀로지 박층 박리 후에 박리 구조를 포함하는 웨이퍼의 기계적수단에 의한 재활용 방법
JP4407127B2 (ja) * 2003-01-10 2010-02-03 信越半導体株式会社 Ｓｏｉウエーハの製造方法
DE60336543D1 (de) 2003-05-27 2011-05-12 Soitec Silicon On Insulator Verfahren zur Herstellung einer heteroepitaktischen Mikrostruktur
FR2858462B1 (fr) 2003-07-29 2005-12-09 Soitec Silicon On Insulator Procede d'obtention d'une couche mince de qualite accrue par co-implantation et recuit thermique
JP2007500435A (ja) * 2003-07-29 2007-01-11 エス．オー．アイ．テック、シリコン、オン、インシュレター、テクノロジーズ 共注入と熱アニールによって特性の改善された薄層を得るための方法
JP4552856B2 (ja) * 2003-09-05 2010-09-29 株式会社Ｓｕｍｃｏ Ｓｏｉウェーハの作製方法
FR2867607B1 (fr) 2004-03-10 2006-07-14 Soitec Silicon On Insulator Procede de fabrication d'un substrat pour la microelectronique, l'opto-electronique et l'optique avec limitaton des lignes de glissement et substrat correspondant
KR101111436B1 (ko) * 2004-09-13 2012-02-15 신에쯔 한도타이 가부시키가이샤 Ｓｏｉ 웨이퍼의 제조 방법 및 ｓｏｉ 웨이퍼
JP4826994B2 (ja) * 2004-09-13 2011-11-30 信越半導体株式会社 Ｓｏｉウェーハの製造方法
JP4696510B2 (ja) * 2004-09-15 2011-06-08 信越半導体株式会社 Ｓｏｉウェーハの製造方法
KR101134485B1 (ko) * 2004-09-21 2012-04-24 소이텍 공동 주입 및 후속 주입에 의해 박막을 획득하는 방법
ATE441206T1 (de) * 2004-12-28 2009-09-15 Soitec Silicon On Insulator Verfahren zum erhalten einer dünnen schicht mit einer geringen dichte von líchern
FR2880988B1 (fr) 2005-01-19 2007-03-30 Soitec Silicon On Insulator TRAITEMENT D'UNE COUCHE EN SI1-yGEy PRELEVEE
FR2881573B1 (fr) * 2005-01-31 2008-07-11 Soitec Silicon On Insulator Procede de transfert d'une couche mince formee dans un substrat presentant des amas de lacunes
JP2006279015A (ja) * 2005-03-02 2006-10-12 Seiko Epson Corp 半導体装置の製造方法、集積回路、電気光学装置、及び電子機器
FR2884647B1 (fr) 2005-04-15 2008-02-22 Soitec Silicon On Insulator Traitement de plaques de semi-conducteurs
FR2895563B1 (fr) 2005-12-22 2008-04-04 Soitec Silicon On Insulator Procede de simplification d'une sequence de finition et structure obtenue par le procede
EP2097923A1 (de) * 2006-12-28 2009-09-09 MEMC Electronic Materials, Inc. Verfahren zur herstellung glatter wafer
FR2912258B1 (fr) * 2007-02-01 2009-05-08 Soitec Silicon On Insulator "procede de fabrication d'un substrat du type silicium sur isolant"
FR2912259B1 (fr) 2007-02-01 2009-06-05 Soitec Silicon On Insulator Procede de fabrication d'un substrat du type "silicium sur isolant".
JP5125194B2 (ja) * 2007-04-10 2013-01-23 信越半導体株式会社 貼り合わせウエーハの製造方法
JP5135935B2 (ja) 2007-07-27 2013-02-06 信越半導体株式会社 貼り合わせウエーハの製造方法
JP5654206B2 (ja) * 2008-03-26 2015-01-14 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法及び該ｓｏｉ基板を用いた半導体装置
JP2009260315A (ja) * 2008-03-26 2009-11-05 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法及び半導体装置の作製方法
FR2929758B1 (fr) 2008-04-07 2011-02-11 Commissariat Energie Atomique Procede de transfert a l'aide d'un substrat ferroelectrique
EP2161741B1 (de) * 2008-09-03 2014-06-11 Soitec Verfahren zur Herstellung eines Halbleiters auf einem Isoliersubstrat mit verringerter SECCO-Fehlerdichte
FR2938119B1 (fr) * 2008-10-30 2011-04-22 Soitec Silicon On Insulator Procede de detachement de couches semi-conductrices a basse temperature
EP2368264A1 (de) * 2008-11-26 2011-09-28 MEMC Electronic Materials, Inc. Verfahren zum verarbeiten einer silizium-auf-isolator-struktur
FR2943458B1 (fr) * 2009-03-18 2011-06-10 Soitec Silicon On Insulator Procede de finition d'un substrat de type "silicium sur isolant" soi
WO2010109712A1 (ja) * 2009-03-25 2010-09-30 シャープ株式会社 半導体装置用の絶縁基板、及び、半導体装置
FR2987166B1 (fr) 2012-02-16 2017-05-12 Soitec Silicon On Insulator Procede de transfert d'une couche
JP5096634B2 (ja) * 2012-06-14 2012-12-12 ソイテック 低いホール密度を有する薄層を得るための方法
EP2685297B1 (de) * 2012-07-13 2017-12-06 Huawei Technologies Co., Ltd. Verfahren zur Herstellung einer photonischen Schaltung mit aktiven und passiven Strukturen
US9064077B2 (en) 2012-11-28 2015-06-23 Qualcomm Incorporated 3D floorplanning using 2D and 3D blocks
US9098666B2 (en) 2012-11-28 2015-08-04 Qualcomm Incorporated Clock distribution network for 3D integrated circuit
US9536840B2 (en) 2013-02-12 2017-01-03 Qualcomm Incorporated Three-dimensional (3-D) integrated circuits (3DICS) with graphene shield, and related components and methods
US9041448B2 (en) 2013-03-05 2015-05-26 Qualcomm Incorporated Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC) (3DIC) and related methods
US9177890B2 (en) 2013-03-07 2015-11-03 Qualcomm Incorporated Monolithic three dimensional integration of semiconductor integrated circuits
US9171608B2 (en) 2013-03-15 2015-10-27 Qualcomm Incorporated Three-dimensional (3D) memory cell separation among 3D integrated circuit (IC) tiers, and related 3D integrated circuits (3DICS), 3DIC processor cores, and methods
DE102015106441B4 (de) * 2015-04-27 2022-01-27 Infineon Technologies Ag Verfahren zum Planarisieren eines Halbleiterwafers
KR102424963B1 (ko) 2015-07-30 2022-07-25 삼성전자주식회사 집적회로 소자 및 그 제조 방법
FR3146018B1 (fr) * 2023-02-16 2025-12-26 Soitec Silicon On Insulator Procédé de réduction de la concentration en bore d’une couche semi-conductrice

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JPH05102112A (ja) * 1991-10-04 1993-04-23 Kyushu Electron Metal Co Ltd 半導体シリコンウエーハの製造方法
EP0553852B1 (de) 1992-01-30 2003-08-20 Canon Kabushiki Kaisha Verfahren zur Herstellung eines Halbleitersubstrates
JP2994837B2 (ja) 1992-01-31 1999-12-27 キヤノン株式会社 半導体基板の平坦化方法、半導体基板の作製方法、及び半導体基板
US5589422A (en) * 1993-01-15 1996-12-31 Intel Corporation Controlled, gas phase process for removal of trace metal contamination and for removal of a semiconductor layer
JPH09260620A (ja) * 1996-03-25 1997-10-03 Shin Etsu Handotai Co Ltd 結合ウエーハの製造方法およびこの方法で製造される結合ウエーハ
FR2748851B1 (fr) 1996-05-15 1998-08-07 Commissariat Energie Atomique Procede de realisation d'une couche mince de materiau semiconducteur
JP3660469B2 (ja) * 1996-07-05 2005-06-15 日本電信電話株式会社 Ｓｏｉ基板の製造方法
JP3522482B2 (ja) 1997-02-24 2004-04-26 三菱住友シリコン株式会社 Ｓｏｉ基板の製造方法
JPH10275905A (ja) * 1997-03-31 1998-10-13 Mitsubishi Electric Corp シリコンウェーハの製造方法およびシリコンウェーハ
JP3346249B2 (ja) * 1997-10-30 2002-11-18 信越半導体株式会社 シリコンウエーハの熱処理方法及びシリコンウエーハ
JP3451908B2 (ja) * 1997-11-05 2003-09-29 信越半導体株式会社 Ｓｏｉウエーハの熱処理方法およびｓｏｉウエーハ
JP2998724B2 (ja) * 1997-11-10 2000-01-11 日本電気株式会社 張り合わせｓｏｉ基板の製造方法
JPH11195774A (ja) * 1997-12-26 1999-07-21 Canon Inc 半導体基板の作成方法
FR2774510B1 (fr) 1998-02-02 2001-10-26 Soitec Silicon On Insulator Procede de traitement de substrats, notamment semi-conducteurs
FR2777115B1 (fr) 1998-04-07 2001-07-13 Commissariat Energie Atomique Procede de traitement de substrats semi-conducteurs et structures obtenues par ce procede
AU3488699A (en) * 1998-04-10 1999-11-01 Silicon Genesis Corporation Surface treatment process and system
US6287941B1 (en) * 1999-04-21 2001-09-11 Silicon Genesis Corporation Surface finishing of SOI substrates using an EPI process

Also Published As

Publication number Publication date
US7029993B1 (en) 2006-04-18
EP1208589A1 (de) 2002-05-29
WO2001015215A1 (fr) 2001-03-01
FR2797713A1 (fr) 2001-02-23
KR20020026375A (ko) 2002-04-09
US7288418B2 (en) 2007-10-30
JP2003509838A (ja) 2003-03-11
EP1208589B1 (de) 2010-12-22
FR2797713B1 (fr) 2002-08-02
TW515000B (en) 2002-12-21
JP2012104839A (ja) 2012-05-31
MY133102A (en) 2007-10-31
KR100764978B1 (ko) 2007-10-09
US20060189102A1 (en) 2006-08-24

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