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DE60042640D1 - Datenprozessor mit cachespeicher - Google Patents

Datenprozessor mit cachespeicher

Info

Publication number
DE60042640D1
DE60042640D1 DE60042640T DE60042640T DE60042640D1 DE 60042640 D1 DE60042640 D1 DE 60042640D1 DE 60042640 T DE60042640 T DE 60042640T DE 60042640 T DE60042640 T DE 60042640T DE 60042640 D1 DE60042640 D1 DE 60042640D1
Authority
DE
Germany
Prior art keywords
cache memory
data processor
processor
cache
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60042640T
Other languages
English (en)
Inventor
Adwin H Timmer
Francoise J Harmsze
Jeroen A Leijten
Meerbergen Jozef L Van
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Application granted granted Critical
Publication of DE60042640D1 publication Critical patent/DE60042640D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0848—Partitioned cache, e.g. separate instruction and operand caches
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE60042640T 1999-12-17 2000-12-04 Datenprozessor mit cachespeicher Expired - Lifetime DE60042640D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP99204375 1999-12-17
PCT/EP2000/012231 WO2001044948A1 (en) 1999-12-17 2000-12-04 Data processor with cache

Publications (1)

Publication Number Publication Date
DE60042640D1 true DE60042640D1 (de) 2009-09-10

Family

ID=8241020

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60042640T Expired - Lifetime DE60042640D1 (de) 1999-12-17 2000-12-04 Datenprozessor mit cachespeicher

Country Status (7)

Country Link
US (1) US6643738B2 (de)
EP (1) EP1157336B1 (de)
JP (1) JP2003517682A (de)
KR (1) KR100810781B1 (de)
CN (1) CN1206594C (de)
DE (1) DE60042640D1 (de)
WO (1) WO2001044948A1 (de)

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JP4457185B2 (ja) * 2001-02-13 2010-04-28 ネットアップ，インコーポレイテッド シリコンベースのストレージ仮想化サーバ
US6933945B2 (en) * 2003-03-31 2005-08-23 Sun Microsystems, Inc. Design for a non-blocking cache for texture mapping
US7063151B2 (en) * 2004-03-05 2006-06-20 Halliburton Energy Services, Inc. Methods of preparing and using coated particulates
US7644239B2 (en) 2004-05-03 2010-01-05 Microsoft Corporation Non-volatile memory cache performance improvement
US7558920B2 (en) * 2004-06-30 2009-07-07 Intel Corporation Apparatus and method for partitioning a shared cache of a chip multi-processor
US7475190B2 (en) * 2004-10-08 2009-01-06 International Business Machines Corporation Direct access of cache lock set data without backing memory
US7490197B2 (en) 2004-10-21 2009-02-10 Microsoft Corporation Using external memory devices to improve system performance
US8443162B2 (en) 2005-01-21 2013-05-14 Qualcomm Incorporated Methods and apparatus for dynamically managing banked memory
US8914557B2 (en) 2005-12-16 2014-12-16 Microsoft Corporation Optimizing write and wear performance for a memory
US7836435B2 (en) * 2006-03-31 2010-11-16 Intel Corporation Checking for memory access collisions in a multi-processor architecture
US7574564B2 (en) * 2006-05-11 2009-08-11 Freescale Semiconductor, Inc. Replacement pointer control for set associative cache and method
JP5245349B2 (ja) * 2007-10-17 2013-07-24 日本電気株式会社 登録先ウェイの固定方法、プロセッサ、及び情報処理装置
US8631203B2 (en) * 2007-12-10 2014-01-14 Microsoft Corporation Management of external memory functioning as virtual cache
ES2304118B1 (es) * 2008-02-25 2009-07-29 Sener Grupo De Ingenieria, S.A Procedimiento para generar energia mediante ciclos termicos con vapor de presion elevada y temperatura moderada.
US9032151B2 (en) * 2008-09-15 2015-05-12 Microsoft Technology Licensing, Llc Method and system for ensuring reliability of cache data and metadata subsequent to a reboot
US8032707B2 (en) 2008-09-15 2011-10-04 Microsoft Corporation Managing cache data and metadata
US7953774B2 (en) 2008-09-19 2011-05-31 Microsoft Corporation Aggregation of write traffic to a data store
EP3540059A1 (de) 2010-04-16 2019-09-18 Nuevolution A/S Bifunktionelle komplexe und verfahren zur herstellung sowie verwendung derartiger komplexe
US20120144118A1 (en) * 2010-12-07 2012-06-07 Advanced Micro Devices, Inc. Method and apparatus for selectively performing explicit and implicit data line reads on an individual sub-cache basis
CN102521161B (zh) * 2011-11-21 2015-01-21 华为技术有限公司 一种数据的缓存方法、装置和服务器
US10961920B2 (en) 2018-10-02 2021-03-30 8 Rivers Capital, Llc Control systems and methods suitable for use with power production systems and methods
US10333503B1 (en) 2018-11-26 2019-06-25 Quantum Machines Quantum controller with modular and dynamic pulse generation and routing
US10454459B1 (en) 2019-01-14 2019-10-22 Quantum Machines Quantum controller with multiple pulse modes
US11164100B2 (en) 2019-05-02 2021-11-02 Quantum Machines Modular and dynamic digital control in a quantum controller
US10931267B1 (en) 2019-07-31 2021-02-23 Quantum Machines Frequency generation in a quantum controller
US11245390B2 (en) 2019-09-02 2022-02-08 Quantum Machines Software-defined pulse orchestration platform
US10862465B1 (en) 2019-09-02 2020-12-08 Quantum Machines Quantum controller architecture
US11126926B1 (en) * 2020-03-09 2021-09-21 Quantum Machines Concurrent results processing in a quantum control system
US11043939B1 (en) 2020-08-05 2021-06-22 Quantum Machines Frequency management for quantum control
US12132486B2 (en) 2021-04-08 2024-10-29 Quantum Machines System and method for pulse generation during quantum operations
US11671180B2 (en) 2021-04-28 2023-06-06 Quantum Machines System and method for communication between quantum controller modules
US12242406B2 (en) 2021-05-10 2025-03-04 Q.M Technologies Ltd. System and method for processing between a plurality of quantum controllers
US12165011B2 (en) 2021-06-19 2024-12-10 Q.M Technologies Ltd. Error detection mechanism for quantum bits
US12332682B2 (en) 2021-07-21 2025-06-17 Q.M Technologies Ltd. System and method for clock synchronization and time transfer between quantum orchestration platform elements
US12111352B2 (en) 2022-01-24 2024-10-08 Quantum Machines Machine learning for syncing multiple FPGA ports in a quantum system
US12488275B1 (en) 2022-05-10 2025-12-02 Q.M Technologies Ltd. Buffering the control of a quantum device

Family Cites Families (12)

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Publication number Priority date Publication date Assignee Title
US5070502A (en) * 1989-06-23 1991-12-03 Digital Equipment Corporation Defect tolerant set associative cache
US5450564A (en) * 1990-05-04 1995-09-12 Unisys Corporation Method and apparatus for cache memory access with separate fetch and store queues
US5353424A (en) * 1991-11-19 1994-10-04 Digital Equipment Corporation Fast tag compare and bank select in set associative cache
US5509135A (en) * 1992-09-25 1996-04-16 Digital Equipment Corporation Multi-index multi-way set-associative cache
US5761706A (en) * 1994-11-01 1998-06-02 Cray Research, Inc. Stream buffers for high-performance computer memory system
US6047357A (en) * 1995-01-27 2000-04-04 Digital Equipment Corporation High speed method for maintaining cache coherency in a multi-level, set associative cache hierarchy
US5732242A (en) * 1995-03-24 1998-03-24 Silicon Graphics, Inc. Consistently specifying way destinations through prefetching hints
US5715427A (en) * 1996-01-26 1998-02-03 International Business Machines Corporation Semi-associative cache with MRU/LRU replacement
JPH09259041A (ja) * 1996-03-27 1997-10-03 Hitachi Ltd キャッシュメモリ制御方式
US5829028A (en) * 1996-05-06 1998-10-27 Advanced Micro Devices, Inc. Data cache configured to store data in a use-once manner
GB9701960D0 (en) * 1997-01-30 1997-03-19 Sgs Thomson Microelectronics A cache system
US6016533A (en) * 1997-12-16 2000-01-18 Advanced Micro Devices, Inc. Way prediction logic for cache array

Also Published As

Publication number Publication date
EP1157336A1 (de) 2001-11-28
EP1157336B1 (de) 2009-07-29
US6643738B2 (en) 2003-11-04
KR20010102210A (ko) 2001-11-15
JP2003517682A (ja) 2003-05-27
WO2001044948A1 (en) 2001-06-21
KR100810781B1 (ko) 2008-03-06
US20020004876A1 (en) 2002-01-10
CN1206594C (zh) 2005-06-15
CN1347527A (zh) 2002-05-01

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