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DE60041124D1 - Ruktur mit kontrollierten eigenspannungen - Google Patents

Ruktur mit kontrollierten eigenspannungen

Info

Publication number
DE60041124D1
DE60041124D1 DE60041124T DE60041124T DE60041124D1 DE 60041124 D1 DE60041124 D1 DE 60041124D1 DE 60041124 T DE60041124 T DE 60041124T DE 60041124 T DE60041124 T DE 60041124T DE 60041124 D1 DE60041124 D1 DE 60041124D1
Authority
DE
Germany
Prior art keywords
ruktur
voltages
controlled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60041124T
Other languages
English (en)
Inventor
Hubert Moriceau
Olivier Rayssac
Anne-Marie Cartier
Bernard Aspar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA filed Critical Commissariat a lEnergie Atomique CEA
Application granted granted Critical
Publication of DE60041124D1 publication Critical patent/DE60041124D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00642—Manufacture or treatment of devices or systems in or on a substrate for improving the physical properties of a device
    • B81C1/0065—Mechanical properties
    • B81C1/00666—Treatments for controlling internal stress or strain in MEMS structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10P10/12—
    • H10P90/1916—
    • H10W10/181—
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0161—Controlling physical properties of the material
    • B81C2201/0163—Controlling internal stress of deposited layers
    • B81C2201/0167—Controlling internal stress of deposited layers by adding further layers of materials having complementary strains, i.e. compressive or tensile strain
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/12—All metal or with adjacent metals
    • Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
    • Y10T428/12528—Semiconductor component
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/31504—Composite [nonstructural laminate]
    • Y10T428/31678—Of metal

Landscapes

  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Micromachines (AREA)
  • Recrystallisation Techniques (AREA)
  • Diaphragms And Bellows (AREA)
  • Physical Vapour Deposition (AREA)
  • Chemical Vapour Deposition (AREA)
DE60041124T 1999-02-10 2000-02-09 Ruktur mit kontrollierten eigenspannungen Expired - Lifetime DE60041124D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9901558A FR2789518B1 (fr) 1999-02-10 1999-02-10 Structure multicouche a contraintes internes controlees et procede de realisation d'une telle structure
PCT/FR2000/000308 WO2000048238A1 (fr) 1999-02-10 2000-02-09 Structure multicouche a contraintes internes controlees et procede de realisation d'une telle structure

Publications (1)

Publication Number Publication Date
DE60041124D1 true DE60041124D1 (de) 2009-01-29

Family

ID=9541823

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60041124T Expired - Lifetime DE60041124D1 (de) 1999-02-10 2000-02-09 Ruktur mit kontrollierten eigenspannungen

Country Status (7)

Country Link
US (1) US6756285B1 (de)
EP (1) EP1155442B1 (de)
JP (1) JP4889154B2 (de)
KR (1) KR100743557B1 (de)
DE (1) DE60041124D1 (de)
FR (1) FR2789518B1 (de)
WO (1) WO2000048238A1 (de)

Families Citing this family (70)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2773261B1 (fr) 1997-12-30 2000-01-28 Commissariat Energie Atomique Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions
FR2823599B1 (fr) 2001-04-13 2004-12-17 Commissariat Energie Atomique Substrat demomtable a tenue mecanique controlee et procede de realisation
FR2823596B1 (fr) * 2001-04-13 2004-08-20 Commissariat Energie Atomique Substrat ou structure demontable et procede de realisation
US6956268B2 (en) 2001-05-18 2005-10-18 Reveo, Inc. MEMS and method of manufacturing MEMS
US7045878B2 (en) 2001-05-18 2006-05-16 Reveo, Inc. Selectively bonded thin film layer and substrate layer for processing of useful devices
FR2828762B1 (fr) * 2001-08-14 2003-12-05 Soitec Silicon On Insulator Procede d'obtention d'une couche mince d'un materiau semi-conducteur supportant au moins un composant et/ou circuit electronique
US7163826B2 (en) 2001-09-12 2007-01-16 Reveo, Inc Method of fabricating multi layer devices on buried oxide layer substrates
US6875671B2 (en) 2001-09-12 2005-04-05 Reveo, Inc. Method of fabricating vertical integrated circuits
FR2830983B1 (fr) 2001-10-11 2004-05-14 Commissariat Energie Atomique Procede de fabrication de couches minces contenant des microcomposants
US6806151B2 (en) * 2001-12-14 2004-10-19 Texas Instruments Incorporated Methods and apparatus for inducing stress in a semiconductor device
US20030227057A1 (en) 2002-06-07 2003-12-11 Lochtefeld Anthony J. Strained-semiconductor-on-insulator device structures
US6995430B2 (en) 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US7176108B2 (en) 2002-11-07 2007-02-13 Soitec Silicon On Insulator Method of detaching a thin film at moderate temperature after co-implantation
FR2848337B1 (fr) * 2002-12-09 2005-09-09 Commissariat Energie Atomique Procede de realisation d'une structure complexe par assemblage de structures contraintes
FR2848336B1 (fr) * 2002-12-09 2005-10-28 Commissariat Energie Atomique Procede de realisation d'une structure contrainte destinee a etre dissociee
FR2856844B1 (fr) 2003-06-24 2006-02-17 Commissariat Energie Atomique Circuit integre sur puce de hautes performances
US6982210B2 (en) 2003-07-10 2006-01-03 S.O.I.Tec Silicon On Insulator Technologies S.A. Method for manufacturing a multilayer semiconductor structure that includes an irregular layer
FR2857953B1 (fr) 2003-07-21 2006-01-13 Commissariat Energie Atomique Structure empilee, et procede pour la fabriquer
EP1667207B1 (de) * 2003-09-08 2019-07-17 SUMCO Corporation Gebondeter wafer und herstellungsverfahren dafür
US20050067377A1 (en) * 2003-09-25 2005-03-31 Ryan Lei Germanium-on-insulator fabrication utilizing wafer bonding
FR2860178B1 (fr) * 2003-09-30 2005-11-04 Commissariat Energie Atomique Procede de separation de plaques collees entre elles pour constituer une structure empilee.
FR2861497B1 (fr) 2003-10-28 2006-02-10 Soitec Silicon On Insulator Procede de transfert catastrophique d'une couche fine apres co-implantation
FR2863405B1 (fr) * 2003-12-08 2006-02-03 Commissariat Energie Atomique Collage moleculaire de composants microelectroniques sur un film polymere
US7772087B2 (en) 2003-12-19 2010-08-10 Commissariat A L'energie Atomique Method of catastrophic transfer of a thin film after co-implantation
FR2864970B1 (fr) * 2004-01-09 2006-03-03 Soitec Silicon On Insulator Substrat a support a coefficient de dilatation thermique determine
JP4020097B2 (ja) * 2004-05-11 2007-12-12 セイコーエプソン株式会社 半導体チップ、半導体装置及びその製造方法、並びに電子機器
KR100669778B1 (ko) * 2004-11-20 2007-01-16 삼성에스디아이 주식회사 기판 및 박막 트랜지스터를 구비한 기판
JP4624131B2 (ja) * 2005-02-22 2011-02-02 三洋電機株式会社 窒化物系半導体素子の製造方法
US7271069B2 (en) * 2005-04-21 2007-09-18 Freescale Semiconductor, Inc. Semiconductor device having a plurality of different layers and method therefor
US7205202B2 (en) * 2005-04-21 2007-04-17 Freescale Semiconductor, Inc. Semiconductor device and method for regional stress control
FR2886051B1 (fr) 2005-05-20 2007-08-10 Commissariat Energie Atomique Procede de detachement d'un film mince
US20060270192A1 (en) * 2005-05-24 2006-11-30 International Business Machines Corporation Semiconductor substrate and device with deuterated buried layer
US7319591B2 (en) * 2005-05-26 2008-01-15 International Business Machines Corporation Optimized thermally conductive plate and attachment method for enhanced thermal performance and reliability of flip chip organic packages
US7262112B2 (en) * 2005-06-27 2007-08-28 The Regents Of The University Of California Method for producing dislocation-free strained crystalline films
FR2889887B1 (fr) 2005-08-16 2007-11-09 Commissariat Energie Atomique Procede de report d'une couche mince sur un support
FR2891281B1 (fr) 2005-09-28 2007-12-28 Commissariat Energie Atomique Procede de fabrication d'un element en couches minces.
US7544964B2 (en) * 2005-12-01 2009-06-09 National Institute Of Information And Communications Technology, Incorporated Administrative Agency Method for fabricating thin layer device
US7992128B2 (en) * 2006-01-27 2011-08-02 Sap Ag Computer software adaptation method and system
FR2899378B1 (fr) 2006-03-29 2008-06-27 Commissariat Energie Atomique Procede de detachement d'un film mince par fusion de precipites
JP5532527B2 (ja) * 2006-08-03 2014-06-25 株式会社デンソー Ｓｏｉ基板およびその製造方法
JP4958147B2 (ja) * 2006-10-18 2012-06-20 Ｈｏｙａ株式会社 露光用反射型マスクブランク及び露光用反射型マスク、多層反射膜付き基板、並びに半導体装置の製造方法
FR2910179B1 (fr) 2006-12-19 2009-03-13 Commissariat Energie Atomique PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART
FR2913968B1 (fr) * 2007-03-23 2009-06-12 Soitec Silicon On Insulator Procede de realisation de membranes autoportees.
FR2924273B1 (fr) 2007-11-28 2010-02-19 Commissariat Energie Atomique Procede de moderation de deformation
FR2925221B1 (fr) * 2007-12-17 2010-02-19 Commissariat Energie Atomique Procede de transfert d'une couche mince
FR2926674B1 (fr) * 2008-01-21 2010-03-26 Soitec Silicon On Insulator Procede de fabrication d'une structure composite avec couche d'oxyde de collage stable
JP2009277944A (ja) * 2008-05-15 2009-11-26 Toyoda Gosei Co Ltd 接合体の製造方法及び発光装置の製造方法
US8309432B2 (en) * 2008-05-30 2012-11-13 Alta Devices, Inc. Epitaxial lift off stack having a universally shrunk handle and methods thereof
CN101634880A (zh) * 2008-07-23 2010-01-27 鸿富锦精密工业（深圳）有限公司 电磁干扰挡片制造方法
JP5430109B2 (ja) * 2008-09-30 2014-02-26 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
US8063370B2 (en) * 2009-01-16 2011-11-22 Hanvision Co., Ltd. Semiconductor device and method of manufacturing the same
DE102009000514A1 (de) * 2009-01-30 2010-08-26 Robert Bosch Gmbh Verbundbauteil sowie Verfahren zum Herstellen eines Verbundbauteil
US7927975B2 (en) 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
FR2947098A1 (fr) 2009-06-18 2010-12-24 Commissariat Energie Atomique Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince
WO2012043616A1 (ja) * 2010-09-28 2012-04-05 株式会社村田製作所 圧電デバイス、圧電デバイスの製造方法
EP2622630A1 (de) * 2010-09-30 2013-08-07 Freescale Semiconductor, Inc. Verfahren zur verarbeitung eines halbleiterwafers, halbleiterwafer und halbleiterbauelement
FR2985370A1 (fr) * 2011-12-29 2013-07-05 Commissariat Energie Atomique Procede de fabrication d'une structure multicouche sur un support
WO2013161906A1 (ja) * 2012-04-27 2013-10-31 並木精密宝石株式会社 複合基板の製造方法、半導体素子の製造方法、複合基板および半導体素子
US9481566B2 (en) 2012-07-31 2016-11-01 Soitec Methods of forming semiconductor structures including MEMS devices and integrated circuits on opposing sides of substrates, and related structures and devices
CN104003346B (zh) * 2013-02-25 2019-05-17 中芯国际集成电路制造(上海)有限公司 一种薄膜结构、压力传感器及电子装置
WO2014200460A1 (en) * 2013-06-10 2014-12-18 Empire Technology Development Llc Graded structure films
CN105712286B (zh) * 2014-12-02 2018-03-30 中芯国际集成电路制造(上海)有限公司 Mems器件的制作方法
KR101627815B1 (ko) * 2015-04-21 2016-06-08 인천대학교 산학협력단 비결정질 이그조(igzo) tft 기반 트랜젼트 반도체의 제조 방법
FR3037443B1 (fr) 2015-06-12 2018-07-13 Soitec Heterostructure et methode de fabrication
CN106548972B (zh) * 2015-09-18 2019-02-26 胡兵 一种将半导体衬底主体与其上功能层进行分离的方法
JP6563360B2 (ja) * 2016-04-05 2019-08-21 信越化学工業株式会社 酸化物単結晶薄膜を備えた複合ウェーハの製造方法
JP7120225B2 (ja) * 2017-05-31 2022-08-17 日本ゼオン株式会社 タッチセンサ基材及びその製造方法、タッチセンサ部材及びその製造方法、並びに、表示装置
US11721554B2 (en) * 2019-03-18 2023-08-08 Intel Corporation Stress compensation for wafer to wafer bonding
EP4189734B1 (de) * 2020-07-28 2024-06-26 Soitec Verfahren zum übertragen einer dünnen schicht auf ein trägersubstrat mit ladungseinfangschicht
FR3129622B1 (fr) * 2021-11-26 2023-10-27 Nelumbo Digital Système pour déformer une structure utile

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0355822A (ja) * 1989-07-25 1991-03-11 Shin Etsu Handotai Co Ltd 半導体素子形成用基板の製造方法
US5362667A (en) * 1992-07-28 1994-11-08 Harris Corporation Bonded wafer processing
US5102821A (en) * 1990-12-20 1992-04-07 Texas Instruments Incorporated SOI/semiconductor heterostructure fabrication by wafer bonding of polysilicon to titanium
US5261999A (en) * 1991-05-08 1993-11-16 North American Philips Corporation Process for making strain-compensated bonded silicon-on-insulator material free of dislocations
JPH07187892A (ja) * 1991-06-28 1995-07-25 Internatl Business Mach Corp <Ibm> シリコン及びその形成方法
JPH06196377A (ja) * 1991-11-19 1994-07-15 Sumitomo Metal Mining Co Ltd 半導体基板の接合方法
JP3048754B2 (ja) * 1992-06-25 2000-06-05 日本電気株式会社 半導体基板
US5310451A (en) * 1993-08-19 1994-05-10 International Business Machines Corporation Method of forming an ultra-uniform silicon-on-insulator layer
US5753134A (en) * 1994-01-04 1998-05-19 Siemens Aktiengesellschaft Method for producing a layer with reduced mechanical stresses
JP3257580B2 (ja) * 1994-03-10 2002-02-18 キヤノン株式会社 半導体基板の作製方法
JP2669368B2 (ja) * 1994-03-16 1997-10-27 日本電気株式会社 Ｓｉ基板上化合物半導体積層構造の製造方法
CN1132223C (zh) * 1995-10-06 2003-12-24 佳能株式会社 半导体衬底及其制造方法
CA2233115C (en) * 1997-03-27 2002-03-12 Canon Kabushiki Kaisha Semiconductor substrate and method of manufacturing the same
US6255731B1 (en) * 1997-07-30 2001-07-03 Canon Kabushiki Kaisha SOI bonding structure
US5909627A (en) * 1998-05-18 1999-06-01 Philips Electronics North America Corporation Process for production of thin layers of semiconductor material

Also Published As

Publication number Publication date
EP1155442A1 (de) 2001-11-21
FR2789518B1 (fr) 2003-06-20
KR20010113684A (ko) 2001-12-28
KR100743557B1 (ko) 2007-07-27
FR2789518A1 (fr) 2000-08-11
JP2002536843A (ja) 2002-10-29
WO2000048238A1 (fr) 2000-08-17
US6756285B1 (en) 2004-06-29
EP1155442B1 (de) 2008-12-17
JP4889154B2 (ja) 2012-03-07

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