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DE60027149D1 - Aritmetik Einheit - Google Patents

Aritmetik Einheit

Info

Publication number
DE60027149D1
DE60027149D1 DE60027149T DE60027149T DE60027149D1 DE 60027149 D1 DE60027149 D1 DE 60027149D1 DE 60027149 T DE60027149 T DE 60027149T DE 60027149 T DE60027149 T DE 60027149T DE 60027149 D1 DE60027149 D1 DE 60027149D1
Authority
DE
Germany
Prior art keywords
arithmetic unit
arithmetic
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60027149T
Other languages
English (en)
Inventor
Sebastien Ferroussat
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Application granted granted Critical
Publication of DE60027149D1 publication Critical patent/DE60027149D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52Multiplying; Dividing
    • G06F7/523Multiplying only
    • G06F7/533Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5334Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
    • G06F7/5336Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
    • G06F7/5338Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm each bitgroup having two new bits, e.g. 2nd order MBA
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443Sum of products

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
DE60027149T 2000-08-01 2000-08-01 Aritmetik Einheit Expired - Lifetime DE60027149D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP00410090A EP1178398B1 (de) 2000-08-01 2000-08-01 Aritmetik Einheit

Publications (1)

Publication Number Publication Date
DE60027149D1 true DE60027149D1 (de) 2006-05-18

Family

ID=8174042

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60027149T Expired - Lifetime DE60027149D1 (de) 2000-08-01 2000-08-01 Aritmetik Einheit

Country Status (3)

Country Link
US (1) US7096246B2 (de)
EP (1) EP1178398B1 (de)
DE (1) DE60027149D1 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3663186B2 (ja) * 2002-06-10 2005-06-22 日本テキサス・インスツルメンツ株式会社 部分積生成回路および乗算器
US7308470B2 (en) * 2003-12-05 2007-12-11 Intel Corporation Smaller and lower power static mux circuitry in generating multiplier partial product signals
US7433912B1 (en) * 2004-02-19 2008-10-07 Sun Microsystems, Inc. Multiplier structure supporting different precision multiplication operations
CN113767362B (zh) * 2020-04-01 2024-05-17 华为技术有限公司 一种多模融合乘法器

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4575812A (en) * 1984-05-31 1986-03-11 Motorola, Inc. X×Y Bit array multiplier/accumulator circuit
JPS62229439A (ja) * 1986-03-31 1987-10-08 Toshiba Corp 並列乗算器
EP0813143A3 (de) * 1989-11-13 1998-01-28 Harris Corporation Zeichenausbreitung in einem mehrere Bit umkodierenden Multiplizierer
JP3033212B2 (ja) * 1991-01-31 2000-04-17 日本電気株式会社 乗算器
JPH07234778A (ja) * 1994-02-22 1995-09-05 Texas Instr Japan Ltd 演算回路
US6463453B1 (en) * 1998-01-12 2002-10-08 Motorola, Inc. Low power pipelined multiply/accumulator with modified booth's recoder
US6157939A (en) * 1998-06-04 2000-12-05 Integrated Device Technology, Inc. Methods and apparatus for generating multiplicative inverse product

Also Published As

Publication number Publication date
EP1178398B1 (de) 2006-04-05
US20020042805A1 (en) 2002-04-11
US7096246B2 (en) 2006-08-22
EP1178398A1 (de) 2002-02-06

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Legal Events

Date Code Title Description
8332 No legal effect for de