DE3830044C1 - Method and device for digitising an analog signal with an amplitude-dependent resolution - Google Patents

Abstract

A device for the amplitude-dependent resolution during digitisation of an analog signal has N analog/digital converters (10) and a combining circuit (17). N reference voltages form the upper limit for the input-voltage ranges. For the respective voltage value of the ith reference voltage it holds true that the voltage difference to the preceding (i-1)th reference voltage is greater by a factor Mi than the voltage difference to the next (i+1)th reference voltage following. An analog input signal (9) is allocated to the input-voltage range in which there is no further reference voltage between its upper limit and the voltage value of the analog input signal (9). The digital output signal (18) digitised in the analog/digital converters (10) and selected in the combining circuit (17) exhibits a very high resolution at small analog input signals (9), which decreases slowly towards large analog input signals (9). Using six 8-bit analog/digital converters, a quasi-13-bit analog/digital converter is constructed which has good resolution even at medium amplitudes. <IMAGE>

Description

The invention relates to a method according to the Ober Concept of claim 1 and one for performing the Appropriate facility.

It is known that analog signals of great dynamics, that is those with large and small values in time Sequence that can only be digitized imprecisely. A Common 8-bit analog-to-digital converter with 256 digits Levels can be increased in relation to the maximum processing voltage signal a dynamic range of 48 dB to capture.

Furthermore, a simple interconnection of several Analog-digital converter known, each the same large, non-overlapping but adjacent part sections of voltage values of the analog input capture voltage. A reference voltage is too  Auxiliary reference voltages divided that the respective auxiliary reference voltage values the limits of Corresponding voltage sections. The analog Input signal is with the auxiliary reference voltages compared and as a result of this comparison a chip section and thus an analog-digital Transducers associated with it in a digital output signal changes.

The digital signals from the various analog-digital converters are then combined to obtain the output signal. In order for such an arrangement to cover a dynamic range of 78 dB, i.e. to detect a maximum voltage of 2 ¹³ times the smallest quantization of the analog input signal, 32 8-bit analog-digital converters are necessary. This is a technically very complex structure.

From DE-OS 36 11 822 a method is known in which the analog signal is divided into two or preferably three areas. The range of high amplitudes is digitized directly. The range of the small amplitudes is digitized after an amplification by an amplification factor N and then the digital signal obtained is divided down by an amplification factor 1 / N. The composite digital signal results in a higher resolution for smaller analog voltage values.

In an intermediate area, however, to the top through the maximum convertible analog voltage amplitude of the small-range analog-digital converter be the digital signal is limited by an additive sliding combination of the small-value digital signal and the large digital signal, preferably by a linear transition of the Ge weighting from zero to one of the proportion of the tall term digital signal with an increase in the analog Input signal. This method has the disadvantage that when using e.g. two 8-bit analog Digital converters have a dynamic range of 78 dB only through one Factor N of 32 is reached. This means that over 95% of the measuring range the rough resolution of a single 8- Oro Range Analog Bit Analog Digital Converter Digital converter.

DE-OS 27 06 928 teaches a method for analog Digital conversion of signals where the analog Input signal different in several channels is reinforced. The amplified analog signals are used by several similar analog-digital Converters converted, using a priority encoder determines the most significant bit and that together digital output signal set on a data output switches. The known method works with a low clock rate and thus has a low  Processing speed for incoming analog signals on. A device according to the method comprises thus a variety of with the analog-digital Converters to be networked digital multiplexers.

Based on this state of the art Invention based on the object, a method and a To create a facility of the type mentioned at the beginning, which allow a high level in a simple manner solution of the digitized analog input signal for the smallest as well as for the medium signal amplitudes receive.

This object is achieved according to the invention for a ver drive through the characteristic features of the An spell 1 solved. A device for performing the method is characterized in claim 6.

The invention relates to the prior art an order better by several binary orders of magnitude solution at medium voltage amplitudes if of an equal resolution compared to the status of Technology both for voltages close to the maximum change voltage as well as for the smallest voltage amplitudes are assumed.  

The reduction in the number of 32 8-bit analog-digital Converters with simple interconnection of the analog Digital converter compared to only 6 8-bit analog-digital Converters allowed to achieve 78dB dynamic range a considerable simplification of the structure.

In the following, exemplary embodiments of an on direction for performing an inventive Process explained with reference to the drawings. It demonstrate:

Signals Fig. 1 waveforms of two analog input and their corresponding digital output signals of a conventional 4-bit analog-to-digital converter,

Signals Fig. 2 waveforms of two analog input and their corresponding digital output signals of a conventional interconnection of four 4-bit analog-to-digital converters,

Fig. 3 waveforms of two logarithmically amplified analog input signals and their corresponding digital output signals of a 4-bit analog-to-digital converter,

Fig. 4 is a block diagram of a device according to the invention for digitizing an analog signal having an amplitude dependent on solution according to a first Ausführungsbei game,

Signals Fig. 5 waveforms of two analog input and their corresponding digital output signals of an inventive device for digitizing an analog signal having an amplitude dependent on solution comprising 4-bit analog-to-digital converters,

Fig. 6 is a block diagram of an inventive device for digitizing an analog signal having an amplitude dependent on solution according to a second Ausführungsbei game,

Fig. 7 shows the distribution of the voltage ranges of the rich be dependent analog-to-digital converter when digitizing AC signals in accordance with a development of the invention for digitizing signals of AC voltage,

Fig. 8 shows the allocation of the digitizing stages in a non-overlapping joining of the analog-to-digital converter according to a further embodiment of the invention, and

Fig. 9, the selection of the converting analog-to-digital converter with overlapping digitization areas of the analog-to-digital converter.

Fig. 1 shows waveforms of two analog input signals 1 , 2 , which are supplied to a conventional analog-to-digital converter, and accordingly digital output signals 3 , 4 of a 4-bit analog-to-digital converter. The amplitude of the signals in digitization stages 5 is plotted against the time, which is represented by a sequence of sampling points 6 .

The number of sampling points 6 per second gives the sampling frequency in Hertz. A 4- bit analog-digital converter has sixteen digitization stages 5 , which correspond to a dynamic range of 24 dB. The analog input signals 1 , 2 are detected in the sampling points 6 with their respective instantaneous value 7 , which is indicated by the distances parallel to the time axis.

The first analog input signal 1 of the 4-bit analog-digital converter has a large increase in amplitude over time, so that the convertible amplitude range of the analog-digital converter is fully utilized. Accordingly, the first digital output signal 3 of the 4-bit analog-digital converter closely approximates the first analog input signal 1 .

The second analog input signal 2 of the 4-bit analog-digital converter, on the other hand, has a smaller amplitude slope during the drawn sampling interval, so that the convertible amplitude range of the analog-digital converter is almost not used. The second digital output signal 4 of the 4-bit analog-to-digital converter, which in the case shown shows only two values, accordingly approximates the second analog input signal 2 very poorly.

Fig. 2 shows waveforms of two analog input signals 1 , 2 and corresponding digital output signals 3 , 4 of a prior art interconnection of four 4-bit analog-digital converters, the mode of operation of a 6-bit analog-digital -Converters with its 64 digitization levels correspond to 5 .

The four 4-bit analog-digital converters process the signal in four non-overlapping, but adjacent digitization areas 8 , each with 16 digitization stages 5 . This enables a dynamic range of 36 dB to be achieved. The smaller second analog input signal 2 is well represented here by several digital values of the second digital output signal 4 .

When using 8-bit analog-digital converters are used to realize a dynamic range of 78 dB  with this structure the large number of 32 8-bit Analog-digital converters required.

FIG. 3 shows signal waveforms of two logarithmically amplified analog input signals 1, 2 and corresponding them digital output signals 3, 4 of a 4-bit analog-to-digital converter.

The logarithmically amplified analog input signal 1 is fed to a single, here 4-bit, analog-digital converter, which converts it into a logarithmic digital output signal 3 . The smaller logarithmic second analog input signal 2 is represented here by several digital values of the second digital output signal 4 . The difficulty of this dynamic compression lies in the technical implementation of the logarithmic amplifier with a well-kept characteristic over the entire frequency range.

Fig. 4 shows the block diagram of an inventive device for digitizing an analog signal with an amplitude-dependent on solution according to a first embodiment. In FIG. 4 as well as in FIG. 6, the simply drawn connections mean transmission paths for analog signals or control signals, while the connections drawn with one line pair each represent transmission paths for digital signals or control signals, for example for several bits in parallel.

An analog input signal 9 is simultaneously fed into the inputs of N analog-digital converters 10 .

Further reference voltages 13 , 14 are derived from an input reference voltage 11 in a reference divider circuit 12 N -1. The input reference voltage 11 serves as the first reference voltage, so that N reference voltages are present together with the derived N -1 further reference voltages. For the voltage value of the i th of the successive reference voltages, the voltage difference to the previous, ( i -1) th reference voltage is greater by a factor Mi than the voltage difference to the next, ie ( i +1) th reference voltage. I denotes a natural number between 2 and N -1. In the simplest case, an input reference voltage 11 is fed into the reference divider circuit 12 , which consists of a high-precision resistance chain for generating the reference voltages.

The factors Mi can be kept constant and, in the preferred embodiment of the invention described below, have the constant value Mi = 2 for all i .

The reference voltages each determine the upper limit of an input voltage range which is predetermined for the respective analog-digital converter 10 .

The analog input signal 9 is digitized in the N analog-digital converters 10 . This results in a valid value at a digital data output 16 of the i- th analog-digital converter 10 if the analog input signal 9 is less than or at most equal to the i- th reference voltage 11 , 13 or 14 . If the analog input signal 9 is greater than the i- th reference voltage 11 , 13 or 14 , an overflow signal 15 is generated in the i- th analog-digital converter 10 .

Each analog-digital converter 10 is connected to a combination and selection circuit 17 via a digital data line 40 and via a control line 41 . Via the control lines 41 , the possible overflow signals 15 are applied to the combination and selection circuit 17 .

The combination and selection circuit 17 uses the overflow signals 15 to determine which of the N analog-digital converters 10 is selected for the combination of the digital output signal 18 .

Furthermore, a sequence control circuit 19 can be seen easily, which provides various clock signals 20 , 21 , which guarantee an error-free creation and readout of the digital output signal 18 .

FIG. 5 shows waveforms of two analog input signals 1, 2 and corresponding them digital output signals 3, 4, a conversion according to the invention of an analog signal of three 4-bit analog-to-digital converters in their effect a quasi-6-bit analog- Correspond to digital converters with a dynamic range of 36 dB. The analog-digital converter operating in this way is described with quasi-6-bit, since the quantization of the analog input signal 1 with the aid of a device according to the invention no longer corresponds to the quantization by a 6-bit analog-digital converter with large voltage amplitudes.

The three 4-bit analog-digital converters process the signal in three overlapping digitization areas 8 , each with 16 digitization levels 5 . The factor Mi is constant and is two. The lower limit of the input voltage range is zero. This realizes a dynamic range of 36 dB. The smaller second analog input signal 2 is well represented here by several digital values of the second digital output signal 4 .

When using 8-bit analog-digital converters are used to realize a dynamic range of 78 dB only six analog-to-digital converters needed their  Mode of operation corresponds to a quasi-13-bit analog Digital converter.

Fig. 6 shows the block diagram of another means for digitizing an analog signal with an amplitude dependent resolution. The analog input signal 9 is present at the inputs of N amplifiers 22 at the same time.

The amplifier 22 amplify the analog input signal 9 and generate an amplified analog input signal 23 . The amplified analog input signals 23 act on N analog-digital converters 10 . The reference voltage 11 is applied to the reference voltage input of the analog-digital converter 10 . The digitization and selection of the corresponding digital output signal 18 is done according to the description of FIG. 4th

FIG. 7 shows the division of the voltage ranges 8 of the range-dependent analog-digital converters when digitizing AC signals according to a development of the invention. The factor Mi is chosen to be approximately equal to 3.3 and the lower limit of the input voltage range is equal in magnitude to the voltage value of its upper limit with opposite polarity. The three digitization areas 8 of the analog-digital converter shown are arranged symmetrically around the zero voltage 29 . Seven 8-bit analog-digital converters are required for a resolution of 78 dB for each polarity of the analog signal 9 .

Fig. 8 shows the distribution of digitizing step 5 of the analog-digital converter with a dung überlappfreien contiguity digitization regions 8, according to a further embodiment of the OF INVENTION. The factor Mi is constantly equal to 2, and the lower limit of an input voltage range is equal to the upper limit of the next next lower input voltage range. For a resolution of 78 dB, an 8-bit analog-digital converter for the lowest digitization range 8 and five 7-bit analog-digital converters for the other digitization ranges S are necessary. Compared to the first embodiment of the invention, the bit value of several analog-digital converters can be reduced by one bit for the same resolution with the same number of analog-digital converters used.

Fig. 9 shows the selection of the converting analog-to-digital converter with overlapping digitization areas 8 of the analog-to-digital converter. There are the digitization stages 5 of three 4-bit analog-Digi tal converters, the digitization areas with 51 , 52 and 53 are designated.

A large analog input signal 54 is present at the three first, second and third analog-digital converters identified by their digitization areas 51, 52 and 53 . Both the second and the third analog-digital converter generate an overflow signal 15 , so that the digitized signal of the first analog-digital converter is selected.

A middle analog input signal 55 is present at the three analog-digital converters. Only the third analog-digital converter generates an overflow signal 15 , so that the digitized signal of the second analog-digital converter is selected.

A small analog input signal 56 is present on the three analog-digital converters. None of the analog-digital converters generates an overflow signal 15 , so that the digitized signal of the third analog-digital converter is selected.

Claims (6)

1. A process for digitizing an analog signal great momentum with an amplitude dependent on solution with a plurality of analog-to-digital converters, characterized in that N reference voltages are provided, wherein for the voltage value of i - applies th reference voltage that the voltage difference to the previous, ( i -1) th reference voltage is a factor Mi greater than the voltage difference from the next, ( i +1) th reference voltage, where i represents a natural number between 2 and N -1, that N input voltage ranges are produced, the voltage value of which the upper limit is determined in each case by one of the N reference voltages that an analog input signal is assigned to the input voltage range in which there is no further reference voltage in absolute values between its upper limit and the voltage value of the analog input signal, that the analog input signal is in the range assigned to it Input voltage range too a Digi talsignal is converted and that only the thus obtained digital signal of this input voltage range contributes to the digital output signal. 2. The method according to claim 1, characterized in that the factors Mi are a constant and that their value is greater than one. 3. The method according to claim 1 or 2, characterized records that the voltage value at the lower limit of all input voltage ranges is zero. 4. The method of claim 1 or 2, characterized in that the voltage value at the lower limit of each, th except the N, Eingangsspannungsbe Reich equal to the voltage value at the upper limit of the next input voltage range and that the voltage value at the lower limit of N - input voltage range is zero. 5. The method according to claim 1 or 2, characterized records that the voltage value at the lower limit of each input voltage range the voltage value at the upper limit of the same on voltage range with reverse polarity corresponds. 6. Device for performing the method according to one or more of claims 1 to 5, characterized in that N analog-digital converters ( 10 ) are seen before, which form N input voltage ranges and which are struck with an analog input signal ( 9 ) that the analog input signal ( 9 ) is converted into a valid digital signal ( 16 ) by the analog-to-digital converter ( 10 ), in which it is in their input voltage range that the other analog-to-digital converter ( 10 ) is a control generate signal ( 15 ) and that the valid digital signal ( 16 ) is selected in a combination circuit ( 17 ) as a digital output signal ( 18 ), the associated input voltage range of which has the smallest maximum voltage value and no control signal ( 15 ).