DE3506960A1 - TIME BASE CORRECTION - Google Patents

Description

Time base correction circuit

description
5

The present invention relates to a time base correction circuit, the clock-responsive delay elements, such as charge-coupled elements which are operated with clock pulses.

Time base correction circuits for correcting the same time base error that occurs in two input signals of two different ones Frequency bands are present, contain circuits that respond to clocks delay elements, such as using charge coupled devices as time base correction elements.

Fig. 1 shows a signal processing circuit of a picture record player, the one with such a time base correction circuit that uses charge coupled devices (CCD), is equipped. The time correction circuit contains two CCDs 2 and 3, a voltage controlled oscillator (VCO) 4 for Generating a common clock pulse signal (hereinafter referred to simply as "clock") for operating the CCDs, and a Time base error detector 5 for determining the time base error contained in the video signal and for supplying the determined Output signal to VCO 4.

The RF input signal reproduced from the optical disc consists of • a video signal and an audio FM signal. The video signal is demodulated by a video demodulator 6 before it is supplied to the CCD 2, while the Audio FM signal is fed directly to the CCD 3. If the RF input signal has a time base error, then the demodulated video signal and the audio FM signal that are fed to the CCDs have the same time base

error on.

The time base error detector 5 detects that in the video output signal contained time base errors and feeds a corresponding output signal to the VCO 4. The VCO 4 generates a clock whose frequency depends on the generated output voltage of the time base error detector 5, and feeds the clocks to CCDs 2 and 3. The CCDs operated by the clock have the same time delay as the demodulated Video signal and the audio FM signal in directions that have the time base error, which both have in common is canceled so that a time base correction is made. The output of the CCD 2 and that of the CCD 3, the is demodulated by an audio demodulator 7 are output as a video or audio signal.

It is assumed that the number of CCD stages, that is, the number of stages in the transmission section of the CCDs is N and that the frequency of the drive clock is f (MHz). The CCD delay time T _d (microseconds) is determined by the following equation:

T _d = N / f _c (1).

From the above equation it can be seen that one can get the delay time by changing the clock frequency f can change.

It is assumed that the time base error that occurs in the RF input signal is present, has a maximum deviation of ΔΤ. The possible range of variation Ar, the delay time of the CCDs 2 and 3 must then be ΔΤ or more

ΓΠ9.Χ

so that the demodulated video signal and the audio FM signal are successfully time base corrected can.

The range of variation ΔΤ, the delay time when changing the frequency of the N-stage CCDs from f. To f ~, is general

mine by the following equation (based on the preceding Equation (1)) given with:

T _d1 = NZf ₁ , and
5

T _d2 = NZf ₂ ,

where T, .. is the delay time of the CCD corresponding to the frequency f. and f _{2 is} the clock frequency. If f'.j <f " ₂ , then ^ T, can be expressed by:

= ^T d1 ~ ^T d2 ^{= N / f} 1 ' ^{N / f} 2 ^{= N} ( ^{1 /} ( ^f i - ^Γ 2 ^)}

In the time base correction circuit according to FIG. 1, this is the same Timing errors in the demodulated video signal and in the reproduced audio FM signal supplied to the CCDs 2 and 3, respectively are included, so that the time base correction with the same delay time variation width in the CCDs 2 and 3 can be performed. In the time base correction circuit 1 of Fig. 1, a clock of the same frequency the CCDs 2 and 3 supplied as a common clock from the VCO 4. Therefore, as can be seen from the equation (2), the number of stages must of the CCD 2 must be the same as that of the CCD 3, so that the two CCDs have the same delay time variation width exhibit.

A further explanation will now be given with reference to an optical scanning video disc player which uses the PAL system.

The demodulated video signal fed to the CCD 2 has a frequency range of 0 to 5 MHz, while the Audio FM signal supplied to the CCD 3 uses FM carriers with frequencies between approximately 0.7 and 1.1 MHz. The CCD 3 is therefore supplied with a signal having a frequency band wider than that at the CCD 2, and the highest signal frequency that appears on the CCD 2 is 5 MHz,

- 3508960

while it is only 1.1 MHz for the CCD 3.

Since a CCD is basically a scanning element, according to the well-known scanning theory, the clock frequency f must be more than twice as high as the highest frequency of the input signal. In general, in consideration of the characteristics of the CCDs, the scanning frequency is set three times as high or higher. The clock frequency of the CCD 2 therefore only needs to be sufficient:
10

f _c > 5 x 3, i.e., f _c ^ 15 MHz (3),

and that of the CCD 3 must suffice:
f _c > 1.1 x 3, ie, f _c > 3.3 MHz (4).

In other words, if the maximum deviation ΔΤ des

Max

If the time base error contained in the reproduced RF input signal is subjected to the time base correction, then the lowest frequency f _{mi of} the clock only has to satisfy equations (3) and (4). If a common clock is used for the CCDs 2 and 3, as is the case in the case of the time base correction circuit 1 according to FIG. 1, then the lowest frequency f _in of the voltage controlled

th oscillator 4 generated clock satisfy equation (3).

A possible minimum value N. the number of CCD stages, which is necessary to carry out the time base correction even with the maximum deviation ΔΤ of the RF input signal, is now considered. The highest frequency f of the clock should not be set higher without limitation, but is limited depending on the operation of the CCD element. Around 20 MHz is generally considered to be upper Limit at the current state of technology.

Based on equation (2) is the possible delay time variation range T, given for the CCD by:

1 / f _max ) (5).

From the foregoing, it appears that the possible delay time variation ATj_ _ax must be greater for the CCD, when the maximum deviation ΔΤ, the time base error contained in the reproduced RF input signal. Assuming that the time base correction circuit 1 is designed so that it satisfies ΔΤ ■, _v = AT _mQV , then

Q Iu α. Χ ΠΙ 3rd X

the minimum number N is expressed. the CCD stages on the The basis of equation (5) is based on:

- 1 / f _max ) (6).

In equation (6), Δΐ \ _v is set so that the switching

Max

performance requirements are met, and f. is through the Equations (3) and (4) determined, while f__ “by the Operating behavior of the CCD element is determined.

Assuming that the maximum deviation ΔΤ of the HF

iUclX input signal 10 Us and the maximum frequency f _ _{v of} the clock

t Iu 3rd X

tes is 20 MHz, equation (6) becomes:

¹⁰ = ^N min-1 < ^{1 / f} min ~

If the CCDs 2 and 3 are not fed with a common clock, but clocks of different frequencies are applied to them and if N. . and N. ₂ indicate minimum numbers of levels of CCDs 2 and 3, and if f. = 15 MHz (from equation (3)), then:

10 = N. . (1/15 - 1/20).

ill JL11 ^mm 1

It therefore becomes N _1111n1 = 600 (7).

For f _min = 3.3 MHZ from equation (4) it follows for CCD 3

¹⁰ = ^N min-2 ^(1/3> 3 - 1/20).

It therefore becomes N _min _ ₂ = 40 (8).

If in the time base correction circuit according to FIG and 3 are fed, then the CCDs 2 and 3 should have more than 600 and 40 steps, respectively.

In the time base correction circuit of Fig. 1, however, the number of stages of the CCD 2, as described above, must be the same like that of the CCD 3, since a common clock is used for the two CCDs. Both CCDs must therefore have more than 600 levels. This means that there are more steps in the CCD than is actually necessary.

* ° The greater the number of steps in a CCD, the greater becomes the chip area when the CCD is manufactured in integrated circuit form. This leads to higher Costs and increases power consumption.

The invention is therefore based on the object of a time base correction circuit using CCDs as time base correction elements in which the number of CCD stages is reduced.

² ^ This object is achieved by the invention specified in claim 1. An embodiment of the invention is the subject of the dependent claim.

In the time base correction circuit according to the present invention, the number of CCD stages is reduced by generating of a signal of a frequency band, the highest frequency of which is greater, arranging two parallel CCDs with the same number of CCD stages to operate equivalently at a frequency twice as high, and Using CCDs identical in number of CCD stages to these CCDs for the other signal.

The invention is to be explained in more detail below with reference to the drawings. It shows:

Fig. 1 is a block diagram of a conventional time base correction circuit;

Figure 2 is a block diagram of a time base correction circuit in accordance with the present invention;

3 is a timing waveform diagram, and FIG

Figs. 4, 5 and 6 are waveform diagrams for explanation

the mode of operation of the embodiment according to FIG. 2.

Fig. 2 shows a time base correction circuit 8 with the features of the present invention. The circle is how that of Fig. 1, intended for an optical scanning video disc player. The difference between the two Circles is that the CCD 2 of Fig. 1 is replaced by two CCDs 9 and 10, the outputs of which to a changeover switch 11 are connected. The switching position of the switch 11 is from the clock output of the voltage-controlled Oscillator (VCO) 4 controlled. The clock is inverted and fed to the CCD 10 via an inverter 12. The number of the levels in the CCDs 9 and 10 is the same. The other circuit elements are the same as those in Fig. and the same reference numerals are therefore used for them.

The switching position of the switch 11 is determined by the clock supplied by the VCO 4, and for a sinusoidal clock f _CLK »which, as FIG. 3 shows, is supplied by the VCO 4, the switch 11 is switched to the upper position when the positive Half-wave is present, whereby the contacts a and c are connected to each other, and it is in the negative half-wave in the lower switching position

ment switched, in which the contacts b and c with each other are connected.

A sample output signal will now be described, which is shown in FIG

on the output side of the switch 11 by means of the CCDs 9 and 10 and the changeover switch 11. FIGS. 4A and 4B show the type of sampling of the demodulated video signal in the CCD 9, FIG. 4A relating to a demodulated video signal S _TN and a sampling output signal S, and FIG. 4B relating to the clock f _CLK supplied from the VCO 4 to the CCD 9. The demodulated video signal S _1n fed to the CCD 9 is always sampled when the clock fptν rises above the zero point and is generated as the sampling output signal S.
a ^&

FIGS. 5A and 5B show a mode of scanning of the demodulated video signal in the CCD 10, FIG. 5A showing the demodulated video signal Sj _n and a scanning _{output signal S b} and FIG. 5B relating to that of the CCD 10 via the inverter 12

·

VCO 4 supplied clock signal f _CLR refers. The video signal S ^ _n supplied to the CCD 10 is sampled whenever the clock signal f _CLK rises above the zero point, and it is generated as the sampling output signal S.

As has been explained with reference to FIG. 3, the changeover switch 11 is switched over by the clock signal of the VCO 4 and a sampling output S shown in Fig. 6A is finally obtained on the output side (contact

c) of the switch 11. Figures 6B and 6C show the

Clocks f-τ τ, and ΐ _η ·, _ν to represent the sampling times.

L-LK. LLIS

As can be seen, the output signal S has a sampling frequency which is twice as high as that of the output signals.

le S and S. according to Figures 4 and 5. This pushes away

it is evident that a CCD has been operated with one clock,

which is equivalent to twice the frequency.

From the above equation (3) it follows that the fre-

frequency f of the clock fed to the CCDs 9 and 10 is only greater than 15/2 = 7.5 MHz, because the demodulated video signal has a sampling frequency of 15 MHz or more

must be scanned.
5

f _o > 7.5 MHz (9).

On the other hand, since the CCD 3 is similar to the CCDs 9 and 10, the frequency f of the clock supplied to the CCD 3 must be satisfy equation (4). Since the clock frequency f for the CCDs 9 and 10 is at least 7.5 MHz, as mentioned above, the choice of a frequency of 7.5 MHz or more for the clock generated by the VCO 4 also meets the requirements, given by the equation (4).

In this case, if a possible minimum value N. for the number of stages of the CCDs 3, 9 and 10 on a similar basis, is to be found, as explained with reference to FIG. 1, then N. from equation (6) as is obtained as follows:

10 = ^N _min (1 / 7.5 - 1/20), and therefore

^N min = ¹²⁰
25th

The use of two parallel CCDs with more than 120 levels for video signal time base correction and one CCD with more than 120 steps for the time base correction of the audio FM signal therefore fully meets the requirements of the present invention.

A table below shows a comparison between time base correction circuits according to the present invention and given according to the state of the art: 35

V / a-

Tabel

Time base correction circuit according to FIG. 1

Time base correction circuit according to FIG. 2

For the video signal

A CCD with more
than 600 steps

For the audio FM signal

A CCD with more than 600 levels

Two CCDs, each one CCD with more than 120 than 120 steps

It is therefore possible using the invention to use CCDs whose number of stages is smaller than those which is required in the prior art. It is also evident from the preceding description that the highest Frequency lower in the frequency band of the audio FM signal must be than half that in the frequency band of the demodulated video signal.

Although the present description is made with reference to an embodiment of a time base correction circuit of a video disc player, such a circle can be used in any device, in which a time base correction must be made simultaneously on two signals that have the same time base error have and where the highest frequency in the frequency band of a signal is less than half of the is the highest frequency in the frequency band of the other signal.

If a large number of signals with the same time base error and different frequency bands require a time base correction in the time base correction circuit according to the present invention, then two parallel CCDs with the same number of stages are used for one signal in a frequency band whose highest frequency is higher than that contained in the other frequency band

to reduce the number of CCD stages by operating the signal at an equivalent double frequency while only one CCD, the number of stages of which is identical to the number of stages in the other two CCDs, for the other signal is used. It is therefore possible to use CCDs whose total number of steps is much lower than that of the prior art of the technique. The overall arrangement is therefore cheaper and more economical in terms of power consumption.

Although CCDs are described as clock responsive delay elements in the above-described embodiments BBDs and bladder elements can also be used for this purpose, for example.

-Pt.

- Blank page

Claims (2)

Claims Π. Time base correction circuit for subjecting a first input signal having a time base error, the highest frequency component has a frequency that is less than half the highest frequency component is in the frequency band of the first input signal, a time base correction comprising: first and second N-stages clocked delay elements (9, 10) to which the first input signal is fed, a third N-stage clocked Delay element (3) to which the second input signal is fed, a single clock generator (4) to Generation of clock pulses, which the clock inputs of the first, second and third delay elements (9, 10, 3) are supplied, and driver means (11, 12) for equivalent operation of the first and second delay elements (-9, 10) with a frequency that is twice as high as that generated by the clock generator (4) Clock pulses. 2. The time base correction circuit according to claim 1, wherein said drive means includes: an inverter (12) for inverting a clock pulse signal generated by the clock generator (4) and for supplying the inverted clock pulse signal on the one hand (10) of the first and second delay elements (9, 10), and a changeover switch (11) for alternating Connecting the outputs of the first and second delay elements (9, 10) under control of the Clock pulses of the clock generator (4) with an output terminal.