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DE3578270D1 - Feldeffekt-transistor-anordnung und verfahren zu deren herstellung. - Google Patents

Feldeffekt-transistor-anordnung und verfahren zu deren herstellung.

Info

Publication number
DE3578270D1
DE3578270D1 DE8585104809T DE3578270T DE3578270D1 DE 3578270 D1 DE3578270 D1 DE 3578270D1 DE 8585104809 T DE8585104809 T DE 8585104809T DE 3578270 T DE3578270 T DE 3578270T DE 3578270 D1 DE3578270 D1 DE 3578270D1
Authority
DE
Germany
Prior art keywords
production
field effect
effect transistor
transistor arrangement
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8585104809T
Other languages
English (en)
Inventor
Kirby Gannett Vosburgh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Electric Co
Original Assignee
General Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Electric Co filed Critical General Electric Co
Application granted granted Critical
Publication of DE3578270D1 publication Critical patent/DE3578270D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/015—Manufacture or treatment removing at least parts of gate spacers, e.g. disposable spacers
    • H10P50/283—
    • H10P76/40—
DE8585104809T 1984-04-30 1985-04-20 Feldeffekt-transistor-anordnung und verfahren zu deren herstellung. Expired - Lifetime DE3578270D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US60546084A 1984-04-30 1984-04-30

Publications (1)

Publication Number Publication Date
DE3578270D1 true DE3578270D1 (de) 1990-07-19

Family

ID=24423751

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585104809T Expired - Lifetime DE3578270D1 (de) 1984-04-30 1985-04-20 Feldeffekt-transistor-anordnung und verfahren zu deren herstellung.

Country Status (3)

Country Link
EP (1) EP0160255B1 (de)
JP (1) JPS60254659A (de)
DE (1) DE3578270D1 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02271537A (ja) * 1989-04-12 1990-11-06 Mitsubishi Electric Corp 半導体装置及びその製造方法
JP2786307B2 (ja) * 1990-04-19 1998-08-13 三菱電機株式会社 電界効果トランジスタ及びその製造方法
GB2273202B (en) * 1990-04-19 1994-10-12 Mitsubishi Electric Corp Field effect transistor and production method thereof
US5672531A (en) * 1996-07-17 1997-09-30 Advanced Micro Devices, Inc. Method for fabrication of a non-symmetrical transistor
US5874340A (en) * 1996-07-17 1999-02-23 Advanced Micro Devices, Inc. Method for fabrication of a non-symmetrical transistor with sequentially formed gate electrode sidewalls
US5759897A (en) * 1996-09-03 1998-06-02 Advanced Micro Devices, Inc. Method of making an asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region
US5877050A (en) * 1996-09-03 1999-03-02 Advanced Micro Devices, Inc. Method of making N-channel and P-channel devices using two tube anneals and two rapid thermal anneals
US5677224A (en) * 1996-09-03 1997-10-14 Advanced Micro Devices, Inc. Method of making asymmetrical N-channel and P-channel devices
US6051471A (en) * 1996-09-03 2000-04-18 Advanced Micro Devices, Inc. Method for making asymmetrical N-channel and symmetrical P-channel devices
US5648286A (en) * 1996-09-03 1997-07-15 Advanced Micro Devices, Inc. Method of making asymmetrical transistor with lightly doped drain region, heavily doped source and drain regions, and ultra-heavily doped source region
US6027978A (en) * 1997-01-28 2000-02-22 Advanced Micro Devices, Inc. Method of making an IGFET with a non-uniform lateral doping profile in the channel region
US5923982A (en) * 1997-04-21 1999-07-13 Advanced Micro Devices, Inc. Method of making asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region using two source/drain implant steps
US6004849A (en) * 1997-08-15 1999-12-21 Advanced Micro Devices, Inc. Method of making an asymmetrical IGFET with a silicide contact on the drain without a silicide contact on the source
US5904529A (en) * 1997-08-25 1999-05-18 Advanced Micro Devices, Inc. Method of making an asymmetrical IGFET and providing a field dielectric between active regions of a semiconductor substrate
US6096588A (en) * 1997-11-01 2000-08-01 Advanced Micro Devices, Inc. Method of making transistor with selectively doped channel region for threshold voltage control
WO2009001252A1 (en) * 2007-06-27 2008-12-31 Nxp B.V. An extended drain transistor and a method of manufacturing the same
CN119873730B (zh) * 2024-12-30 2025-10-24 广州增芯科技有限公司 Mems空腔结构的制备方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52156576A (en) * 1976-06-23 1977-12-27 Hitachi Ltd Production of mis semiconductor device
US4318216A (en) * 1978-11-13 1982-03-09 Rca Corporation Extended drain self-aligned silicon gate MOSFET
DE2902665A1 (de) * 1979-01-24 1980-08-07 Siemens Ag Verfahren zum herstellen von integrierten mos-schaltungen in silizium-gate- technologie

Also Published As

Publication number Publication date
JPS60254659A (ja) 1985-12-16
EP0160255A2 (de) 1985-11-06
EP0160255A3 (en) 1986-12-30
EP0160255B1 (de) 1990-06-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee