DE3314600A1 - Digital signal processor for real-time operation - Google Patents

Abstract

Digital real-time signal processing is used, in particular, in voice transmission at low bit rate, in voice analysis and synthesis, in telecommunication (modems, echo cancellers, and so forth) in seismology and in biomedical engineering. The signal processor consists of three main components: 1. an input/output unit (2) which decouples the signal processor from the environment; 2. a computing unit (3) which processes computing-intensive basic functions of the digital signal processing, and 3. a central processing unit (1) which co-ordinates the other two units (2, 3) and processes complicated decision functions. A computer coupling circuit (48, 49, 50, 61) provides for particularly rapid synchronisation of the computing unit (3) with the central processing unit (1) and for a flexible subroutine call-up. <IMAGE>

Description

Digital signal processor for real-time operation

The invention relates to a digital signal processor for real-time operation, which has a central unit and a computing unit activated by this arithmetically the extensive data fields that arise in digital signal processing linked.

The processing of complex processing-intensive procedures the field of digital signal processing, especially since it operates in real time must be done, high speed requirements on digital computers that either only through expensive, complex mainframe systems or through specialized signals lp roze s so.ren can be solved. With technological advances in the development of highly integrated circuit components, the so-called LSI components, digital signal processors can recently be produced inexpensively that Compared to conventional mainframe systems, they are orders of magnitude cheaper and smaller and therefore ideal for use in future communications equipment are suitable. Main areas of application for digital real-time signal processing are: the voice transmission with low bit rates, the speech analysis and synthesis, telecommunications, especially modems, echo equalizers, etc., the Seismics and Biomedical Engineering.

The main areas of application have in common that analog measured values first digitized and then a class of mathematically similar processing procedures be subjected. A signal processor of the type mentioned, which is in a digital filter is used, is e.g. from DE-OS 28 40 471 (our symbol G.Bostelmann 1) known.

When using a voice transmission method with a low bit rate with the help of an analysis method from the speech signal certain model parameters (Filter coefficients, fundamental speech frequency, amplification factor) obtained in encoded form are transmitted over a message channel and in the receiver a Controlling the synthesizer for the generation of speech (e.g. IEEE Trans., Vol.ASSP-25 379-387 (Oct. 1977), E.M. Hofstetter; J. Tierny, O Wheeler Micorprocessor realization of a linear predictive code). The whole thing here with a so-called LPC vocoder (Linear Predictive Coding Voice Coder) speech analysis and synthesis processing to be performed requires the following procedures in detail: digitization of the analog voice signal, digital correlation and prediction, digital filtering, solving a matrix equation, complex search and decision-making processes for extracting the basic speech frequency and table access for parameter coding.

The number of the most processing-intensive of this vocoder method operations required is between 1 x 106 and 2 x 106 multiplications and Additions per second. Such a workload can be done with a large computer system cope, but because of the technical and financial effort involved here considered signal processing is out of the question.

A process computer does not have the required processing speed, to meet the real-time requirements. The required computing speeds can be achieved, however, if you have a process computer with a so-called Field or array processor combined. These are processors that are preferred similar operations are suitable for processing larger data fields are subject to, as they occur in digital signal processing. The disadvantage of the array processors is that they can only be used in conjunction with a process computer work.

Their use is therefore limited to laboratory operations.

For a portable device that can also be used for field tests they are therefore not suitable.

Well-known specialized signal processors either work as well only in connection with a process computer, or they are exclusively for an application (such as DE-OS 28 40 471) has been developed and thus for other applications not suitable.

The invention is based on the object of providing a powerful, to create portable and versatile digital signal processor.

In the case of a digital signal processor, this task is described at the beginning mentioned type solved according to the invention in that it has an input / output unit, those with analog-to-digital and digital-to-analog converters for data input and output and with an interface circuit for the serial output of signal parameters is provided; that the input / output unit has a shared transfer memory connected to the central unit, and that the micro-programmable fast Computing unit connected to the central unit via a computer coupling circuit is.

Advantageous further developments of the invention are set out in the subclaims marked.

An embodiment of the invention is described below with reference to the Drawing explained. They show: FIG. 1 a digital signal processor according to the invention as a block diagram; FIG. 2 shows a circuit arrangement for continuous data acquisition and for block-wise data exchange between the input / output unit and the central unit the signal processor of Figure 1; FIG. 3 shows a shift circuit in the arithmetic unit of the signal processor of Figure 1, and Figure 4 is a computer coupling circuit of the Signal processor according to Figure 1.

The signal processor according to the invention has three main components which are summarized in Figure 1 by a dashed border: a central unit 1, an input / output unit 2 and a specially designed one fast arithmetic unit 3.

The input / output unit 2 essentially consists of a microcomputer 4 - an 8-bit microprocessor 5, a program memory 6 and a data memory 7 contains -, an analog-to-digital converter 8, a digital-to-analog converter 9 and a serial interface circuit 10. It can also be a parallel interface circuit 11 have for connection to a host computer. The circuit components mentioned are interconnected by address lines 12, control lines 13 and data lines 14 and connected to a transfer memory 16. The lines that make up the individual building blocks with the environment (periphery) - i.e. with the facilities that the signal processor provide the data to be evaluated and the data to be evaluated by him and Parameter values are supplied - connect, can be seen from the drawing.

The input / output unit is used to decouple the signal processor from the surroundings. In the analog-to-digital converter 8, incoming analog signals digitized.

In the digital-to-analog converter 9, outgoing digital data are in Converted to analog signals. Both converters 8, 9 process twelve bits in parallel. the The sampling rate can be changed in terms of both hardware and software.

Parameter values are transmitted via the digital interface circuit 10 - e.g. LPC parameters - exchanged. It is a serial synchronous V24 interface trained according to the CCITT recommendation, both in half and full duplex traffic can be operated with a variable data rate. The signal processor is in the laboratory via the interface circuit 11, which acts as a bidirectional parallel communication interface is designed for a word length of 16 bits, connected to a host computer. The interface circuit is used for operation without a host computer (so-called standalone operation) 11 not required, so it can be removed. Another initialization program must then be used can be used for the microcomputer 5 controlling the input / output unit. on the other two main components of the signal processor, the central unit 1 and the arithmetic unit 3, this change has no effect.

The signal data recorded and digitized in the converter 8 are from the input / output unit 2 to the central unit 1 and the computing unit 3 for passed further processing. The values in the central unit 1 transferring signal data processed in the arithmetic unit 3 to the input / output unit 2, converted in the converter 9 into analog signals and sent to the Perppherie. the Data acquisition takes place on a continuous basis - i.e. at one sampling frequency of 8 kHz, for example, a new sample is generated every 125 psec - while the Processing of the data within the signal processor in blocks he follows. For example, 180 samples are combined to form a processing block.

To ensure continuous data acquisition with block-by-block processing To be able to connect the data is conventionally an alternating buffer system with two memories and a switchover logic, in which one memory is the input / output unit and the other memory is allocated to the central unit. From the analog-to-digital converter the data are continuously read into the memory of the input / output unit, while the data from the memory allocated to the central unit is sent in blocks Processing can be read out. If the first memory is filled with data, then the mode of operation of the two storage tanks exchanged. The signal processor according to the invention works in the same way, but only requires one memory namely the transfer memory 16 (see a. Fig. 2), whereby the circuit complexity is decreased. The input / output unit 2 and the central unit 1 have a Multiplexer 18A access to the shared transfer memory 16. Through a control circuit 18B, via the multiplexer 18A, address lines 20, 21 are data lines 22, 23 and read / write lines 24, 25 of the input / output unit 2 or the central unit 1 switched through to the transfer memory 16. The multiplexer 18A and the control circuit 18B form an arbitration circuit 17. Their operation is as follows: to one The transfer memory 16 is assigned to the input / output unit 2 at any point in time, which continuously fills it with data. At the end a data block, i.e. when the transfer memory 16 is full, the input / output unit 2 signals via a line 26 of the central unit 1 that this data block is ready for transmission stands. At the same time he gives control of the transfer memory via a line 27 16 from.

The central unit 1 receives access via a request line 28 to the transfer memory 16. This enables the transfer of a data block from the transfer memory 16 started in the central unit 1. During the entire block transfer, the Access of the input / output unit 2 to the transfer memory 16 through a line 29 blocked.

The output values of the continuously occurring during this time Analog-digital converters are stored in the internal microprocessor of the input / output unit cached. At the end of the block transfer, a delivery line 30 is the transfer memory 16 again free for the input / output unit 2, this release via the line 29 is signaled. The input / output unit 2 receives access via the line 27 to the transfer memory 16 and subsequently stores the in this continuously resulting measurement data. The one during the block transfer - the one just opposite the The filling time of the entire memory is - in the internal memory of the input / output unit Accumulated data can now also be transferred to the transfer memory 16 will. An acknowledgment line 31 serves as an additional safeguard against access conflicts on the transfer memory 16 can be avoided.

The control signals of the control circuit 18B arrive via a signal line 19 to the multiplexer 18A. This is via address lines 32A, Data lines 32D and read / write lines 32S are connected to the transfer memory 16.

The signal processor contains the central unit as the second main component 1, which - except from the transfer memory 16 and the allocation circuit 17, which they shares with the input / output unit - from a 16-bit microprocessor 33, a Program memory 34 and a data memory 35 consists. The capacity of the Program and table memory 34 is 16 bytes, for example, that of data memory 4 Kbyte.

The central unit 1 has a monitoring function for the entire system, coordinates the program sequence with the input / output unit 2 and activates the fast one Computing unit 3. It also serves to process complicated decision functions and strategies that require a great deal of programming effort. The circuit modules the central unit 1 are connected to the components of the computing unit 3 via data lines 36, address lines 37 and control lines 38 connected.

The fast arithmetic unit 3, which with regard to special processes the digital signal processing was developed, has two data memories 40, 41 with respectively associated address decoding, counting and data driver circuits 42, 43, a data allotment circuit 45, a high speed multiply-adder circuit 46 and a microprogram controller 47, which consists of a microprogram start circuit 48, a microprogram control unit 49 and a microprogram memory 50. By the microprogram control 47 is the functional sequence of Computing unit 3 controlled at the micro level. A microprogram is created by the central processing unit 1 activated via the microprogram start circuit. The microprogram control unit 49 generates an address containing a specific instruction in microprogram memory 50 responds, which controls the individual functional units of the computing unit 3 takes over. Part of the microinstruction is used to control the microprogram control unit used. The following is the mode of operation of the arithmetic unit 3 for the arithmetic Linking of data fields explained.

In digital signal processing there are often one or two data fields X (i) and Y (i) to be processed in one of the following ways: N (1) Z (j) = # x (i). Y (i + j); j = 0.1 ... jmax (j = parameter value) i = 1 N (2) Z (j) = Z X (i) ~ x (i + j); j = i = 1 Equation (1) is an example of a cross correlation.

In the event that X (i) is a set of filter coefficients and Y (i) represent a sequence of time-delayed sample values (j = O), equation (1) applies for the output values of a digital filter. Equation (2) corresponds to an autocorrelation function, which for j = O corresponds to the energy of a signal. To such basic functions of the digital signal processing as quickly as possible and thus a maximum Performance of the Achieving the unit of arithmetic is as follows Circuit structure of the arithmetic unit has been implemented (see FIG. 1).

To form the product sums Z (j) given above, the fast multiplier-adder circuit 46 is used, which has a multiplier Accumulator represents the multiplications of 16 x 16 bits and an accumulation with 35 bits.

The data fields X (i) and Y (i) are in the data memories 40 and 41, respectively filed. The data allocation circuit 45 has the task of extracting the data from these Store the two inputs A and B of the multiplier-adder circuit 46 to be fed. This results in the following possible combinations: Input A Input B memory 1 storage 2 storage 1 storage 1 storage 2 storage 2 With these combinations can be a term of the product sum within of a micro cycle. For adress switching for the two data memories 40, 41 each become an address counter contained in the circuit arrangements 42, 43 which is controlled by the microprogram. This creates a data throughput in pipelined mode that allows the speed of the multiplier to full takes advantage of: within one cycle, two new data values are read from the memories 40, 41 is applied to the multiplier inputs, while at the same time the previously laid Data values are multiplied with one another and added to the subtotal stored in the accumulator can be added. The arithmetic unit would be, as usual, with only equipped with a data memory, this would have to achieve the same throughput achieve, within one cycle with twice the clock frequency and with a corresponding Changeover in address decoding work.

The sums of products formed in the multiplier-adder circuit 46 are fed to a shift circuit 52 (FIG. 3). This circuit enables es, the output data of the multiplying-adding circuit 46 corresponding to the position of the leading bit and thus a maximum utilization of the computer word length to achieve. In the present case, scaling means moving a Data word in such a way that it is in a memory location with its most significant bit or register can be left-justified. As with a product total with input data of 16 bits each in the multiplier when adding up values with more than 32 bits can occur, the accumulator is designed so that a Summation over a total of 35 bits is possible. At the output of the multiplier-adder circuit 46 therefore initially 35 bits (bit 0 to bit 34) are available, which are scaled in this way must be that they fit into one or two computer words with 16 bits each. In addition bits no. 30 to 34 are branched off from the output word and a test and Control circuit 53 is supplied, in which the position of the leading bit is determined and a scaling signal derived therefrom. that is used to control a shift multiplexer 54 is used. At the output of this shift multiplexer 54 a scaled 16-bit word is then available. A scaling signal once determined can be permanently set for the following data values. As an example for a fixed setting is called the scaling of an autocorrelation function, where the first product sum always has the absolute greatest value. There is only one Data word with a maximum of 32 bits, this can be unscaled by the shift multiplexer 54 be taken over.

The input A of the multiplier-adder circuit 46 from the data allocation circuit 45 - as already explained - data words with 16 bits and their input B as well Data words with 16 bits supplied. The result data word after the product sumbi Idung with a maximum of 35 bits comes from the multiplier-adder circuit 46 via a Line bus 55 to the shift multiplexer 54 and via a line 56 to the test and control circuit 53. After scaling in the shift circuit 52 from the shift multiplexer 54 via an output line 57 one or two 16-bit data words to the data allocation circuit 45 and the data memories 40 and 41 are output.

A computer coupling circuit 60 (Figure 4) is used to couple the Central unit 1 with the arithmetic unit 3. It essentially consists of the microprogram control 47, i.e. the microprogram control unit 49, the microprogram memory 50 and the Microprogram start circuit 48, and a memory circuit 61, which is a register for the microprogram start address and a Cache for contains a loop counter of the microprogram. From the central unit 1 the various subroutines of the processing unit 3 addressed by their start addresses and certain parameter values - e.g. Data field pointer, number of points in a data field (Loop counter) - are transferred The data pointers are transferred by Writing to the address decode and counter circuits 42, 43. A micro-subroutine is called as follows. The computing unit 3 is initially in a Waiting state in which a microprogram (jump) command from memory 50 (FIG. 4) via line 62 and via a line 63 the jump address for the waiting state to the control unit 49 can be submitted. This has the consequence that the microprogram on the same wait instruction jumps back. When a microprogram is called, the central unit 1 will use the Start address of the program into the register via a 16-bit data line 64 the memory circuit 61 and the start logic 48 via address lines 65 and control lines meet the requirements. The start logic 48 generates from this request control signals, the output of the microprogram jump address via a line 66 from the memory 50 and at the same time via a line 67 the memory circuit 61 with the start address created by the central unit 1 on line 63. As a result, the microprogram control unit 49 executes one in the next instruction Jump to the start address of the subroutine. The loop counter (parameter value) of the subroutine, which is carried out simultaneously with the application of the track address to the memory circuit 61 was written into the buffer of this circuit, can can now be transferred to control unit 49. As long as the arithmetic unit 3 has a subroutine executes, a signal is transmitted to the central unit 1 via a control line 68, which prohibits any access to the processing unit 3. At the end of a subroutine the control unit 49 jumps back to the waiting state.

The microprogram control unit 49 addresses the via a line 70 Micropogram memory 50. The signals required to control the arithmetic unit 3 are via the lines 62, 63 (control of the microprogram control unit) or via the line bus 70 (control of the other functional units: address counter, Memory, data allocation, multiplier accumulator).

The computer coupling circuit 60 reduces the time required for the The synchronization of the central unit 1 and the computing unit 3 is greatly reduced.

In summary, the signal processor according to the invention is as follows described. Digital real-time signal processing is particularly used in speech transmission with low bit rate, speech analysis and synthesis, in telecommunications (modems, echo equalizers, etc. #), in seismics and in biomedical engineering. The signal processor consists of three main components: 1. an input / output unit 2, which decouples the signal processor from the environment; 2. a computing unit 3, the computationally intensive basic functions of digital signal processing processed, and 3. a central is called 1, which is the other two Units 2, 3 are coordinated and complex decision-making functions are processed. A computer coupling circuit 48, 49, 50, 61 enables a particularly fast Synchronization of the processing unit 3 with the central unit 1 and a flexible one Subroutine call.

Claims (6)

Claims Digital signal processor for real-time operation, the a central unit (1) and a computing unit (3) activated by this, due to the extensive data fields that arise in digital signal processing arithmetically linked, that is, it is not shown that he an input / output unit (2) with analog-to-digital and digital-to-analog converters (8 or 9) for data input and output and with an interface circuit (10) is provided for the serial output of signal parameters; that the input / output unit (2) connected to the central unit (1) via a shared transfer memory (16) is, and that the fast computing unit (3) via a computer coupling circuit (60) is connected to the central unit (1). 2. Signal processor according to claim 1, characterized in that the Computing unit (3) contains a fast multiplying-adding circuit (46) and that between the outputs of two data memories (40, 41) and two inputs (A, s) the multiplier-adder circuit (46) a data allocation circuit (45) is arranged by the on the basis of output signals of a microprogram control (47) the data to be supplied to the inputs (A, B) are specified. 3. Signal processor according to claim 2, characterized in that the Outputs of the multiplier-adder circuit (46) with a shift circuit (52) are connected, through which the output data of the MultipLizier adder circuit (46) scaled according to the position of their leading bit. 4. Signal processor according to one of the preceding claims, characterized characterized in that it is provided with an allocation circuit (17) which one Multiplexer (18A) and a control circuit (18B), via which alternately the input / output unit (2) and the central unit (1) with the transfer memory (16) get connected. 5. Signal processor according to one of the preceding claims, characterized characterized in that the computing unit (3) has a microprogram control (47), the via a microprogram memory (50), a commands from this memory processing Microprogram control unit (49) and a microprogram start circuit (48) the arithmetic unit (3) controls. 6. Signal processor according to one of the preceding claims, characterized characterized in that the computer coupling circuit (60) in addition to the microprogram control (47) a memory circuit (61) through which when enabled through the start circuit (48) a start address received from the central unit (1) and a loop counter value to the microprogram memory (50) or to the microprogram control unit (49) and thereby start a microprogram.