DE3119448C2 - Circuit arrangement for generating a cosine signal and a sinusoidal signal - Google Patents

Abstract

A predetermined but possibly variable incremental signal (Φ ↓ 1) is fed to a first or a second multiplier (M1 or M2). A difference signal (U ↓ k ↓ ↓ 1) or a sum signal (V ↓ k ↓ ↓ 1) are generated with a first or second adder (SU1 or SU2) and fed to an amplitude control (AR). The cosine-shaped signal or sine-shaped signal to be generated is fed to a delay stage (T1 or T2) via the outputs of the amplitude control (AR). The output of the first delay stage (T1) is connected to the first summer (SU1) and via the first multiplier (M1) to the second summer (SU2). The output of the second delay stage is connected on the one hand to the second adder (SU2) and on the other hand to the first adder (SU1) via the second multiplier (M2).

Description

The invention relates to a circuit arrangement according to the preambles of claims 1 and 2. It is already a digital sine wave penetrator with the preambles of claims 1 and aiiEeeebcnen characteristics known (DIi-OS 29 27713). The in the preambles of claims 1 and

»The mentioned further input of the first or second totalizer is not direct, but via a third or / iert multiplier connected to the output of the first or second delay element. These two Multipliers each receive a constant provided by a signal source at a further input signal (sine signal) supplied. Another signal source gives a constant phase shifted from this signal signal (cosine signal) to the signal input. connected to inputs of the first and second multipliers st. However, the known sine wave generator therefore has the disadvantage of a not inconsiderable circuit technology Effort.

It is now the object of the present invention to show a way as compared to the prior art with A lower circuit complexity can be done to sinusoidal and cosinusoidal Generate signals. m

The object indicated above is achieved according to the invention by the claims in claim 1 or in Claim 2 characterized sound arrangement.

Compared to the sine wave generator under consideration, the invention not only saves on there provided third and fourth multipliers and a simplification of the correction circuit with the advantage that only a single signal input is required. In the case of the marked in claim 2? th circuit arrangement also results in a particularly low circuit complexity for the Correction circuit.

An advantageous embodiment of the amplitude control circuit according to claim 1 results from the Claim 3.

The invention cosinusförniger for the production and sinusoidal signals as they are needed for the readjustment of the Normalkomponcnte and the quadrature component has proven especially, iobei a digital Trägerphasenregeiung provided at the receiving end of a data transmission system v "ir" i.

Exemplary embodiments of the invention are described below with reference to FIGS. 1 to 6. Show it:

1 shows a circuit arrangement for generating a cosine-shaped and a sine-shaped signal in:>

basic representation,

Fig. 2 shows a circuit arrangement for generating a cosine-shaped and sinusoidal signal, in which as

Amplitude control binary limiters are used,
3 shows a characteristic curve of the limiters shown in FIG. 2,

FIG. 4 shows a further characteristic curve of the limiters shown in FIG. 2. *>

FIG. 5 shows an exemplary embodiment of the amplitude control shown schematically in FIG. 1, and FIG Fig. 6 shows a circuit arrangement for digital Trugerrhasenre ^ clung in the context of a message transmission

with quadrature modulation.

The circuit arrangement shown in Fig. 1 comprises the delay elements 7Ί. 77. the multipliers MX. Ml, the summers SUX, SUl and the amplitude control AR. All components of this circuit arrangement work in a binary manner. The connections shown between the individual components each consist of several connection lines via which binary signals are transmitted in parallel. For example, eight connecting lines can be provided so that the individual transmitted signals represent binary / dials, each with ach bit. -κι

A binary incremental signal φ, which can represent the binary number 00000001, for example , is supplied via the circuit point PX. The signals that are connected to the inputs of the multipliers M 1 and Ml also represent numbers and the outputs of these multipliers emit signals which signal the products of the binary numbers. The adder SL'X forms the difference between the binary signals present at the inputs u and b and sends the difference signal Ui ,, to the amplitude control AR . The summer SUl forms the sum of the signals present at the inputs r and t / and outputs the sum signal l \ ,, to the amplitude control AR . Signals X _k , ι or ) \ ,, are emitted via the outputs of the amplitude control AR , by means of which the cosine-shaped signal sin φ <, ι is approximated. In addition, the signal X _k . , fed to the delay stage TX , whereas the signal Y _k , ι is fed to the delay stage Tl . The successive signal sections, which are distinguished by the indices k and fc + 1, are determined by the delays of these delay stages TX -ind Tl. The delay caused by the delay steps TX and Ί1 must be at most equal to half the period duration of the cosine-shaped and sinusoidal signals generated. In general, the delay caused by the delay steps TX and Ί1 will be chosen to be much smaller than half the period of the cosine-shaped or sinusoidal signals generated. In a preferred embodiment, the delay T brought about by the delay stage 71 and T1 is equal to the eight hundredth part of the period of the generated cosine-shaped and sinusoidal signals.

To explain the mode of operation of the circuit arrangement shown in FIG. I, it can be assumed that the following relationship applies with regard to the angle φ.

Ψί. II - Φί - Φ I (1) M '

The cosine functions and the sine functions of these angles can be expressed by the following equations being represented:

cose / »* ,, = cos (</) j + </> 1) = cos ψ; cos φ 1 - sin φ * sin </ »i (2)

, 1 = cu (</> (+ φι) = sin i /> _A cos ψ ₍ + cos φι si η </> ι (3)

Since the terms cos (/> i approximately equal to I and the terms siii (/) | approximately equal to φ \ , the following simplified expressions result:

cos0 (. t = cos (/) j - sin </) j φι (4)

sin </> j. ι = sin0j t-cos0 _t ι (5)

From Fig. 1 it can be seen directly how equation (4) is implemented. It is therefore assumed that the signal A \ ,, is emitted via the node PI , which is the same as the signal co: i (/> i,,. This signal was formed on the one hand from the previously occurring signal -Vj = COSi /), and on the other hand from the product sin0t ■ φι. A signal that represents this product is output via the output of the multiplier MI to the adder SUl , because on the one hand the Inkrcmcntsignal φι and on the other hand the signal K * = sin (£ i is present at the input of this multiplier. It is assumed that on Beginning with either the quantity ΛΆ or the quantity K _t or both quantities are not equal to zero, otherwise the multiplications would result in zero.

The adder .S'i'l forms the difference between the inputs ti. h applied components and generates the difference signal LU . ι. At first it can be assumed that the signals U _k , _t and \\ . so that the signal eos $ ₍ , ι is actually emitted via the sounding point PI . If the amplitude control AR were not available, the amplitude of the signal cos </> j, ι would increase continuously. However, this amplitude control AR prevents a such uiufcnui: increasing the amplitudes so that the maximum amplitudes of the signal cos ^ ₁ ,, remain constant.

Equation (5) is implemented in a similar manner, assuming first. that the signal ) \ , ι is equal to the signal sin 0j., is. With the signal V ₁ = sin φι, a component of equation (5) is already fed to the summer SUI via the input d. The multiplier Ml outputs a signal. which is the same as the product cosifo · φι. At the output of the summer SUI , the sum signal V \ , ι is thus obtained. that after a few steps the signal Y \ again. _t equals. In this case, too, the amplitude control AR prevents a continuous increase in the maximum amplitudes of the signal sin </> ₄ ,,.

In contrast to FIG. 1, FIG. 2 shows a special exemplary embodiment of the amplitude control AR \ instead of the amplitude control AR shown in FIG. This amplitude control AR \ shown in FIG. 2 consists of the two binary limiters RCl and HCI. A conceivable characteristic of these two limiters is shown in FIG. 3, another conceivable characteristic of the two limiters is shown in FIG. The directions of the abscissa relate to the signals U and V supplied to the limiters at the beginning. The directions of the ordinates relate to the signals X and Y given by the limiters until a predetermined binary value W is reached. for example, this Binärwerl W may be equal to the number of Ol 11 111 I. until Erreichendes binary value unequal thus the input signals the output signals. When the binary values of the input signal U or V is equal to or greater than the binary value W Then output signals A 'or Y are emitted which are at most equal to the binary value W. At this Wmc, a permanent increase in the muxinal amplitudes of the eosine-shaped and sinusoidal signals generated is avoided.

FIG. 5 shows the amplitude control ARI as a further exemplary embodiment of the amplitude control Λ R shown in FIG. 1. This exemplary embodiment consists of the multipliers! Λί3. MA, from the squaring stages QSX. QSI. from the summers .S '(/ 3, SUA. from the setpoint generator .SG'. from the polarity stage PS, from the switch SW and from the two generators G "01 and O ^- IO. The difference signal Ui" is sent to the multiplier M3 and a possibly corrected signal X _k , is output via its output. The sum signal V _{t t} is fed to the multiplier Λ / 4 and a possibly corrected signal Y _{k M is} output via its output Switch SW to the two multipliers Λ / 3 and • V / 4. Since the sum cos ² ^> and sin - </> must be constant, the square sum of the numbers, which is represented by the signals X and Y, must also be constant . by means of the squaring QSL or QS2 the expressions X are respectively squared! ', with the aid of the adder .St / 3 summed so as to give on the output of the actual value A, which the Quudratsummc X :., and Yi ₁ > _t . With the help of the setpoint generator SG , the

ι Setpoint B generated by the square sum and fed to the summer SUA. By forming the difference, a signal is emitted via the output of the adder .S '(. 4, which signals either a positive difference AB or a negative difference AB . With the help of the polarity level PS , the binary value 1 is assigned to a positive difference and the switch position 1 of the switch S H'eingestellt. Wcjin the difference AB is positive, then causes the polarity stage PS, the switch position I of the switch SW. the generator 6 "Ol generates a signal whose binary value is slightly smaller than one. In contrast, generated to the generator GIO a Signal which equals the value 1. If the difference AB is positive, then a signal is emitted via switch SH-'which, with the help of V / 3. Λ / 4, the binary waves of the signals U _k ,, and V \ , is slightly reduced. thus, if the square sum of the cosine and sine functions are too large, then the binary values of the signals Ut ι _f and V _{k. x} reduced. In contrast, when the difference AB is negative. then expectant en the signals Ut _{+ 1} and K _{1 + 1} nichi

■ changed because in this case the sum of squares of the cosine and sine functions is too low and anyway is continuously increased.

The components shown in FIGS. 1 and 2 can be implemented, for example, with the aid of microprocessors will.

6 shows a circuit arrangement for the transmission of a message with the aid of a modulated carrier

^: being the carrier phase on the empire with the help of the in I-ig. 1 is controlled circuit arrangement shown. It is assumed that the carrier on the transmission side is modulated in the course of a quadral amplitude modulation. For example, it can be a differential phase modulation. The data source DQ sends the data to the encoder COP in the form of bit groups. With the help of the encoder, each

- "» I 17 ttO

Hit group is assigned a phase difference and a carrier is modulated in accordance with this phase difference in the modulator MOD. The modulated carrier is via the line /. / transmitted to the receiving side. The received signal is demodulated in the demodulator DEM and the standard concept V and the quadral component '* Q are obtained. When the modulated carrier is transmitted over the line, phase and frequency shifts of the entire spectrum are assumed. With the help of the correction stage KOR , a correction of the normal component, Y and the quadrature component Q is carried out and the corrected normal component ΛΊ or the corrected quadrature component Q \ is on the one hand 'Lm comparator VGL and on the other hand, the assessment result Δ' / V '/' / uggl. For the decision stage ENT, the corrected normal component / V1 and the corrected quadrature component Q \ can be viewed as actual values, whereas the output normal component Nl or the output quadrature component Q1 can be viewed as setpoint values. The comparator VGL compares the actual values of the normal component or quadrature component with the corresponding setpoint values and outputs the already mentioned discriminator signal ψ ι to the circuit arrangement shown in FIG. 1 as a control signal. As described, this circuit arrangement emits the signals cos </>_; , ι and sin 0t, ι to the correction level KOR. Using the multipliers, V / 5, Λ / 6. MT, MS are obtained in a manner known per se, and the summers SU5. SU6 supplied, via the outputs of which the corrected normal component / Vl or the corrected quadrature componentc Q \ is emitted.

In connection with the sound arrangement shown in FIG. 6, the sound arrangement according to FIG. thus the Aiifgahe. to generate eosinus- shaped or sinusoidal signals of different phase and frequency as a function of a changing Diskriminalorsignal φι.

The dependence of the incremental signal φι on the frequency / cosine-shaped or sinusoidal signals is given by the following equation:

The delay time T is caused by the delay elements 7Ί and 7Ί. &

The signals Nl and Ql emitted by the decision stage ENT define a special phase of the «

transferred carrier. Depending on the phase differences of successive modulation sections c]

the decoder DOC determines the Uit groups assigned to the phase differences. The decoder DEC fulfills i'ij

thus the opposite function as the encoder COD provided on the transmission side. The receptive m '-j

determined η bit groups are sent to the data sink. j

For this purpose 3 sheets of drawings

Claims (3)

Patent claims: 1 circuit arrangement for generating a cosine-shaped signal (cos <fo > ,) and a sinusoidal signal (sin S _k + ,) with a binary operating first multiplier ( M 1) and a binary operating second multiplier (Ml). with a binary first totalizer (.Wl). which is connected to one input at the output of the second multiplier (Ml) and another input to the output of a first delay element (7Ί) and which outputs a binary difference signal ( U _{1 :} +,) which is the difference between the signals present at its inputs represents, with a binary operating second adder (SUl), which is connected to an input at the output of the first multiplier (MX) and a further input to the output of a second delay element (71) and the output side is a binary sum signal ( Y _{k +} , ) outputs, which represents the sum of the signals at its inputs, with a correction circuit between the inputs of the two delay devices (Tl, Tl) and the output sides of the two summers (SUl, SUl) and with a signal input (Pl). which is connected to one of the inputs of the two multipliers i> (Ml, Ml) . which each with a further input at the output of the first delay element (Tl) or. of the second delay device (T2) are connected, characterized in that an optionally changeable binary increment signal (φ, ) is input via the signal input (Pl) to the aforementioned one inputs of the two multipliers (Ml. Ml) provided as the only multipliers, and that as (, 7Ί 77) -glieder provided a Amplitudcnrcgclungsschaltung (AR) which is designed so that jj; correction circuit between the AusgangEseiten the summer and the inputs of \ i delay: _e r> _{ua (j r2>} (sul sul). _S aniine of the numbers given by the difference signal (Ui ,,) and by the sum signal ( V _k ,,) does not exceed a predetermined amount or remains largely constant. 2 Circuit arrangement for generating a cosine-shaped signal (cos φ »,,) and a sinusoidal signal (sinfou) with a binary operating first multiplier (Λ / 1) and a binary operating second ^ multiplier (Ml). with a binary first summer (SU, ). which is connected to one input at the output of the second multiplier (A / 2) and another input to the output of a first delay element (Tl) and which gives a binary difference signal ( U _k ,,) r.b on the output side, which is the difference between the its inputs present signals, with a binary operating second summer (SUl), which is connected to an input at the output of the first multiplier (Ml) and a further input at the output «ι of a second delay element (Tl) and the output side a binary Summation signal ( V _k + Ο emits which represents the sum of the signals at its inputs, with a correction circuit between the inputs of the two delay elements (7Ί, Tl) and the output sides of the two summers (SUl. SUl) and ml, a signal input ( Pl ), which is connected to one of the inputs of the two multipliers (Ml, Ml) , each with a further input at the output of the first delay erative member J <(7 "I) 'or. of the second Vcrzögei jngsglicdcs (Tl) are connected, characterized in that an optionally changeable binary increment signal (φι) is inputted via the signal input (Pl) to said one inputs of the two multipliers (MX, Ml) provided as single multipliers, and that an amplitude control sound system (AR) with two binary limiters (BGl. BGl) is provided as a correction circuit, the input signal of which ((Z ₁ ,, or K _t ,,) corresponds to the corresponding output _{signals <V 4 + 1} or K _A »,) , if the numbers represented with the input signal are smaller than specified numbers ( W), and their output signalc represent smaller numbers than the input signals, if the numbers represented by the input signal are greater than the specified numbers ( W) , that the outputs of the first or the second summer (SUl or SUl) to the inputs of the first b / w. of the second limiter (BGl or BGl) are connected and that the outputs of the first b / .w. of the /.weiden limiter (BGl or BGl) to the inputs of the first b / .w. of the second delay element (71 or T1) are connected. 3. Circuit arrangement according to claim I, characterized in that the amplitude control circuit (AR) contains a third and a fourth multiplier (/ V / 3 or M4) to which the difference signal ( l \ ,,) and the sum signal ( V ₁ , ,) is supplied and the generated cosine-shaped signal or the generated sinusoidal signal is output via the outputs that a first squaring stage (QSl ) and a second squaring stage 5 (1 (QSl) are provided, which with the DifTcrcnzsignul (ίΛ, ι) or with the sum signal (V _k ,,) and the output signals of which represent the squares of those numbers which are represented by the difference signal or the sum signal that the output signals of the first quadricrstufc (QSl) and the second squaring stage ( QSl) are fed to a third adder (.Vt / 3), the output signal of which represents an actual value (A) of the sum of squares, so that a setpoint generator (.VC) is provided which outputs a setpoint value (B) of the sum of squares, that a fourth adder (St / 4) forms the Dif.'orcnzcn the actual values (A) and the setpoint values (S) and supplies a corresponding output signal to a polarity stage (PS) , which emits a binary polarity signal and thus a first or a second Switch position (1. 0) of a switch (.SI + ') sets, depending on whether the difference between the actual values (Λ) and the setpoint values (fl) is positive or negative, that two generators (COl or GlO) produce a first or a second reduction signal generate, which represents a number less than one or a number equal to one, and that in the first or second switch position (1.0) of the Schaller (SW) the first and the second reduction signal to the third and fourth multiplier (MX / V / 4) is supplied.