DE3108342C2 - Dynamic shift register circuit - Google Patents

Abstract

A dynamic shift register circuit according to the invention has an input and an output terminal. It also contains a first transmission gate circuit (11) connected to the input terminal for taking an input signal and transmitting it under the control of a first clock signal, a converter (12) for inverting the level of an output signal of the first transmission gate circuit (11) , a second transmission gate circuit (13) connected to the converter (12) for taking an output signal of the converter (12) and for transmitting the output signal under the control of a second clock signal which has a level opposite to the first clock signal, a signal follower circuit (14 ) for supplying an output signal with a level which follows the level of the output signal of the first transmission gate circuit (11), and a logic circuit (Q ↓ 1, Q ↓ 2, C) connected to two power source voltages. The logic circuit (Q ↓ 1, Q ↓ 2, C) is activated by an output signal from the signal follower circuit (14), and it provides an inverting or converter function as a function of an output signal from the second transmission gate circuit (13). The logic circuit (Q ↓ 1, Q ↓ 2, C) comprises a capacitance or capacitor element (C), one terminal of which is connected to the output terminal of the signal follower circuit (14), while its other terminal is connected to the output terminal of the dynamic shift register .

Description

marked by

a signal follower circuit (14) for providing an output signal of a level which corresponds to the level of the Output signal of the first transmission gate unit (11) follows, and

a logic circuit (Qi, Q 2, C) connected to a first and a second power source voltage, which can be converted by an output signal of the signal follower circuit (14) f'-ti and an inverter or converter function depending on an output signal of the second transmission Gating unit (13) is able to ensure.

2. Shift register circuit according to claim 1, η characterized in that the logic circuit (Q 1. Qt C) has a first MOS transistor (QX) which is connected to the first power source voltage with one terminal and to the output terminal (OUT) with the other terminal is connected and whose gate electrode is switched to pick up an output signal of the signal follower circuit (14). and a second MOS transistor (Q 2), one terminal of which is connected to the second power source voltage and the other terminal of which is connected to the output terminal (OUT) and the gate electrode of which is connected to receive an output signal of the second transmission gate unit (13) is switched. having.

3. Shift register circuit according to claim 2, characterized in that the logic circuit (Q 1, Q 2. C) also has a capacitance or capacitor element (CC) from a third MOS transistor (Q 9), the gate electrode with the gate electrode of the first MOS transistor (Q I) is connected and its drain and source electrodes are connected to the output terminal (OUT) .

4. Shift register circuit according to claim 1, characterized in that the signal follower circuit (14) is a source follower circuit (Q 7, QS) .

65

The invention relates to a dynamic shift register circuit according to the preamble of claim 1.

Such a circuit for generating interrogation pulses with an input terminal, an output terminal. one connected to the input terminal first transmission gate unit for acceptance an input signal and for the transmission of the same under control of a first clock signal, a converter for inverting the level of an output signal of the first transmission gate unit and a second transmission gatekeeper connected to the converter Acceptance of an output signal of the converter and for the transmission of this output signal under the control a second clock signal is known from DE-OS 29 23 746 So that a circuit for - Generation of interrogation pulses which is simple in construction and a small number of Components required in each stage

In addition, various dynamic shift register circuits have already been discussed which input data hold or store dynamically and the capacitances of the gate capacitors of MOS transistors exploit. Commonly used shift register circuits of this type are a "proportionless" dynamic shift register and a shift register circuit consisting of a so-called E / D converter (Enrichment / depletion converter) and a transmission gate circuit connected in cascade with this. The E / D converter includes a depletion type MOS transistor serving as a load transistor and an enhancement type MOS transistor serving as a driving transistor.

The shift register circuit provided with an E / D converter inevitably has a direct current line. so that it has a high power consumption. The ratioless dynamic shift register also has disadvantages: its output voltage can cannot be raised to the power source voltage, and the shift register cannot provide an output signal sufficient size deductible.

It is therefore an object of the invention to provide a dynamic shift register circuit that has only one has a low power requirement and yet to deliver an output signal of sufficiently large amplitude able.

This task is performed in a dynamic shift register circuit according to the preamble of claim I solved according to the invention by the features specified in its characterizing part.

The invention thus enables a dynamic shift register circuit that changes as a result of the signal follower circuit and the logic circuit is characterized by a low power requirement and still has an output signal can deliver with a sufficiently large amplitude.

Advantageous further developments of the invention are specified in claims 2 to 4.

In the following a preferred embodiment of the invention is explained in more detail with reference to the drawing. It shows

F i g. I is a block diagram of a dynamic shift register circuit with features according to the invention,

Fig.2 is a detailed circuit diagram of the dynamic Shift register circuit according to FIG. 1 and

3A to 3H timing diagrams for Explanation of the mode of operation of the circuit according to FIG. 2.

The dynamic shift register circuit shown in FIG comprises a transmission gate circuit 11. a converter 12. a further transmission trasunes-Tnr-

circuit 13 and a signal follower circuit 14. The transmission gate circuit 11 is triggered by a clock pulse Φ controlled to control an input signal This means that the gate circuit 11 the Reading out and writing of the input signal under the control of the control clock signal Φ controls On The output signal of the gate circuit 11 is input to the converter 12 and its level through this inverted An output signal of the converter 12 is fed to the transmission gate circuit 13 ^, which is through a control clock signal pulse Φ is driven, the level of which corresponds to that of the control clock signal Φ is opposite Under the control of the control clock signal Φ, the gate circuit 13 transmits the Output signal of the converter 12.

The output signal of the transmission gate circuit II is also fed to the signal follower circuit 14 which is designed so that it follows a signal that is generated by the gate circuit 11 in its switched-through state. More precisely: the level of the output signal of the signal follower circuit 14 changes depending on the level of the output signal of the gate circuit 11. When the To. circuit 11 blocks, the output signal of the signal follower circuit 14 is held at a reference potential, ie ground potential. The output signal of the signal follower circuit 14 is applied to the gate electrode of an n-channel enhancement type MOS transistor Q \ which is connected on one side to receive a voltage + Vdd and on the other side to an output terminal OUT of the dynamic shift register circuit The output signal of the transmission gate circuit 13 is applied to the gate electrode of an n-channel enhancement type MOS transistor Qi which is grounded on one side and connected to the output terminal OUT on the other side.

A capacitor C is connected between the gate and source electrodes (ie terminal OUT) of the transistor Q). The capacitor C can also be omitted. Jen. because a parasitic capacitor is present between the gate and source electrodes of the transistor Q \. However, the capacitor CaIs is preferably provided in such a way that the potential at the terminal OUT is properly raised to the power source voltage Vm .

The following describes the operation of the dynamic shift register circuit.

Assume that the input impedance of the MOS transistor Q is high and therefore the output of the transmission gate 13 is dynamically maintained at a high level. If a high-level input signal is fed into the transmission gate circuit U while the level of the control clock signal Φ remains high, that is to say, for example, at the level of the power source voltage + Vm , the output signal of the signal follower circuit 14 is given a high level. At this point in time, the control clock signal Φ has a low level and the gate circuit 13 remains in the blocking state. Nevertheless, the output signal level of the gate circuit H is kept high. The transistor Qi is therefore switched on. As a result, the output signal at the output terminal OUT has a low level, that is to say ground potential or level. Under these conditions, the capacitor C is at a voltage V ″ which corresponds to the difference between the power source voltage V ₁ /, / and the sum of the voltage u-waves at the circuits 11 and 14

If a low level output signal of the converter 12 is fed into the gate circuit 13 while the level of the control clock signal Φ remains high, the transistor Qt goes into the blocking state. As a result, the output signal appearing at the output terminal OUT has a high level. Thereupon the level of the output signal of the signal follower circuit 14 increases practically to the sum of the

ίο voltage V, and the voltage Vdd · This means that the output signal received at the output terminal OL / Ter receives a level corresponding to the power source voltage of Vdd
F i g. 2 illustrates the construction of the dynamic shift register circuit in detail. In FIG. 2 the parts of FIG. 1 denotes corresponding parts with the same reference numerals as before

According to FIG. 2, the dynamic shift register circuit 9 contains n-channel MOS transistors Ci to Q *

a> Of these transistors, the transistors Qu Qi,

Qi. Q *, Qb, Qj and Q, from the enricher. ■ type while

the other transistors Q 1 and Qa are of the low-voltage type.

The transistor Qj forms the transmission gate

device 11. Its drain electrode is connected to the input terminal / Λ 'of the shift register circuit, while its gate electrode is connected to pick up a control clock signal Φ

The transistors Qi and Ob form the converter IZ

»The drain electrode of the transistor Q. is connected to the voltage + V & , while its source electrode is connected to the drain electrode of the transistor Ot . The source electrode of the transistor Qt is connected to a reference potential, ie ground level, and its gate electrode is connected to the source electrode of the transistor Q. The gate and source electrodes of the transistor Qi are connected to ground potential.

The transistors Qj and Qa form the signal sequence; r-

circle 14 of the source follower type. The drain electrode of transistor Qj is situated on the voltage + Vdd, J endures its source electrode to the drain electrode of transistor Q is connected. The source and gate electrodes of the transistor Q » are connected together. The gate electrode of the transistor Qj is connected to the source electrode of the transistor Qj .

The transistor Q _t forms the transmission gate circuit 13. Its drain electrode is connected to the source electrode of the transistor Qs and to the drain electrode of the transistor Qt , while its gate; Electrode for picking up a control clock signal Φ is connected.

The gate electrode of the capacitor C representing ndrr forming the transistor Q is connected to the source electrode of the transistor Q ₁ and to the drain of T ^r ansistors O ". The transistor Qt can optionally be omitted because - as mentioned - a parasitic capacitor between the gate and source electrodes of the transistor Q \

M) (capacity) is available. The transistor Q is only provided to properly raise the potential at the output terminal OUT to the power source voltage + V _d d . The drain and source electrodes of the transistor Qg are connected to the output terminal Oi / Tangeschlosf> 5 sen.

The drain electrode of the transistor Q \ is connected to the voltage + V ^ , while its source electrode is connected to the output terminal OUT . the

The gate electrode of the transistor Q \ is connected to the source electrode of the transistor Q ₁ and to the drain electrode of the transistor O% .

The transistor Q ₂ has its drain electrode connected to the output terminal Οί / T and its source electrode connected to ground. The gate electrode of the transistor Q ₂ is connected to the source electrode of the transistor Q ₄ .

In the following, with reference to the timing diagrams according to FIGS. 3A to 3H, the operation of the Shift register circuit according to FIG. 2 explained.

The transistor Q or the transmission gate circuit 11 remains switched on, while the controlling clock signal Φ (Fig. 3A) has a high level. In a similar way, the transistor Q ₄ or the transmission gate circuit 13 remains switched on as long as the controlling clock signal Φ (FIG. 3B) has a high level. In the switched-on state, the gate circuits 11 and 13 take an input signal and transmit

Assume that the output signal V4 (Fig. 3G) of transistor Q _{4 is} dynamically held high. If then a high level input signal (Fig.3C) is fed to the transistor Q ₃ , while the level of the clock signal Φ remains high (z. B. at the value of the voltage + Vm), the output, ie the source of the Transistor Q, a signal V 1 (Fig. 3D) of high level

Vdd- V _lhQi ,

where V, ho 3 means the threshold voltage of the transistor Qi . As a result, the transistor Q _{x is turned on} , the output signal V3 (FIG. 3F) of the signal follower circuit 14 going high. The level L 1 of this output signal practically corresponds

V _lhQJ ),

where V, i, Qj mean the threshold voltage of transistor Q 7.

As long as the controlling clock signal Φ has a high level, the controlling clock signal Φ has a low level. The output signal V 4 (FIG. 3G) of transistor Q ₄ is therefore dynamically held at a high level. The transistor Q ₂ thus remains switched on and the output signal (FIG. 3H) of the shift register circuit has the ground level, while the clock signal Φ has a high level. As a result, the capacitor C is charged to almost the level L 1 (FIG. 3F), which practically

Vöä- (V _lhQ} + V _lhQ7 )

is equivalent to

When a low level output signal V2 (FIG. 3E) from converter 12 is written into and read out from transmission gate circuit 13 while the level of control clock signal Φ remains high, transistor Q _{2 turns off} , with the output signal on the terminal OUT goes high. In this case, the output signal V'3 (FIG. 3F) of the signal follower circuit 14 practically rises

Vm- (V ₁₁₁₀ , + V _lhol ) + Vm

on This means that the level of the output signal is the Shift register circuit exceeds the power source voltage + Kft /.

When the output (signal) level of the transmission gate 11 is low, the transistors Qb remain. Ql and QX blocked, so that there is no direct current path in the shift register circuit. It follows that the shift register circuit consumes little power. In particular, the direct current flows only for an extremely short time, the power consumption being reduced when

in the time constant t {= Cq ₉ ■ Rq ») is significantly shorter than the time span 7; during which the input signal is applied to the input terminal / Λ /. (In the above relationship, Cq * denotes the capacitance of the transistor Qi and Rq » the resistance value of the transistor Q _1. ) For example, if r is about 300 ns, while T = 10 μδ and the period of the control clock signal Φ or Φ = 100 ns, the time span during which the direct current flows is shortened very much. The voltage V3 (FIG. 3F) or the gate voltage

J "ucs TfitiisisiiM» ζ? ' ΓιΐΐΓιϊΐΊΙ Γϊΐ'ιΐ the ZcitkcuSiSnic

V = CqI) -RqS from. However, the level of the output signal (F i g. 3H) at the output terminal OUT does not fall to the voltage Vm or below during the half period of the clock signal Φ or Φ,

- '> if the time constant t> i / f is selected, with A = frequency of the clock signal Φ or Φ \ For example, the capacitance Cq * can have a size of 1 pF, and the resistance value Rq » can be 300 kß, so that the Time constant r = 300 ns and the

ίο frequency / "can be 10 MHz, so that 1 / A = 100 ns. In this case

r (= 300ns)> l // "(= 100ns),

so that the output level of the terminal OUT during half the period of the clock signal Φ or Φ in no case drops to the voltage V ^ or below.

The invention thus creates a dynamic shift register circuit that compares with low power consumption an output signal with one of the power source voltage used capable of delivering the same amplitude.

The invention is in no way restricted to the embodiment described above, for example the signal follower circuit 14 does not necessarily have to be a source follower circuit. In its place can be a any other circuit can be used as long as its output signal is an input signal follows In the embodiment described above, the signal follower circuit 14 follows the output

signal of the transmission gate circuit 11. Alternatively, however, it can be switched so that it follows the output signal of the converter 12. Furthermore, instead of the n-channel MOS transistors, p-channel MOS transistors can also be used to form a dynamic shift register circuit. A dynamic shift register circuit formed from p-channel MOS transistors corresponds in terms of its mode of operation and its effect to the embodiment described above, provided that it is supplied with a μ power source voltage of a polarity opposite to the voltage + Vm _{, ie −V 1} *.

Various other changes and modifications are of course possible for the person skilled in the art without that deviates from the scope of the invention.

For this purpose 2 sheets of drawings

Claims (1)

Patent claims: 1. Dynamic shift register circuit, with
one input terminal / W / one output terminal (OUTJ,
a first transmission gate unit (It) connected to the input terminal for receiving an input signal and for transmitting it under the control of a first clock signal (Φ), a converter (12) for inverting the level an output signal of the first transmission gate unit (11), and a second transmission gate unit (13) connected to the converter (12) for receiving an output signal from the converter (12) and for transmitting this output signal under the control of a second clock signal (Φ), the level of which is opposite to that of the first clock signal,