DE3034124A1 - Digital measurement of time-varying values - using correction circuit extrapolating last and preceding stored measurement values - Google Patents

Abstract

A digital measurement circuit for time varying values has a transducer producing a signal of frequency proportional to the measurement value counted during measurement intervals determined by a control circuit and stored. An additional memory controlled by the control circuit holds the counter contents at the end of the interval before the last interval. A correction circuit produces a corrected value for the contents of the counter at the end of the last interval using the last and previously stored values from the memories and a fixed algorithm. The algorithm contains a linear extrapolation of the values.

Description

Circuit arrangement for digital

Measurement of a Time Varying Quantity The invention relates to on a circuit arrangement for the digital measurement of a time-varying quantity, with a transducer that converts the quantity to be measured into an electrical signal sequence converts, the frequency of which is proportional to the quantity to be measured, with one of the Transducer downstream counter, which the signal sequence via a gate circuit during is supplied by a control circuit predetermined measuring intervals and with a the first memory connected downstream of the meter.

Such circuit arrangements are generally known.

Any transducers that can be used as measuring transducers convert the measured variable into an electrical signal sequence, the frequency of which is to is proportional to the quantity to be measured. For example, it contains temperature measurement the transducer is a thermocouple whose output voltage is a voltage controlled The oscillator controls the output of a pulse shaper, such as a sine-square-wave converter is fed. For example, a transducer is used to measure mechanical stresses a strain gauge together with the mentioned voltage controlled oscillator and the pulse shaper.

When measuring speeds of rotating components are used as transducers Pulse generators are used whose output signals are in pulse form and whose Frequency is proportional to the speed of the rotating component.

Further areas of application of such circuit arrangements are the Expert familiar. There only needs to be a transducer, which is an electrical Output signal that has some relation to the quantity to be measured.

Regardless of the specific size to be measured, the said circuit arrangement has the disadvantage that at the end of the measuring interval The measured value obtained (content of the counter) only corresponds exactly to the variable to be measured if this has not changed during the measurement interval, or if exceptionally positive and negative deviations of the variable to be measured compared to a mean value cancel each other out during the measurement interval.

Since the counter is ultimately the sum or the integral of the Measuring interval forms incoming pulses, the content of the counter represents at the end of the measuring interval is the integral of the variable to be measured, taken over the measuring interval and divided by the length of the measurement interval.

If the variable to be measured changes linearly over time, the Contents of the counter at the end of the measuring interval exactly match the value of the variable to be measured at the time of the middle of the measurement interval.

For exact measurements and especially when the measured value is in a Control loop is processed further the measured value at the end of the Measuring interval is important and not a measured value in the middle of the measuring interval.

The object of the present invention is therefore to provide the aforementioned To improve the circuit arrangement in such a way that it outputs a measured value which corresponds as closely as possible to the value of the variable to be measured at the end of the measuring interval.

im This task is supported by the / characterizing part of the claim 1 specified features solved. Advantageous design and developments of The invention can be found in the subclaims.

The basic idea of the present invention is the measured value to get at the end of the measuring interval that from the counter readings of the last and a correction variable is determined for the penultimate measurement interval.

A particularly simple circuit arrangement is obtained when the correction contains a linear extrapolation.

If the linear approximation is not sufficient for the special measuring purposes, of course, a square, cubic, hyperbolic, etc. Extrapolation can be carried out as well as other extrapolation (e.g. e-function), provided that the type of change in the variable to be measured over time is known.

In the following, the invention is explained on the basis of several exemplary embodiments explained in more detail in connection with the figures.

It shows: Figure 1 is a block diagram of the invention Circuit arrangement, Figure 2 shows a timing diagram of the variable to be measured for explanation the mode of operation of the circuit arrangement according to FIG. 1; Figure 3 shows a first variant a correction circuit as used in the circuit arrangement of FIG comes; FIG. 4 shows a second variant of the correction circuit as it is in the circuit arrangement Fig. 1 is used; and FIG. 5 shows a particularly simple implementation the correction circuit of FIG. 1.

In Figure 1, the variable to be measured is a terminal 1 of a transducer 2 supplied. The transducer 2 emits a pulse-shaped output signal whose Frequency is proportional to the quantity to be measured. For this purpose, the transducer 2 can have a Measuring transducer 3 and a pulse shaper circuit 4, for example in the form of a Sine-to-square converter included. The pulse-shaped output signals of the transducer 2 reach a counter 6, preferably a DCD counter, via a gate circuit 5. The binary coded outputs of the counter 6 are with corresponding inputs of a first memory 7 connected. The outputs of the first memory 7 are corresponding Inputs of a second memory 8 connected.

A control circuit 9 is connected to the other via a control line 51 Input of the gate circuit 5 connected.

Via further control lines 61, 71, 81 it is connected to corresponding Control inputs of the counter 6 and the memory 7 and 8 are connected.

The outputs of the two memories 7 and 8 have corresponding inputs a correction circuit 10 connected, the outputs of which with corresponding inputs a further memory 11 are connected. The control circuit 9 is via corresponding Control lines 101 or 111 with control inputs of the correction circuit 10 or the further memory 11 is connected. The individual control pulses from the control circuit 9 ensure the following workflow: The control pulses on control line 51 determine the length of the measurement intervals. The gate is switched on during these measuring intervals permeable to the pulses from the transducer 2. These pulses are therefore for the duration of the pulses on the control line 51 is counted into the counter 6. At the end of the measuring interval, a short takeover pulse appears on control line 81, which ensures that the second memory 8 takes over the content of the first memory 7. A short pulse then appears on the control line 71, which ensures that the first memory 7 takes over the content of the counter 6. Then again appears a short reset pulse on line 61, which returns counter 6 to its initial value, e.g. resets the value zero. A new one then appears on the control line 51 Pulse that opens the gate circuit 5 for a further measurement interval.

After termination of the takeover pulse on line 71 thus contains the first memory 7 the content (N (tn)) of the counter 6 at the end of the last one, i.e. the last measurement interval. The second memory 8, however, contains the value (N (tn-1)) of the counter 6 at the end of the penultimate measuring interval. These two values memory 7 and 8 are in the correction circuit 10 for formation of the corrected measured value is processed. For this purpose, the correction circuit receives 10 via the control line 101 a control pulse that the operation of the correction circuit 10 starts. If the correction circuit 10 has finished its work, so a takeover pulse appears on the control line 111, which ensures that the further memory 11 takes over the final, corrected value of the variable to be measured. It should be noted that the duration of the control pulses on the lines 61, 71, 81, 101 and 111 are very short compared to the measurement interval (control line 51) so that the quantity to be measured is between the end of the last measuring interval and the presence of the measurement result at the outputs of the further memory 11 has practically not changed. The transfer of memory contents and the workflow in the correction circuit 10 therefore takes place via logic operating in parallel.

FIG. 2 shows the course of the variable G to be measured. At the point in time t0 begins a measuring interval Tn-1, which lasts until time t tn-1. Because of The counter 6 contains the temporal (here linear) change in the variable G at the point in time tn-1 does not have the correct value (N * t-1), but a value (N (tn-1)) that is here exactly corresponds to the value of the quantity G in the middle of the measuring interval Tn-1.

Similar conditions also exist during the following measuring interval Tn vdr, which runs from the point in time tn-1 to the point in time tn. At the end of this Measurement interval contains the counter 6 a value N (tn), which corresponds to the value of the variable G in corresponds to the middle of the measuring interval Tn. The correction circuit 10 is the actual value N (tn) corr from the two values Nt-1 and N (tn).

at time tn, i.e. exactly at the end of the last measurement interval Tn determined.

Figure 3 shows a first variant of the correction circuit 10 of the figure 1. The outputs of the first memory 7 have corresponding first inputs each of a first multiplier 14 'and an adder 20, preferably one Full adder connected. In Fig. 3 only one line is shown schematically. The other input of the multiplier 14 'is connected to a digital fixed value transmitter 19, which contains the fixed value F1 with the binary coded value 0.5. In the In practice, the fixed-value transmitter 19 is implemented in that the corresponding inputs of the multiplier 14 'with corresponding voltage levels (logical zero or logical One) are hard-wired.

The outputs of the multiplier 14 'are with the other inputs of the adder 20 connected. The outputs of the adder 20 are with corresponding first inputs of a subtracter 16 connected.

The outputs of the second memory 8 become an input of another Multiplier 17 is supplied, the other input of which in the same way as the multiplier 14 'with a fixed value transmitter 18, which also contains the value F1 = 0.5, connected is. The outputs of the multiplier 17 have corresponding subtraction inputs of the subtracter 16 connected. The outputs of the subtracter 16 represent the output of the correction circuit 10. They are, as shown in FIG. 1, with corresponding Inputs of the further memory 11 connected.

FIG. 4 shows another variant of the correction circuit 10. Same Parts as in Fig. 3 are provided with the same reference numerals. Compared to the variant the adder 20 has been omitted in FIG. The outputs of the first memory 7 are thus fed to one input of a multiplier 14, the other inputs of which are connected to a fixed value transmitter 15, which has a fixed value F2 = 1.5. It it can be seen that the output of the multiplier 14 has the same value as the output of the adder 20 of FIG. 3.

FIG. 5 shows a particularly simple implementation of the correction circuit 10 of Figs. 1, 3 and 4. The ultimate required multiplication of the output of the first memory 7 with a factor of 1.5 is here by a full adder 20 realized, whose first inputs are connected directly to the outputs of the memory 7 are. Its second inputs are shifted by one bit position (division by 2 or multiplication with the factor 0.5) connected to the first inputs. To the Understanding, the individual inputs are labeled with their assigned binary values.

1.5 times the value is thus at the outputs of the full adder 20 the output size of the memory 7.

Similarly, the output of the second memory 8 becomes divided by 2 or multiplied by the factor 0.5 that the subtraction inputs of the subtracter 16, the output values of the memory 8 are shifted by one bit position are fed. Here, too, are the binary values of each for clarity Places indicated. The outputs of the subtracter 16 then carry the corrected Value of the quantity to be measured.

It can be seen that the general available components of an adder or a subtracter the complete Correction circuit can be implemented in a particularly simple manner. The control line 101 (FIG. 1) is omitted from FIG. 5 for the sake of simplicity. The skilled person is familiar, like this control line 101 with corresponding control inputs of a full adder or a subtracter must be connected and what form the control pulses must have on the line 101 so that the corresponding components are correct and work on time.

In summary, the present invention makes use of conventional components a circuit arrangement with which a time-varying Size can be measured, whereby the output at the end of a measuring interval, digital value of this quantity is a good approximation of the actual value of the one to be measured Size at the end of the measuring interval. When the measured variable changes linearly over time if this value is exactly the same as the actual value at the end of the measuring interval match, although digitization errors and other interfering influences are of course not are taken into account.

All in the claims, the description and the drawings The technical details shown can be used either individually or in any Combination be essential to the invention.

Claims (8)

Claims 1. Circuit arrangement for digital measurement of a time-varying quantity, with a transducer that converts the quantity to be measured into a converts electrical signal sequence, the frequency of which is proportional to the quantity to be measured is, with a counter connected downstream of the transducer, to which the signal sequence is transmitted a gate circuit during measurement intervals given by a control circuit is supplied and with a first memory connected downstream of the counter, thereby characterized in that a second memory (8) is provided which is so controlled by the control circuit (9) is controlled so that it always the counter reading (N (tn-1)) of the counter (6) during of the penultimate measurement interval (Tn-1), while the first memory (7) of the control circuit (9) is controlled so that it each time the counter reading (N (tn)) of the Counter (6) during the last measuring interval (Tn) is omitted and that one of the two Storage (7, 8) downstream correction circuit (10) is provided which consists of the two stored counter readings (N (tn-1); N (tn) according to a predetermined Relationship a corrected counter reading (N (t (N (tn) corr) for the end of the last Measuring interval (Tn). 2. Circuit arrangement according to claim 1, characterized in that the predefined relationship is a linear extrapolation of the two stored counter readings (N (tn-1); N (tn)). 3. Switch arrangement according to claim 2, characterized in that the correction circuit (10) contains: a first memory (7) connected downstream Multiplier (14), the other input of which is connected to a fixed value transmitter (15) is a subtracter (16) connected downstream of the multiplier (14) and whose subtraction input via a further multiplier (17) to the output of the second memory (8) is connected, the other input of the multiplier with another fixed value transmitter (18) is connected and wherein the output of the subtracter (16) is the output of the Correction circuit (10) is. 4. Circuit arrangement according to claim 3, characterized in that the first multiplier (14) contains: a further multiplier (14 '), one input of which is connected to a fixed value transmitter (19), as well as an adder (20), one input of which is the output of the further multiplier (14 ') and its the output of the first memory (7) is fed to another input, the output of the adder (20) is connected to an input of the subtracter (16). 5. Circuit arrangement according to claim 3, characterized in that the fixed value transmitter (15) connected to the multiplier (14) contains the value 1.5 and that the fixed value transmitter (18) connected to the multiplier (17) has the value 0.5 contains. 6. Circuit arrangement according to claim 4, characterized in that both fixed value encoders (18, 19) contain the value 0.5. 7. Circuit arrangement according to claims 5 and 6, characterized in that that the multipliers (14 ', 17) with their assigned fixed value encoders (18, 19) through hard-wired connections between the memories (7 or 8) and the adder (20) or the subtracter (16) are implemented, the corresponding connections are made offset by one bit position between the components to be connected. 8. Circuit arrangement according to one or more of claims 1 to 7, characterized in that the output of the correction circuit (10; 16) with a further memory (11) is connected.