DE3004054C2 - Circuit arrangement for filtering out high-frequency interference - Google Patents

Description

The invention is based on a circuit arrangement for filtering out high-frequency interference components the preamble of the first claim. Such a filter is known from DE-OS 22 11 376.

In digital signal processing, in PLL circuits and mixer circuits often have the task of converting low-frequency useful signals from high-frequency To separate interfering signals.

For the applications mentioned above, a filter is desired that is in the pass band up to one Cut-off frequency has a constant transmission factor and above the cut-off frequency there is attenuation for the input signals, with the transition behavior between the pass band and stop band has the steepest possible gradient.

This object is achieved in a digital low-pass filter according to the preamble of claim 1 by the in their characteristics specified invention solved. Further developments and advantageous embodiments are specified in the subclaims. A composite signal to be filtered, consisting of vibrations with different Regarding amplitudes, an amplitude limiter is used before processing by the filter treat.

One area of application of the digital filter results, for. B. in a liinseiienbandempfänger with frequency regeneration via a PLI. loop in which a differential frequency signal is generated by superimposing the received residual carrier is obtained with an internally generated auxiliary carrier. This difference signal contains Even after passing through a limiter, high-frequency signal components that occur in the time interval of the potential change occur with a low-frequency differential frequency signal. Since the period of the difference frequency signal is measured and used to control further stages is one of high-frequency Interference-free signal required.

The invention will now be explained using an exemplary embodiment and the effect of the circuit in Use in a single sideband receiver for filtering of the high-frequency component in a differential frequency signal illustrated using a signal diagram

F i g. 1 shows an embodiment of the invention,
F i g. 2 and 3 associated pulse diagrams,
Fig. 4 to 6 different delay arrangements and

7 shows a pulse diagram for the circuit according to FIG. 6.

The filter shown in Fig. 1 includes an RS flip-flop 3, a delay arrangement 9, two AND gates 7 and 8 and two inverters 6 and 10.

A first path leads from an input terminal 1 via the logic element 8 to a set input 5 of the RS flip-flops 3 and a second way via the inverter 6 and the AND logic element 7 to a reset input 4. The U N D logic elements 7 and 8 serve as controlled gates. One output of the RS flip-flop 3 is on the one hand to an output terminal 2 of the filter and on the other hand connected to the input of the delay arrangement 9. The exit the delay arrangement 9 is on the one hand via the AND logic element 7 to the reset input 4 of the RS flip-flop 3 and on the other hand via the inverter 10 and the AND gate 8 with the Set input 5 of the flip-flop connected.

In the following it is assumed that the input terminal 1 is initially at L potential. It surrendered sicii then the in the F i g. 2 listed potentials at certain characteristic points of the circuit. The switching points are designated as follows:

/ = Input signal

A = signal at the output of the RS flip-flop

at the same time at output terminal 2

B = signal behind the delay arrangement

~ B = signal behind the inverter IO

S = signal at set input 5

R = signal at reset input 4

The reset input 4 remains blocked after a signal jump of the input signal / to Η potential until the delay time V 1 of the delay arrangement 9 has expired. Only then does the potential at point B become equal to that at point A. In the illustration in FIG. 2, the short running times of the components that occur in practice are taken into account. During a high-frequency oscillation of the input signal /, the RS flip-flop cannot be reset as a result of the delay. The gate 7 connected upstream of the reverse gate input remains blocked ^{for the time of the b r} > delay V i. Only after the delay line has elapsed can a potential at input I that has changed from H to L potential also cause a potential change at the output of the flip-flop. The process at

Resetting is basically the same as setting the flip-flop.

The effect of the circuit is shown in FIG. 3 clarifies

The in Fig. 3 shows a comparison between the signal fed to input 1 and the signal tapped at output 2. It illustrates the function of the filter when used in a single sideband receiver, in which a differential frequency signal superimposed with high-frequency interference is processed. The input signal is marked with /, the output signal with A. It can be seen that with the first brief change in potential of the input signal / from H to L, the output signal A already changes its value; but that the subsequent high-frequency oscillations do not cause any further change in potential when the output signal changes. Only after the delay time has elapsed does the output signal change its state at the first change in potential of the high-frequency oscillation and maintain this state for the duration of the high-frequency superimposition. In this way, the high-frequency interference components are filtered out

One embodiment of the delay arrangement 9 is shown in FIG. 4, a shift register is formed from two clocked D flip-flops 11 and 12 connected one behind the other. With each clock edge, the information present at the input of the respective D flip-flop is passed on to its output. Between the delay time r, the period duration of the clock T for the D flip-flops and the period duration of the input signal of the filter Ti, the following relationship must exist: τ less than F smaller0.5 Ti.

If the delay time τ is very short, the delay arrangement can also be generated by a number of gates; as in Fig. 5 shown

In Fig. 6 shows the overall circuit of a filter with a delay arrangement which is implemented with a monostable multivibrator 17 and a D flip-flop 18. The holding time Tm of the monostable multivibrator 17, predetermined for example by an RC element, can have the following relationship to the delay time TV and the period T of the input signal: TM is equal to TV and less than 0.5 Γ,. F i g. 7 shows the mode of operation of the circuit according to FIG. 6 the signals at some switching points. Short running times of the circuit blocks are also shown.

For this purpose 3 sheets of drawings

50

Claims (5)

Patent claims: 1. Circuit arrangement for filtering out high-frequency interference components, in particular in the case of a single sideband receiver, in which the output signal is fed back to the input via a delay stage and the input signal is passed through two AND gates, characterized in that that a flip-flop (3) with set (5) and reset input (4) is provided that the output signal the flip-flop (3) is fed to the input of the delay arrangement (9) that the input signal of the digital low-pass filter via the AND gate (8) to the set input (5) and inverted Form via the AND gate (7) the reset input (4) the flip-flop (3) is fed and that the AND gates (7, 8) also from the output signal or are controlled by the inverted output signal of the delay arrangement (9). 2. Circuit arrangement according to claim 1, characterized in that the flip-flop (3) through an R / S flip-flop (3) is formed. 3. Circuit arrangement according to claim 1 or 2, characterized in that the delay arrangement (9) is formed from at least one trigger stage (11) operating as a D flip-flop. 4. Circuit arrangement according to claim 1 or 2, characterized in that as a delay arrangement (9) a series connection of several logic gates (13,14,15,16) is used. 5. Circuit arrangement according to claim 1 or 2, characterized in that as a delay arrangement (9) a monostable multivibrator (17) is used and that the cutoff frequency is determined by the time constant an R / C link is formed.