DE3000847A1 - METHOD FOR DEVELOPING DOPED ZONES IN A SUBSTRATE - Google Patents

Description

PATENTANWÄLTE ZENZ & HELBER · -D 43OO ESStN ι · AM fkUHRSTElN 1 · TEL .: (02 01) 4126 Page - y -Ö I 189

INTEL CORPORATION 3065 Bowers Avenue, Santa Clara, California, V.St.A,

Process for forming doped zones in a substrate

The invention relates to a method of training doped zones in a substrate and in particular on the Formation of source and drain zones or the like for MOS field effect transistors using shadow masking methods.

In the manufacture of integrated circuits, e.g. B. MOS circuits, a masking pattern using photolithographic techniques is often used. This pattern then becomes used as a mask during subsequent etching of other layers. This is the case, for example, in the manufacture of field effect transistors an oxide layer is usually formed over a polysilicon layer. A photoresist is then used for definition the outlines of gate zones in the oxide layer. The oxide layer then serves as a mask, while the polysilicon layer is etched.

These and similar processing steps occur frequently Undercuts of the masking elements; For example, the silicon is etched from the side and hangs across from the polysilicon gate zone. This overhanging Areas that result from the masking of oxides, silicon nitride layers, photoresist layers, etc., can be exploited in some cases

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BÄÖ ORIGINAL

Some methods "take advantage of the shadows cast by the overhanging areas during the ion implantation. This is done, for example, by protecting the areas below the overhangs from the ion implantation. An example of this method is in US Pat. No. 3,823 352, column 4, lines 32 ff. Other documents describing the utilization of overhangs and undercuts are US Patents ¹ η 3,761,785, 3,351,379, 3,961,999 and 4,060,427 Complicated, especially when the overhangs are used to completely block the dopant implantation into the underlying zones, which is mostly done to establish alignment with one or more circuit components.

The invention is based on the object of the overhangs utilize partial blocking of the dopant implantation in the substrate, in order to achieve an exact alignment in this way of circuit elements and doped zones with minimal manufacturing steps. This should the Miller capacitance can also be reduced and the piercing properties improved.

For this purpose, the invention proposes a method that can be used primarily in MOS technology for the formation of Source and drain zones in a substrate. The substrate has a gate oxide layer and one over the gate oxide layer arranged polysilicon layer. A masking layer is provided on the polysilicon layer in such a way Pattern formed so that the gate electrode can be defined. The polysilicon layer and the gate electrode are then etched educated. The etching is continued until the masking layer is undercut, which causes the masking layer to penetrate Overhangs. Next, the substrate is ion implanted to pass through the source and drain regions

- 3 03032/057

BATH ORIGINAL

To form implantation through the gate oxide layer. the Implantation takes place in such a way that the dopant concentration below the overhanging areas during the implantation is significantly less than that of the masking element unprotected substrate zone is. During the subsequent processing steps occurs in the area of the lower dopant concentration practically none Diffusion, which results in a precise alignment between the gate and the source and drain regions. To this In this way, the Miller capacitance is reduced and the result is improved penetration properties.

An example of the invention is explained in more detail below with reference to the drawing. In the drawing show:

1 shows a partial section through a substrate

with a gate oxide layer, a polysilicon layer, an oxide masking layer and a photoresist layer;

FIG. 2 shows the substrate according to FIG. 1 after masking and etching, in which a gate oxide masking zone is formed;

3 shows the substrate according to FIG. 2 after etching

the polysilicon layer, overhanging areas being formed by side etching;

FIG. 4 shows the substrate according to FIG. 3 during an ion implantation, with the source and Drain regions are formed; and

FIG. 5 shows the substrate according to FIG. 4 after additional processing, including one Re-oxidation step o

The following describes a MOS method for forming source and drain regions or similar regions in a substrate described. Special details, such as special dopant concentrations, gate widths, etc., are also specified here To make the invention easier to understand »It is clear, however, that these particular details of implementation

«= A -

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of the invention are not required. On the other hand will be known manufacturing steps are not described in detail so as not to burden the explanation of the invention unnecessarily.

The method steps newly provided according to the invention can be used with a variety of known MOS processes will. In the embodiment described, these process steps are carried out with that described in US Pat. No. 4,052 229 described MOS method is used. In the following Description will be made of the known "front end" steps, e.g. B. the formation of field oxides, no longer explained.

In Fig. 1 is a p-type monocrystalline silicon substrate 10, which in a preferred embodiment approximates a dopant concentration of 50 ohm-cm. An oxide layer 12 (silicon dioxide) is formed on this substrate. This oxide layer isolates that Substrate opposite the gate electrodes of the field effect transistors and is therefore referred to as the gate oxide layer. at In the exemplary embodiment described, this gate oxide layer 12 is approximately a thermally grown oxide layer 400 S thickness.

After the gate oxide layer 12 is formed, a layer of polycrystalline silicon (polysilicon) is placed over the gate- Oxide layer formed. In the exemplary embodiment described, this polysilicon layer has a thickness of approximately 5500 A * and is doped to improve the etching effect. An oxide layer 16 is formed on the polysilicon layer 14. This oxide layer is used for masking purposes and has in the embodiment described, a thickness of approximately 800 A. A photoresist layer 18 is then over the oxide layer 16 is formed.

Reference is now made to Fig. 2, according to the conventional one photolithographic methods of masking the

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BAD ORiGiMAL

Photoresist layer and used for etching for the definition of the mask ISa. Then the oxide layer 16 is etched, to define a masking part 16a. In the exemplary embodiment described, the masking part 16a is used for definition the gate region of a field effect transistor, which has a width of approximately 3 µm. After the masking part is formed 16a, the photoresist layer 18a is removed.

Next, as shown in FIG. 3, the masking oxide part 16a is used as a mask for the polysilicon layer 14 during its etching is used, defining the gate region 14a. This etching step is controlled in a known manner such that As shown in FIG. 3, a side etching occurs under the masking part 16a. This leads to overhanging Sections 20 which protrude from the gate region 14a. In the embodiment described, the overhangs are by an amount of about 0.5 µm (with a gate width of 2 µm) over the gate region 14a. In the example described a wet etch is used to etch the polysilicon; however, it is possible that the same result will result to achieve omnidirectional plasma etching.

The substrate is then subjected to ion implantation to define the source and drain zones in a field effect transistor. In the example described, an arsenic implantation is used to form the η-conducting source / drain regions 22 and 24 of an n-channel component is used. It should be noted that the source and drain zones by ion implantation through the Gate oxide layer 12 can be formed = (This distinguishes the invention from the process described in US Pat. No. 4,052,229 and makes an etching step required in this known method to define the openings in the gate oxide layer unnecessary for doping the source and drain zones <>) The strength of the ion implantation is controlled according to Fig. 4 so that that some implantation through the overhanging portions 20 to form more lightly doped tails

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BATH

the source / prain zones 22 takes place. As mentioned above, the gate oxide layer 12 has a thickness of approximately 400 S, and a high proportion of the arsenic is incorporated into the the masking part 16a implanted unprotected zones, under the overhanging portions 20 the ions through the SOO A * thick masking sheet 16a and then through pass through the 400 A thick gate oxide layer. As shown in Fig. 4, zones 22 are thereby formed, which much less than the zones 24 are doped. In the example described, this arsenic implantation occurs at an energy level of 125 keV, with a doping

15 2 substance concentration of approximately 3 χ 10 / cm in the zones 24 is achieved. Approximately 90% of the arsenic ions pass through the 400 % thick gate oxide layer. However, only about 5 % of these ions pass through the 1200 R thick oxide layers from the combination of the masking part 16a and the gate oxide layer 12.

In the example described, the masking part 16a consists of an oxide layer. Other masking parts can be used for the used for the same purpose, namely for the formation of a mask for the polysilicon during the formation of the gate region including side etching and a partial barrier to the ions. For example, a silicon nitride layer or a thin layer of photoresist can be used.

In many known MOS processes, the source and drain zones are aligned with a gate electrode (without substantial overhangs) endowed. During the subsequent high-temperature processing steps, z. B. during reoxidation steps, is located in the source and drain zones Dopant diffuses further into the substrate and is further diffused laterally under the gate zone. These Diffusion under the gate zone causes an overlap between the source and drain zones and the gate zone. From this it follows

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3Q0Q847

stray capacitance between the gate electrode and these zones, which can frequency response at high frequencies and reduce the switching speed of the transistor and is commonly referred to as Miller capacitance. aside from that the increased channel depth has the effect of worsening the punch-through or push-through properties of the transistor. The rate at which this diffusion occurs during subsequent high temperature processing steps is a function of dopant concentrations. In reference to on Fig. 4 can be shown that during subsequent processing steps, the more heavily doped zones 24 with a diffuse at a much higher speed than the more lightly doped zones 22.

In Fig. 5 it can be seen that during the subsequent high temperature processing steps the zones 24 according to FIG. 4 diffused and partially corresponding to the zones 24a in FIG. 5 under the overhanging portions 20 are side diffused. However, they do not diffuse to the extent that they interact with the Gate zone 14a come into overlap. The less doped zones 22 according to FIG. 4 diffuse because of their lower Dopant concentration very little, so only a very little overlap (approximately 0.25 µm) between these zones and the gate region 14a occurs in the described method. These zones are after the high temperature machining steps have been carried out shown as zones 22a in FIG.

It has been found that the effects of side diffusion of the Zones 22a are minimized by having the gate oxide above these zones during a re-oxidation step is thickened. This means that the gate oxide is somewhat in the region 28 which lies directly above the edges of the zones 22a is thicker than the gate oxide layer 12. Using the procedure described above, the Miller capacitance was

—4
2 χ 10 px / um gate length. This is a considerable

-4 improvement against the value of the Miller capacitance of 5 10 pf / um

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Gate length in known methods.

It is clear to those skilled in the art that only part of a substrate is shown in FIGS. During and between the treatment described in connection with FIGS Substrate for the formation of buried contact zones and other components are carried out in accordance with the usual manufacturing technology of integrated circuits.

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Claims (5)

PATENTANWÄLTE ZENZ & HELBER · D 4000 ESSEN ι · AM RUHRSTEIN 1 · TEL .: (02 01) 41 2o page - ^ f- I ^ 89 INTEL CORPORATION patent claims 1. A method for forming at least one doped zone in a substrate in alignment with a circuit element, wherein a masking part for defining the outline of the circuit element is formed on a layer and the layer is etched using the masking part as a mask to delimit the circumference of the circuit element until the masking part overhangs outwards over the circumference of the circuit element, characterized in that that a dopant is introduced into the substrate by ion implantation to form the at least one doped zone and the implanted ions are dosed so that they are partially blocked by the overhanging portions, whereby a more lightly doped region is created below the overhanging sections as an extension of the doped zone which can diffuse only insignificantly under the circuit element in subsequent treatment steps. 2. The method, in particular according to claim 1, for forming source and drain zones in a gate oxide layer and a substrate containing a polysilicon layer using MOS technology, with a masking part on the Polysilicon layer formed in a predetermined pattern and the polysilicon layer to form a gate region is etched using the masking part as a mask that the masking part is undercut, whereby over the gate zone overhanging portions are formed, characterized in that the Substrate for the formation of the source and drain zone through the 003 ^ / 057 Gate oxide is subjected to ion implantation and the dosage of the implanted ions is chosen so that in the substrate areas below the overhanging sections a lower dopant concentration than in the vom Masking part is implanted in unprotected substrate areas. 3. The method according to claim 2, characterized in that an oxide layer is used as the masking part. 4. The method according to claim 2 or 3, characterized in that an arsenic implant is used in the ion implantation will. 5. The method according to any one of claims 2 to 4, characterized in that the areas of lower dopant concentration are brought to 0.5 to 5 % of the dopant concentrations in the areas unprotected by the masking part, 03.032 / 0 ^r -71 BAD