DE2923365A1 - FIELD EFFECT TRANSISTOR FOR THE FORMATION OF A STORAGE CELL AND METHOD OF MANUFACTURING THE SAME - Google Patents

Description

- 5 - Patent attorneys

Prince - Dr. G. Hauser - G. Leiser

Ernsbergerstrasse 19

8 Munich 60

THOMSON - CSF June 8, 1979

173, vol. Haussmann 75008 Paris / France

Our sign; T 5255

Field effect transistor for forming a memory cell and method for producing the same

The invention relates to a field effect transistor which has an electrically writable and erasable memory cell forms, a method for its production and a semiconductor memory formed therefrom. General deals the invention with electronic active devices, which are realized from semiconductors and under the designation "non-volatile memory" are known. In such arrangements, the remains in the form of grouped charges Receive information stored in privileged areas of the arrangement in the absence of electrical power. The information "written" in the memory, i.e. stored information, is consequently kept and found intact, even if the device to which the memory belongs is switched off and then started up again.

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The non-volatile memories contain a plurality of elementary memory cells, each with a memory point which, depending on its state, corresponds to a high or low state in Boolean logic. Each memory cell contains an active element whose properties depend on the information to be stored can be changed.

However, there are several types of "non-volatile memory", depending on whether their content is defined during production or can be changed by the user as required. The first type of "read-only memory" includes the memory which is only intended for read-out and is generally called "ROM" (read only memory). Your prior to the production of certain content remains unchangeable, since it depends on the state of memory at the end of manufacture.

This lack of flexibility in the use of ROMs resulted in the creation of user-programmable ones This is based on memories, which are briefly referred to as "PROM" (programmable read only memory). In such a PROM the memory content is caused by processes such as breaking a transistor junction or blowing a "fuse" inscribed in a circuit.

The programming of a memory by its user is already a significant step forward; with regard to the deletion, however, there remains a serious shortcoming: If the programming is irreversible, an error cannot be deleted and the memory contents cannot be changed will. In such a case, the entire memory circuit must be replaced. One on a different programming process based solution allows erasure by exposure to intense ultraviolet light; at this one However, the operation of the device must generally be required

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must be set and the printed circuit boards carrying the memory devices must be taken out to expose them to ultraviolet radiation, which is another disadvantage.

The solution that combines the most advantages is indisputably the solution in which electrical means are used for all three operations, that is to say writing, reading and deleting the memory contents. These non-volatile memories with electrical erasure are generally referred to as "EAROM", which is the abbreviation of the Anglo-Saxon term "electrically alterable read only memory". Since the duration of writing or deleting information is generally longer than the time required for reading it out, these memories are also referred to as "fast reading out" or "RMM" (read mostly memory).

With the non-volatile, electrically writable and erasable memories, which are hereinafter referred to as "EAROM" for the sake of simplicity, can have memory cells a bipolar transistor can be formed in each case. In general, a field effect transistor is used as the active element Used with an insulated electrode, as this is a better way to store information.

An essential characteristic of such transistors is the minimum voltage referred to as the threshold voltage which must be applied to the gate in order to bring this arrangement into the conductive state. This threshold voltage is changed in order to store information, the readout being that the voltage required to achieve the conduction state is measured and the state of the memory cell is checked.

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There are therefore three electrical states of the memory, depending on whether it is a read operation, a write operation or an erase operation.

If the voltage between the drain electrode and the source electrode of the field effect transistor is denoted by V ₀₃ and the gate voltage is denoted by Vq, then the storage contents are read out by a voltage

^V DS1 ■ ^V G1 '
reading is achieved by means of a voltage

^V DS2 " ^V G2 ^;
the deletion takes place through a voltage

^ Substrate * °

The following equations also apply so that the read voltage does not delete the information written are fulfilled:

DbI Ub ^ ^ substrate ^V G1 < ^V G2 < ^V G3

The change in the threshold voltage of a field effect transistor is achieved in a known manner in two ways.

The first way is to provide a transistor in which the gate electrode insulation is made up of two dielectric layers of different types is composed ■; with MNOS (metal / nitride / oxide / silicon) transistors it is e.g. an oxide and silicon nitride.

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By applying a "bipolar voltage to the gate" can a charge or discharge of the interface between the two dielectric layers and consequently a change of the threshold value de3 memory transistor can be reached. However, this solution presents two major difficulties tied together:

The isolation of the memory cell is necessary to enable a polarity reversal when writing and when erasing, and

an improvement in the enrollment conditions either leads to a reduction in retention capacity or to a Deterioration of the erasability of the memory cell, wherein these two characteristics can be determined by a very thin oxide layer (2 to 5 x 10 "^ m).

A second possibility for changing the threshold voltage of a field effect transistor is that the charge a floating electrode is changed by the injection of electrical charge carriers, which in the silicon one Sufficient energy is given so that they reach the potential threshold Si / SiOp can overcome. These so-called "hot" charge carriers are in the underlying Transitions of the memory transistor gained in the reverse direction are polarized.

In such a solution, the gate dielectric thickness values be larger, since the charge carriers have sufficient energy to reduce the conduction band of the dielectric to reach. So the retention or adhesion is very good, the charge accumulated on the electrode however, it is difficult to eliminate.

These so-called FAMOS elements (floating avalanche MOS) are initially erased by making the dielectric conductive through exposure to ultraviolet light

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is moved. However, this tedious process leads to an erasure of the entire memory and requires a complicated housing of a special design.

There are other solutions to charge or discharge the floating electrode that are simpler than extinguishing by ultraviolet radiation. These solutions are different, depending on whether they are written on the electrode injected charges are sent out again or compensated by opposite charges.

The solutions of the first type, in which the stored Charges are emitted or diverted again, require the application of high voltages and use of a thin Dielectric, so that the electrons stored on the floating electrode can flow away through the dielectric and either the semiconductor substrate or another electrode called a control electrode or gate and is arranged above the floating electrode.

If the leakage of the charges to the substrate is localized, for example, in the thin oxide region of the source electrode of the transistor this area must be doped before the floating electrode is deposited and engraved. Through this the advantage of the automatic positioning or arrangement is lost that from the reverse temporal Sequence results in the engraving and diffusion processes, which sequence enables the To neglect positioning deviations or tolerances and to reduce the size of the components.

If the charges are dissipated through the control electrode or the gate, it has been proven experimentally became - the deletion much more effective if the -

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floating electrode is formed from polycrystalline silicon of conductivity type P. This condition is although not absolutely mandatory, it is, however, in the implementation of transistors with one channel faster N-conductivity and not with N-electrode easy to meet.

In the so-called "silicon gate technology", namely, the drain electrode, the source electrode and the gate electrode are used generally doped at the same time and are therefore of the same conductivity type.

All previously known solutions for deleting the contents of a rewritable memory therefore have basic Defects, be it in terms of manufacture or in terms of application; in particular is the erasure with ultraviolet light lengthy and difficult.

In the case of storage arrangements that enable the floating electrode to be charged and discharged through charge compensation, these deficiencies do not occur. The electrical charge and discharge of the floating electrode are carried through Reached electrical particles that are injected from the layers below, i.e. by electrons with negative charge and "holes" with positive charge. A "hole" corresponds to a missing electron; It is about thus a fictitious particle of the same fictitious mass as the electron, with the same electrical charge, its sign however, is opposite.

Depending on the way in which the charge compensation is chosen, the floating electrode of the memory transistor becomes charged with "hot" electrons and then discharged or positively charged with "hot holes".

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The invention "is concerned in particular with such non-volatile memory cells in which the threshold voltage the control electrode or gate electrode of the field effect transistor is changed by charge compensation.

The object of the invention is therefore to create a field effect transistor which forms a memory cell and differs from the above Defects outlined is free. Furthermore, a procedure to produce this transistor.

To solve this problem, the field effect transistor is the initially mentioned, characterized in that a locally overdoped area is provided which automatically is aligned with the edge zones of the channel and the punctiform Localization of the electrical charge carriers is ensured, from the source region and the drain region too the floating electrode are injected, whereby the threshold voltages of the transistor are changed, the correspond to the read operations, write operations and erase operations of the memory cell contents.

The method for producing the field effect transistor according to the invention is defined in claim 5.

Further features and advantages of the invention emerge from the description of exemplary embodiments on the basis of FIG Characters. From the figures show:

1 shows a schematic illustration to explain the change in a threshold voltage due to the flow of charge;

2 shows a schematic illustration to explain the change in a threshold voltage by charge compensation;

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3a shows a plan view, FIG. 3b shows a sectional view along line aa 'and FIG. 3c shows a sectional view along line bb ¹ in FIG. 3a in the case of a field effect transistor according to the prior art;

4 views of a field effect transistor according to the invention corresponding to the sectional views of FIG. 3; and

5 shows different stages (a to f) of a method for producing the memory cell according to the invention.

Fig. 1 shows schematically the flow of electrical charges in a field effect transistor, which from a source electrode 1, a drain electrode 2 and a control electrode or a gate 3 is formed. The channel is the area which separates the source and drain electrodes from each other. Charges 6 injected through from the drain electrode 2 "Hot" electrons are formed at the interface between the two dielectric layers 4 and 5 deposited: this interface is the equivalent of a floating electrode. The change in the threshold voltage the control electrode 3 is achieved by the flow of charge, either towards the substrate on one 7 and through the dielectric layer 4 or to the control electrode 3 on another, with 8, which leads through the other dielectric layer 5.

Fig. 2 shows schematically the charge compensation. Here too the elements forming the field effect transistor are shown, namely the source electrode 1, the drain electrode and the control electrode 3. However, the floating electrode 9 is in contrast to the transistor shown in FIG realized by a semiconductor area in which it is

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preferably silicon with N conductivity. In addition, there is an area 10 of the channel that is connected to the Source electrode 1 is common, P-overdoped, while the Channel in the embodiment shown, N conductivity having.

The floating electrode 9 is negatively charged by the hot electrons 6 and then positively charged by the hot holes 11 charged. This can be achieved, for example, in that, given a suitable polarity, the control electrode 3 has a positive Voltage is applied to the drain electrode to inject electrons into the floating electrode, or by a positive voltage is applied to the source electrode to inject holes.

This technique, which is based on the successive injection of "hot" holes or electrons, generally leads to a specialization of the junctions or simply to the localization of a P ⁺ -doped region in the N-channel as shown in FIG that the generation of hot charge carriers is facilitated.

The deletion of the content is determined by the formation of this overdoped area in the channel of the transistor, and with the previous arrangements, additional engraving and doping are required for this. The minimum The surface covered by these areas is given by the surface of the smallest engraved opening and by the allowed positioning tolerance with respect to the source transition.

Dimensions of 4 χ 4 η for the opening currently appear to be a minimum that cannot be improved if a deviation of t 1 u in the arrangement of the control electrode with respect to this area is to be maintained.

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The invention enables these steps to be eliminated and the creation of areas that are locally overdoped and automatically according to the channel side areas of the Memory transistor are aligned.

The reduction in size of these surfaces leads to a reduction in size of the memory cell and consequently to an increase in the amount of memory.

Fig. 3 shows in greater detail a transistor of the type shown in Fig. 2, namely in Fig. 3a as a plan view, in Fig. 3b as a section along line aa ¹ and in Fig. 3c as a section along line bb ^f in Fig. 3a .

The following elements can be found in these figures:

the N ⁺ -doped source electrode region 1;

the N ⁺ -doped drain electrode region 2;

- The control electrode 3, which is preferably formed from Si;

the floating electrode 9, which is preferably made of N-doped silicon;

- an insulating oxide "4;

the P ⁺⁺ overdoped region 10, by means of which the voltage maintenance of the source electrode 1 is locally reduced and the injection of holes to the floating electrode is facilitated, specifically in the zone marked T; for explanation, a zone E is also drawn in, from which the electrons from the drain electrode are injected into the floating electrode;

a P ⁺ insulating region 12 which separates the transistors in a substrate P from one another.

Such a transistor is described in US Pat. Nos. 3,986,822 and 4,016,588, except for some details.

In this embodiment, the successive

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Injections of electrons into the floating electrode on the drain side and holes into the floating electrode Electrode on the source side through different doping of the channel areas and those on the control electrode applied polarity controlled. There are numerous improvements, especially local thinning the oxide layers of the channel, provided to improve the avalanche conditions.

However, as can be seen from Fig. 3, the P ⁺⁺ overdoped region 10 occupies a large area in the channel, and its asymmetrical arrangement there determines the charge, discharge and readout characteristics of the transistor, while the floating electrode and the control electrode with respect to it of the channel are arranged and designed symmetrically.

In the arrangement according to the invention, the asymmetry between the drain junction and the source junction is achieved by an asymmetry in the coverage of the floating electrode by the control electrode, and the P ⁺⁺ overdoped area is achieved by the particular implementation method used, which is based on the application of a method for local Oxidation is based to allow the oxide layer 4 to grow in a special way.

4a, 4b and 4c show the asymmetrical structure of a transistor according to the invention; these figures are respectively to be compared with FIGS. 3a, 3b and 3c.

The following similarly labeled elements from FIGS. 3a to 3c are again in FIGS. 4a to 4c:

the N ⁺ source area 21;

the N ⁺ drain area 22;

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- the control electrode 23;

the floating electrode 29;

- the insulating oxide 24;

the P ⁺⁺ -doped area 20, which fulfills the same task as the P ⁺⁺ -doped area 10 in FIG. 3.

The difference between the known transistors and this transistor according to the invention can easily be seen: an imbalance between the source junction and the drain junction results from the asymmetry of the control electrode and the floating electrode and is used during manufacture achieved as a result of the asymmetry of these electrodes, and not as a result of a special diffusion. The asymmetry of the electrodes results from simple and precise engraving processes in the corresponding silicon layers, and these electrodes fulfill the task of masks, which the source electrode and the drain electrode during subsequent diffusion processes of the source and drain implanted layers partially cover.

By using the local oxidation so that the oxide layer 24 grows, not only the automatic alignment of the P ⁺ -doped region 20 with the diffusion of the source electrode 21 and the drain electrode 22 (FIGS. 4a and 4b) is achieved, but also with the channel edges, as can be seen from Fig. 4c. By choosing the doping of this area, it can fulfill the usual task of isolating the transistors from one another, and at the same time the function of the P ⁺⁺ over <
Meet Figs. 3a, 3b and 3c.

early the function of the P ⁺⁺ overdoped area 10 in

The arrangement of the hole or electron injection regions is shown in FIG. 4a on the side of the source electrode (T) or Drain electrode (E) shown.

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The significant reduction in size and localization of the areas intended for the injection of holes in an area complementary to the area for the injection of electrons, at the channel edges, makes it possible to obtain a very high efficiency in injecting the holes in conjunction with a very low one Aging of the storage cell. The precise localization (<1 u) of the plasma generated during the avalanche breakdown of the junctions enables an improvement in the efficiency of the injection of hot charge carriers and a weakening of the trapping effect of the electrode dielectric, which causes the "fatigue" of such arrangements.

The precision achieved by the method used here is higher than with the known methods and is made possible a reduction in the size of the memory cell transistor, so that consequently more memory cells thereon Semiconductor crystal can be arranged and so the capacity of memory circuits can be increased.

The following description of the manufacturing process facilitates understanding of the structure of the memory array transistor which is the subject of the invention, and the therewith associated advantages, especially with regard to manufacturing.

The manufacturing process used is based on the technique of localized or localized oxidation, which is the abbreviation for "LOCOS" leads, and on a technique in which silicon is used for the control electrode or the gate will. In the LOCOS technique, the thermal oxidation is masked by a layer of silicon nitride, while with the silicon gate technology a masking the drain-source diffusion through a grid of polycrystalline Silicon takes place. Besides these two techniques will

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Ion implantation is applied, whereby a very satisfactory function of the memory cell is achieved.

The embodiment described here as an example is shown in FIG Figures 5a to 5f, each figure showing the arrangement shows at the end of a step.

Fig. 5a shows the arrangement after engraving of the silicon nitride (Si, Nr) layer 42, which is deposited on a silicon oxide (SiC ^) layer 41, which is obtained by thermal oxidation of a silicon substrate of the P-type <100> and its Surface resistivity is 6 to 12 ohms / cm. In this application, a thickness of the order of 7 x 10 "µ (700 Å) is suitable for the silicon oxide layer and 0.1 µ (1000 %) for the silicon nitride layer. The two P ⁺ regions are implemented by implantation.

The first area I ^, which is formed in the areas that are oxidized, defines at the same time the doping of the field areas and the lateral parts of the channel. The second Implantation area ^ - enables the realization of a more heavily doped layer than the starting substrate. This doping takes place without masking in the entire memory part the circuit and allows the control of the threshold voltage and the breakdown voltage of the transistors.

The implantations I ₁ and I ₂ are dosed in such a way that, in the finished arrangement, the avalanche breakdown takes place safely in the central or lateral areas of the channel, depending on the polarity of the control electrode.

A ^- X ρ

With a dosage of 10 A / cm for boron in the range Ι _Λ

12 2

and from 10 A / cm for the range I ^ changes in the threshold voltage of ί 5 V are achieved for pulses between 20 and 30 V, at times that do not exceed 50 ms.

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An increase in the ion dosage of the area I ₁ leads to a decrease in the voltage which is required to obtain a positive charge on the floating electrode. An increase in the ion dose in the area I ₂ leads to a decrease in the voltage that is required to obtain a negative charge on the floating electrode. In all cases, the lateral surface doping of the _{channel formed by the area I 1} must exceed that in the area I ₂ ¹ ^ at least a factor of 5 in order to ensure good reversibility of the element. An exaggerated increase in the doping of the region Ig, which _{entails that of the region I 1} , would lead to elements which are unstable during readout.

5b shows the diffusion of these P ⁺ regions in the interior of the substrate after oxidation of the field regions 43 and 44. The surface zone between the regions 43 and 44 has undergone neither oxidation nor diffusion because the nitride layer 42 acts as a mask or cover during these processes served. The boron * has penetrated further _{from the implantation zone I 2} into this central area, which is protected by the nitride.

5c shows the structure after engraving and N ⁺ doping by implantation of the first silicon gate level, which is deposited from the vapor phase. This step can be accomplished by Phosphorieplantation, with a dosage of 1O ^izf A / cm ² at 80 keV through the 8 χ 10 ~ ² u (800 2) thick layer 45 of SiO ₂ of the electrode or of the gate is advantageous because it enables makes it possible to bring the junction 46 into the region which _{is overdoped by the region I 2} , and also makes it possible to avoid the breakdown effect which is caused by the laterally disturbing NPN structure. The electrode 47, which defines the length of the channel, has a width of 6 u.

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In Fig. 5d the structure after deposition, engraving and doping of the second gate level 48 is shown schematically, which is asymmetrical with respect to the floating electrode. The layer 49 for isolating the two electrodes can be made either by thermal oxidation of the first level or by the deposition of silicon oxide, which is obtained by decomposition from the vapor phase. The second diffusion is covered by the second gate level on the source electrode 46 side and by the first level on the drain electrode 50 side. This diffusion is more heavily doped and deeper than the first according to FIG. 5b. In this way, the voltage retention of the drain electrode is greater than that of the source electrode, because the junction is curved. This increases the asymmetry and promotes the injection of holes on the source side and electrons on the drain side. This diffusion, which is deeper than in the overdoped area I ₂ , enables the parasitic capacitance of the drain and source junctions to be reduced in this part which is reserved for contacting the transistors.

Of course, this is only possible if the channel width is determined by the width of the floating electrode and by the lateral penetration of the first diffusion on the source side and the second diffusion on the Drain side is reduced, is sufficiently large to prevent breakdown of the transistor. A depth of 0.5 microns for the first diffusion and 1.5 microns for the second diffusion gives an arrangement with excellent Function.

The control electrode 48 must be of sufficient width so that it straddles the edge of the floating Electrode 47 can be arranged on the source side. A width of 8 microns allows easy adherence

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the tolerances in this operation. The contact openings in the cutting plane are also shown.

From Fig. 5e it can be seen that then a layer 51 of phosphorus-doped silicon oxide on the entire Surface of the assembly is deposited and then subjected to a flow process.

The contact opening previously formed during the work steps shown in FIG. 5 becomes after the flow process the insulating layer completed. This can prevent excessive widening of the contacts, which is caused by the different composition of the two oxide layers.

The production of the memory cell transistor is achieved by metallization under vacuum and subsequent engraving completed, and thereby electrical contact points for metal strips 52 on the source electrode or 53 on the drain electrode and 54 on the control electrode.

Fig. 5f shows a sectional view of this completed transistor along one perpendicular to the axis of the channel Level. The metallization 54 of the control electrode can be seen there 48, while the floating electrode 49, as its name suggests, is not connected to any terminal and has no connection whatsoever fixed potential is set.

The memory cell transistor according to the invention and its manufacturing method have the advantages inherent in floating electrode arrangements: - a high retention capacity due to the oxide layers on the order of 0.1 µ (1000 R) between the substrate and the floating electrode is guaranteed;

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- Extinguishing process using "hot" load carriers in a manner analogous to that for registered writing, with the retention of also large-scale oxide layers between the floating electrode and the control electrode is enabled;

- punctiform localization of the plasma generating the holes during erasure and improvement of the injection efficiency in reducing "fatigue" caused by traps in the silica;

- Structure with two superimposed electrode levels; the first electrode, namely the floating electrode, becomes used to store the charges, and the second electrode, which is the floating electrode unbalanced covered, is used to control the arrangement in the three functions of reading, writing and deleting;

- Manufacturing process with automatic alignment, whereby the essentials regardless of the positioning technological properties of the memory cell can be achieved;

- A method for the production of components with small dimensions, so of non-volatile memories with high Capacity.

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Claims (9)

Patent attorneys Dipt -Ing Dipl.-Chem. Dipl -Ing. 2 9 2 3 3 β ζ E. Prince - Dr. G. Hauser - G. Leiser Ernsbergerstrasse 19 8 Munich 60 THOMSON-CSF June 8, 1979 173 »Bd. Haussmann 75008 Paris / France Our reference: T 3255 PATENT CLAIMS .). Field effect transistor, which is an electrically writable and forms erasable memory cell, with a source region, a channel region and a drain region, which are diffused into a substrate made of semiconductor material, and with a control electrode or a gate over the channel region and separated from the substrate by a dielectric layer in which Thickness an insulated electrode, called a floating electrode, is embedded thereby characterized in that a locally overdoped area is provided, which automatically after the edge zones of the Channel is aligned and ensures the punctiform localization of the electrical charge carriers, which are injected from the source region and the drain region toward the floating electrode, whereby the threshold voltages of the transistor are changed, 909851/0778 which correspond to the read operations, write operations and erase operations of the memory cell contents. 2. Field effect transistor according to claim 1, characterized in that two electrode levels are provided, wherein the first electrode, namely the floating electrode, is longer and wider than the channel that in the underlying semiconductor substrate separates the source region from the drain region and wherein the second Electrode covers part of the first electrode and part of the source region in an asymmetrical manner and so after the diffusion process, during which the Electrodes fulfill the function of masks, an asymmetry between the source region and the drain region creates. 3. Field effect transistor according to claim 1 or 2, characterized in that the locally overdoped area, which is in contact with the lateral and buried regions of the source region and the drain region, fulfills the function of an insulating wall between transistors on a common semiconductor substrate. 4. Field effect transistor according to one of the preceding claims, characterized in that the write, read and erase operations of the memory cell contents are carried out using voltages of the same polarity as the contents the memory cell by injecting electrons onto the floating electrode and erasing this content is done by injecting holes on the floating electrode, and that the charges of the holes are the electron charges Compensate with the opposite sign. 5. A method for producing the field effect transistor according to claim 1, characterized in that the following 909851/0778 Process steps are provided:. - A layer (41) made of a dielectric such as silicon oxide is formed on a semiconductor substrate such as silicon and a layer (42) formed of a nitride, the latter of which is engraved to act as a mask during the two to serve subsequent ion implantation operations, the first implantation being deep and in the field 'and Side areas of the canal is localized and the second implantation superficial and generally across the whole Surface of the transistor takes place; - Oxidation of the field areas (43, 44) and depth diffusion of those implanted during the previous step Ions; - Deposition of a silicon layer, engraving of the floating electrode (47) in this layer and doping by a third implantation process involving the floating electrode (47) and the source and drain regions (46 or 50) concerns; - Isolation of the floating electrode by surface oxidation or deposition of silicon oxide (49) from the vapor phase, deposition of a second silicon layer, Engraving of the control electrode or the gate (48) in this layer, doping of this electrode and depth diffusion the source and drain regions (46 and 50, respectively) implanted in the previous step; - Engraving to open the electrical contact zones, deposition of a doped passivation oxide (51), the is subjected to a flow process by the action of heat, reopening of the partially closed by the flow process Contact zones and deposition of electrical connections (52, 53 »54) through metallization underneath Vacuum followed by an engraving. 6. The method according to claim 5, characterized in that the write / erase reversibility of the memory cell the fact that the lateral surface 909851/0778 doping of the channel created by the first ion implantation occurred during manufacture, is at least five times stronger than the doping by the second Ion implantation. 7. The method according to claim 5 or 6, characterized in that that the voltage retention of the drain region is stronger than that of the source region and that the asymmetry of the two electrodes creates a depth asymmetry during the Second diffusion caused, causing the injection of holes on the side of the source region and the injection is promoted by electrons on the side of the drain region. 8. Integrated circuit, characterized by a plurality of field effect transistors according to one of the claims 1 to 4 on a semiconductor substrate, which is a matrix of memory cells. 9. Non-volatile, electrically writable and erasable Semiconductor memory, characterized by at least one memory cell made of a field effect transistor according to one of claims 1 to 4. 909851/0779