DE29623891U1 - System for the transparent transmission of an incoming clock signal over a network segment, and the associated transmitting and receiving unit - Google Patents

Description

F:\IJBDHF\DHFANM\O138O45

Applicant:

ALCATEL

54, rue La Boetie

75008 Paris

0138 045 07.03.2000

sch/neg

Title: SYSTEM FOR THE TRANSPARENT TRANSMISSION OF AN INCOMING CLOCK SIGNAL OVER A NETWORK SEGMENT, AND THE ASSOCIATED TRANSMITTING AND RECEIVING UNIT

Description

The present invention relates to a system for transparently transmitting an incoming clock signal over a network segment as defined in the preamble of claim 1, a transmitting unit and a receiving unit equipped to implement this system as defined in the preambles of claims 8 and 10 respectively.

As is well known in the art, such a system is used, for example, in telecommunications networks where a network timing reference signal must be transmitted over the network, but where data is transmitted over a network segment which is based on a

network segment's internal timing reference signal. The network timing reference signal must be transmitted over that network segment, even though it may not be used within it. Within a segment of an ATM (Asynchronous Transfer Mode) network, data may be transmitted, for example, over a telephone line in accordance with the ADSL (Asymmetric Digital Subscriber Line) specifications. The transmission of data packaged in ADSL frames over the telephone line between a sending and a receiving modem is synchronized with the modem clocks. Nevertheless, the network level specifications require that the ATM network's timing reference signal be transmitted transparently over that ADSL network segment. From the point of view of the network segment, the ATM network's timing reference signal is thus an incoming clock signal which must appear unaffected at the output of the ADSL network segment, i.e. at the output of the receiving modem. This could be done by sending the network timing reference signal over a separate transmission medium or over the telephone line, using part of the transmission capacity of that line. In addition, this method of transmitting the network timing reference signal results in a significant increase in the complexity of the transmitter and the receiver.

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An object of the present invention is therefore to realize the transmission of the timing reference signal in an efficient manner, i.e. without the strong increase in the complexity of the transmitter and the receiver in the network segment over which the clock signal is to be transmitted.

According to the invention, this object is achieved by the system defined in claim 1, as well as the transmitting unit and receiving unit defined in claims 8 and 10 respectively.

In fact, since the transmission over the network segment is synchronized to transmit the clock signal, and since both clock signals, the transmit clock signal and the receive clock signal, are synchronized, the receiving unit only needs to know the phase difference between the incoming clock signal and a reference signal synchronous to the transmit clock signal in order to be able to generate a copy of the incoming clock signal, provided that it also has a reference signal equally synchronous to the received clock signal. The reference signal can be obtained by frequency division of the transmit clock signal. Obviously, an equal reference signal obtained by frequency division of the receive clock signal must then be used at the receiving side in combination with the measured

Phase difference value can be used to generate the outgoing clock signal. Determining the phase difference and using it in the receiver and generating a reference signal obviously requires less additional complexity in the transmitter and receiver than is required in these known systems.

In a particular implementation of the present system in which the additional complexity required is even further reduced, the reference signal is equal to the data frame clock signals as defined in claim 2.

In this way, every time a data frame is sent, the phase difference value is determined by measuring the time interval between the incoming clock signal and the data frame boundary. The phase difference value is measured and transmitted once per data frame. If the data frame is sufficiently large (eg an ADSL superframe with a length of 68 x 250 μβ) , the additional overhead of transmitting the phase difference value from the transmitting to the receiving unit can be neglected. As will become clear later, the phase difference in this particular implementation can easily be measured with a counter.

An advantageous feature of this particular implementation is defined in claim 3.

As will be described in more detail later, the implementation just mentioned can in fact be realized with a counter in such a way that the phase difference value is measured as an integer number of transmit clock pulses. Since the transmit clock and the receive clock are synchronous, the phase difference to be realized in the receive unit is also an integer number of receive clock pulses.

Another special feature of the present system is that the phase difference value can be embedded in the fields of the data frames as defined in claim.

In this way, no additional overhead has to be added to the data frames to transmit the phase difference information. This technique is particularly recommended when the network segment transmits data packed in data frames in which some fields are reserved for special purposes.

If the data is transmitted in the network segment according to the Asymmetric Digital Subscriber Line (ADSL) specifications, the phase difference values fields

which are reserved for so-called "fast bytes" as defined in claim 6.

In fact, an ADSL superframe contains several fast byte fields, only a part of which are used to transmit the operating channel information. Consequently, the remaining fast byte fields can be used to transmit the phase difference values.

A further additional feature of the present system is defined by claim 7.

The overhead of the phase difference values is further reduced by transmitting the phase difference values only when they differ from a previously transmitted value. Since the receiver knows this previously transmitted value, it can continue generating the outgoing clock signal without degradation in accuracy if it does not receive any new phase difference values for a certain time.

In an alternative embodiment, not the phase difference itself but the deviation from the previous phase difference is transmitted. Here too, the occupancy overhead can be further reduced by only transmitting the values of the phase difference deviation if

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they differ from a previously transmitted value. This technique is particularly advantageous in the case of a fixed clock offset of the incoming clock signal in relation to the reference signal synchronous to the transmitting clock. In this case, the phase difference deviations are (almost) constant and therefore do not need to be transmitted.

The above and other objects and characteristics of the invention will become clearer and the invention itself will be best understood by referring to the following description of an embodiment and the accompanying drawing, which shows a network segment with a transmitting unit TX and a receiving unit RX performing an implementation of the method according to the present invention.

The network segment shown in the figure consists of a series connection of a transmitter TX, a telephone line TL and a receiver RX. The transmitter TX has 3 input connections, a data input DATA, a network clock input CLK2 and a transmit clock input CLK1. The transmitter TX also has an output connection and is equipped with a data insertion device EMBED and a device for phase measurement PHASE. The receiver RX has an input connected to the telephone line TL, a receive clock input CLK1', a

Data output DATA' and a network clock output CLK2". The receiver RX also contains a data extraction device D-EMBED and a network clock generator GEN.

In the transmitter TX, the data inserter EMBED is connected between the data input DATA and the output connection of the transmitter TX. The network clock input CLK2 serves as an input for the phase measuring device PHASE, and the transmit clock input CLK1 is also connected to an input of the phase measuring device PHASE. An output of the phase measuring device PHASE and an input of the data inserter EMBED are connected to one another. The transmitter TX in the figure also contains an unlabeled star-shaped device that can represent any means by which the transmit clock signal CLK1 is converted into a reference signal R. The reference signal R is thus nothing but a converted clock signal CLK1, is synchronous with this clock signal CLK1 and is connected to the inputs of the data inserter EMBED or the phase measuring device PHASE.

In the receiver RX, the data extraction device is located between the input connected to the telephone line TL and the data output DATA'. A phase output P of the extraction device is connected to a first input of the

Network clock generator GEN, which has a second input which is connected to the receive clock input CLK1' and which has an output which is connected to the network clock output CLK2' of the receiver RX. In the receiver RX, a similar star-shaped, unlabeled device is shown, which represents any means, e.g. a series of frequency dividers, which converts the receive clock signal CLK1' into a reference signal R' in a similar way to the conversion in the transmitter TX. The reference signal R' is applied to the inputs of the data extraction device D-EMBED or the network clock generator GEN.

Two clocks, Cl and Cl", in the figure represent the transmit clock and the receive clock, respectively, which generate the transmit clock signal and the receive clock signal. For obvious reasons, their outputs are connected to the transmit clock input CLKl of the transmitter TX and to the receive clock input CLKl' of the receiver RX, respectively.

In order to demonstrate the function of the illustrated network segment according to the present invention, it is assumed in the following sections that ATM cells are applied to the data input DATA of the transmitter TX, which are to be transmitted via the telephone line TL. These ATM cells are accompanied by a network clock signal which

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is applied to the transmitter TX via the network clock input CLK2. The network clock signal is typically an 8 kHz signal, i.e. a signal having a pulse every 125 μΩ. The transmitter TX and the receiver RX can communicate with each other according to the ADSL specification. In other words, the transmitter is an ADSL modem which groups incoming data DATA into DMT (Discrete Multi Tone) symbols and embeds these DMT symbols in successive frames to form a so-called ADSL superframe FRAME from 68 successive frames. The functional blocks of such an ADSL modem and the structure of DMT symbols, frames and superframes in ADSL are well known to those skilled in the art. Their description is not relevant from the point of view of the present invention. Further details on these issues can be found in the approved version of the ANSI (American National Standards Institute, Ine.) standard for ADSL, designated ANSI Tl.413 and entitled "Network and Customer Installation Interfaces, Asymmetry Digital Subscriber Line (ADSL) Metallic Interface". The embedding of the incoming data DATA into DMT symbols and ADSL superframes is carried out by the inserter EMBED. Each time the reference signal R shows a pulse, the inserter EMBED applies an ADSL superframe to the telephone line TL via its output. The reverse operation is carried out by the extractor

D-EMBED is carried out in the receiver RX, triggered by the second reference signal R', which is obtained from the receive clock signal CLKl' via similar frequency dividers. The reference signal R is obtained from the transmit clock signal CLKl by frequency division. The transmit clock signal CLKl, in this case the ADSL modem clock, has a frequency of 2.208 MHz.

The ATM network layer specifications require that the ATM network clock signal CLK2 of 8 kHz be transmitted over the entire network. The ADSL network segment, consisting of the transmitter TX, the telephone line TL and the receiver RX, must thus transmit the ATM network clock signal from the transmitter TX to the receiver RX. For the ATM network, the ADSL network segment is a black box, which means that it is not important how the network clock signal is transmitted between TX and RX. The next section describes in detail how the information required to enable the receiver RX to recover the ATM network clock signal is determined in the transmitter TX. A following section explains how this information can be embedded in the ADSL superframes to be transmitted to the receiver, and a third section is devoted to the processing in the receiver RX to generate the network clock signal from the receiver information.

Since the frequency of the ATM network clock signal is well known (8 kHz), no information about it needs to be transmitted between TX and RX. Dividing the modem clock signals (the transmit clock signal CLK1 in TX and the receive clock signal CLK1' in RX) of 2.208 MHz by 276 results in a new signal with a frequency of 8 kHz, i.e. the ATM network clock frequency. The receiver RX therefore only needs to receive phase information about the incoming ATM clock signal CLK2 in order to be able to generate a perfect copy of it at its network clock output CLK2'. The phase measuring device PHASE determines the phase difference between the incoming ATM network clock signal CLK2 and the reference signal R, which is used to trigger the transmission of the ADSL superframes. In the phase measuring means PHASE, the value of a counter is reset to zero when the reference signal R has a pulse. At this moment, the inserter EMBED sends an ADSL superframe. The value of the counter is increased by one each time the transmit clock signal CLK1 shows a pulse, and the count value P is applied to the inserter EMBED via the output of the phase measuring means PHASE when the ATM network clock CLK2 shows a pulse. In summary, the phase measuring device PHASE counts the number of transmit clock pulses between the boundary of an ADSL superframe and a network clock pulse. This

Number is a measure of the phase difference P between CLK2 and R and is transmitted to the receiver RX.

The EMBED insertion device has the task of including the phase difference P in the ADSL superframe. This superframe has a length of 68 DMT symbols, i.e. in time 68 x 250 /zs. Each DMT symbol contains a field for so-called "fast bytes". This field can be used for special purposes, such as the transmission of operating channel information, STM synchronization

Information, In the already quoted

The ADSL standard specification specifies how the fast byte fields of the first two DMT symbols in an ADSL superframe must be used. The content of the other fast bytes, i.e. that of DMT symbols 3 to 68, is not defined in the specification. Therefore, one of these bytes can be used to transmit the phase difference P from the transmitter TX to the receiver RX. Since a DMT symbol has a length of 250 ßs and the phase measuring means PHASE at CLK2 receives a pulse every 125 με , the value P is reliably determined at the end of the first DMT symbol of an ADSL superframe. As a result, it is no problem for the inserter EMBED to fill one of the fast bytes in DMT symbols 3 to 68 with the value P.

It should be noted that an intelligent inserter first checks whether the measured phase difference P differs from a previously measured value or not. To minimize the bandwidth usage for transmitting phase difference values, the intelligent inserter writes the value of P into the fast byte field only if there is a difference.

On the receiver side, the extraction device extracts the value P from the fast byte field each time an ADSL superframe arrives, i.e. for each pulse of the reference signal R'. The phase difference value P is then applied to the generator GEN, which forms the outgoing network clock signal CLK2'. An 8 kHz clock signal is generated from the receive clock signal CLK1' with a frequency of 2.208 MHz, again by frequency division by 276. This 8 kHz clock signal must have a phase difference of P receive clock pulses from the reference signal R' in order to be a perfect copy of the incoming ATM network clock signal CLK1. The generator GEN thus manipulates the 8 kHz signal obtained by frequency division of CLKl', e.g. by delaying the pulses so that the first pulse appears P clock periods of the receive clock Cl' after the reference signal R' has shown a pulse.

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It is noted that the above embodiment is described in terms of functional blocks. As is clear from the description of their function, the functional blocks do not contain any unknown components. Consequently, given the above description of the functions performed by these blocks, it is obvious to a person skilled in the art of electronic circuit design how to implement the various EMBED, PHASE, D-EMBED and GEN blocks.

It must be further noted that embedding the phase difference value P in the fast byte locations is not a necessity when the clock transmission method according to the present invention is used. Many alternative solutions, for example the use of sync byte fields in ADSL superframes for transmitting the phase difference values, can be considered without inventive effort.

It should also be noted that the present invention is not limited to systems in which the phase difference value P is transmitted embedded in frames, since it is obvious to any person skilled in the art that the measured phase difference value can also be transmitted separately from the frames, e.g. in time division multiplex or frequency division multiplex with the frames in order to introduce the receiver to the

To be able to reconstruct the network clock signal CLK2.

Another note is that the phase measurement does not necessarily have to be performed every time a frame is transmitted from the transmitter to the receiver. The frequency of the phase measurements can be chosen completely freely. It is obvious that there is a compromise between the precision of the outgoing network clock and the amount of bandwidth resources used on the connection. The more frequently phase measurements are performed in the transmitter, the more bandwidth is required on the connection between transmitter and receiver to transmit the phase information, but the more accurate a copy of the incoming network clock CLK2 can be generated in the receiver.

Another parameter that can affect the precision of the generated outgoing network clock is the technique used to measure the phase. In this regard, it must be noted that an implementation using a counter that determines the phase difference P as a number of transmit clock periods is only one of the many different techniques for measuring the phase difference.

Furthermore, it must be pointed out that although the network segment described above is an ADSL segment receiving ATM cells and an accompanying 8 kHz ATM clock signal at its data input, the present invention is not limited thereto. It will be clear to a person skilled in the art that by minimal modifications of the method described above it is possible to implement it in other networks, e.g. in SDH (Synchronous Digital Hierarchy) networks where data and network clock must be transmitted over non-ADSL network segments, e.g. over VDSL (Very High Speed Digital Subscriber Line) segments, HFC (Hybrid Fiber Coax) segments, and so on.

A final remark is that although the data symbols in the network segment described above are transmitted over a telephone line TL, the applicability of the present invention is not limited by the transmission medium over which the data is transmitted. In particular, the present invention can be implemented on any connection between two communicating entities, TX and RX, e.g. on a cable connection, a fiber optic connection, a satellite connection, a radio connection over the air and so on.

Although the principles of the invention have been described above in connection with a specific apparatus, it is to be clearly understood that this description is given as an example only and not as a limitation on the scope of the invention.

Claims (10)

1. A system for transparently transmitting an incoming clock signal (CLK2) having a well-known frequency over a network segment, comprising a transmitting unit (TX) to which an input can be applied with said incoming clock signal (CLK2) and a clock input can be applied with a transmitting clock signal (CLK1) from a transmitting clock (C1), a transmission medium (TL) and a receiving unit (RX) to which a receiving clock signal (CLK1') from a receiving clock (C1') synchronized with said transmitting clock (C1) can be applied, characterized by : a) means for measuring a phase difference value (P) between said incoming clock signal (CLK2) and a reference signal (R) obtained from said transmitting clock signal (CLK1); b) means for transmitting said phase difference value (P) from said transmitting unit (TX) to said receiving unit (RX); and c) means for generating in said receiving unit (RX) an outgoing clock signal (CLK2') having a frequency equal to said well-known frequency, said outgoing clock signal (CLK2') having a phase difference to a second reference signal (R') which is obtained from said receiving clock signal (CLK1') in the same way as said reference signal (R) is obtained from said transmitting clock signal (CLK1), and which is equal to said phase difference value (P). 2. System according to claim 1, characterized in that said transmitting unit (TX) transmits data frames (FRAME) via said transmission medium (TL) to said receiving unit (RX), the transmission of each of said data frames (FRAME) being triggered by said reference signal (R). 3. System according to claim 2, characterized in that said phase difference value (P) can be measured with a precision equal to a period of said transmit clock signal (CLK1), or alternatively of an up- or down-sampled transmit clock signal. 4. System according to claim 2, characterized in that said measured phase difference value (P) can be embedded in said data frame (FRAME) to be transmitted to said receiving unit (RX) by means b). 5. System according to claim 2, characterized in that said transmitting unit (TX) and said receiving unit (RX) are of the type Asymmetric Digital Subscriber Line (ADSL) transmitter and receiver, respectively, said data frames (FRAME) are Asymmetric Digital Subscriber Line superframes as defined in ANSI Standard T1.413, said incoming clock signal (CLK2) is a network timing reference signal, and said transmitting clock signal (CLK1) and receiving clock signal (CLKJY) are Asymmetric Digital Subscriber Line modulator and demodulator timing references, respectively. 6. System according to claim 4 and claim 5, characterized in that said phase difference value (P) can be embedded in fast byte fields of discrete multi-tone (DMT) symbols of said asymmetric digital subscriber line superframe. 7. System according to claim 1, characterized in that said phase difference value (P) can only be transmitted if it differs from the previously measured and transmitted phase difference value. 8. Transmitting unit (TX), to whose first input data (DATA) can be applied and to whose second input an incoming clock signal (CLK2) can be applied, said transmitting unit comprising: a) insertion means (EMBED) located between said first input (DATA) and an output of said transmitting unit (TX) and adapted to embed said data (DATA) in data frames (FRAME) and to apply a data frame (FRAME) to said output of said transmitting unit (TX) when triggered by a reference signal (R) which can be derived from a transmitting clock signal (CLK1) which can be applied to a clock input of said transmitting unit (TX) from a transmitting clock (C1), characterized in that said transmitting unit (TX) further comprises: b) phase measuring means (PHASE) to which said incoming clock signal (CLK2) and said reference signal (R) can be applied to a first and a second input, respectively, and which is adapted to measure a phase difference value (P) between said incoming clock signal (CLK2) and said reference signal (R) and to apply said phase difference value (P) to an output of said phase measuring means (PHASE);
and further that: c) said insertion means (EMBED) is provided with an additional input terminal connected to said output of said phase measuring means (PHASE), said insertion means being further adapted to embed said phase difference value (P) in said data frame (FRAME). 9. A transmitting unit (TX) according to claim 8, characterized in that said phase measuring means (PHASE) includes a counter adapted such that its count value is increased upon activation of a first counter input by said transmit clock signal (CLK1), that its count value is reset upon activation of a second counter input by said reference signal (R), and that said count value is read out and said count value is applied to said output of said phase measuring means (PHASE) when a third counter input is activated by said incoming clock signal (CLK2), said count value representing said phase difference value (P) when applied to said output of said phase measuring means (PHASE). 10. Receiving unit (RX) to which data frames (FRAME) can be applied to an input, comprising said receiving unit (RX). a) extraction means (D-EMBED) having an input connected to said input of said receiving unit (RX), said extraction means (D-EMBED) being adapted to recover data (DATA') and apply it to a first output of said receiving unit (RX), and to recover a phase difference value (P) from a reserved field of said data frame (FRAME) and apply said phase difference value (P) to a phase output of said extraction means (D-EMBED), characterized in that said receiving unit (RX) further comprises: b) generator means (GEN) having a first input connected to said phase output having said phase difference value (P) applied thereto and a second input having a second reference signal (R') obtainable from a receive clock signal (CLK1') applied to a clock input of said receive unit (RX) from a receiver clock (C1'), said generator means (GEN) being adapted to generate an outgoing clock signal (CLK2') equal to said well-known frequency and having a phase difference with respect to said second reference signal (R') equal to said phase difference value (P).