DE2952326A1 - TERMINAL DEVICE SYSTEM - Google Patents

Description

DIPL. ING. HEINZ BARDEHLE PATENT ADVOCATE File number:

Minchen, 24. Οβ2. 1979

My reference: ρ 2987

Honeywell Information Systems Inc.

200 Smith Street

Waltham, Mass, V.St. ν. Α.

End device system

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description

The invention relates generally to terminal systems, also referred to as terminal systems, for data processing systems and in particular to cathode ray tube display devices.

A cathode ray tube display system consists of a number of sub-systems, including a central data processing sub-system, all of the sub-systems being connected to a common bus line. If a subsystem wants to be taken into account by the central data processing system, the subsystem concerned sends an interrupt signal to the central unit via the bus line . In the system previously used, the central processing unit subsystem queries the subsystems to determine which subsystem has sent an interrupt signal. The central processing unit subsystem will then process the relevant interrupt and generate the relevant interrupt vector address on the bus line. This process entails the requirement for the data processing system or the central unit to use hardware and firmware in order to query or retrieve all devices in the subsystem, in order to also give priority to those devices which have active interruptions, and in order to obtain the clear firmware Generate the address with which the firmware interrupt handler is entered.

There are several other known types of interrupt processing systems, which are coupled so that an interrupt service occurs in response to the occurrence of an interrupt signal which from any

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which is picked up in a number of existing sources, such as peripheral devices associated with a Input / output bus line are connected. Typically, the handling of the procedure requires Servicing the interruptions of such peripheral luinrichtungen the identification of the interrupting peripheral devices, then the request for the status of the peripheral device concerned and finally the update of the status. This procedure is relatively slow, and in certain types of systems where interrupt routines are carried out frequently, the acknowledgment or feedback routine duration bring serious speed restrictions of the overall system with it. at one such interrupt system as disclosed in US Pat. No. 3,881,174 comprises the interrupt processing arrangement a computer that a peripheral device au.? the recording of an acknowledgment signal from the computer on an interrupt request that the peripheral device has previously generated, /, at the same time as the Computer to supply the address and the status of the device concerned, whereby the time span is shortened, which is required for the interrupt routine.

In US-PS 40 ~} 0 075 a data processing system is described which has a priority network with distributed priority. This priority network is coupled to each of the units in order to indicate the relevant unit which, as the I unit with the highest priority, requests the transmission of information via the bus line. The priority network comprises a priority bus line to which the units are coupled, the unit connected closest to one end of the bus line having the highest priority and the units connected to the other end of the bus line having a lower priority. All

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However, the above systems have the disadvantage that they require a considerable amount of hardware and are time-consuming Cycles are needed to connect to the bus line.

In the display system "Honeywell 7760" is a central processing unit subsystem provided which controls a fixed number of peripheral subsystems. A peripheral sub-system is in data exchange with the sub-system of the central unit in order to make a request with respect to an interrupt signal to be sent to the subsystem of the relevant central unit. The throughput however, the display system is enhanced by having higher speed microprocessors be included in the system. This enables the development of system applications that are more peripheral Require subsystems than exist in the previously known display systems.

The cathode ray tube displays were originally designed to have a keyboard and a Exhibited image display device. New applications require additional facilities to be added to the system are. Communication subsystems, printers and Floppy disks were included in the system.

These devices were connected to a linking unit in a radial manner. The linking unit selected facilities on a given priority basis.

The continued expansion of application requirements has resulted in many more facilities adding to the System were added. The use of the microprocessor increases the throughput of such systems

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to make executable. The Interrupt Procedure Techniques on the Display System were "Honeywell 7760" but unable to achieve the desired throughput deliver. If such a system was designed to be connected to a large number of facilities too then were systems with a few facilities with a significant separate superordinate Provide link arrangement that was not required for the system.

In an article (see the magazine "Computer Design", January 1978, pages 117 to 124 - by Joseph Nissam) the prior art is summarized, which relates to the Bus line cycle time control refers, with various DMA (direct memory access) transfer methods described including the Halt method, the Multiplexer DMA / CPU method and the "cycle stealing" method. With the Halt method, the central processing unit CPU is switched off, while the so-called DMA transfer takes place, i.e. the transfer by the direct memory access device. The disadvantage here is the relatively long period of time that is required to turn on the central unit the bus line to or. to switch off from this. With the multiplex DMA / CPU method, each memory cycle is in divided into two time slot slots or time slots, one of which is used for the central processing unit CPU and the other of which is used for the direct memory access device DMA is used. These However, method requires high-speed memory to achieve high performance. The "cycle stealing" method is the best method for the applications considered in the above article. These However, the method has the disadvantage that it slows down the operation of the central processing unit CPU when the direct memory access devices DMA to access the memory.

The invention is accordingly based on the object

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To create improved terminal equipment system for data processing systems.

The object indicated above is achieved by the invention covered in the patent claims.

According to the invention, a data terminal system is created, which comprises a bus system to which a memory subsystem is operatively connected and to which a central processing subsystem is connected, which operates with the relevant memory subsystem is connected in order to be able to transmit address signals via the system bus line which characterize are for a storage location of the storage system concerned. Furthermore, a first plurality is peripheral Subsystems connected to the system bus line, the central processor subsystem and the memory subsystem. These first plurality of peripheral subsystems generate a plurality of interrupt request signals, when access to the storage subsystem is required. The central processing subsystem speaks responds to the plurality of interrupt request signals to modify the address signals, the modified address signals are indicative of a first start address memory location to an interrupt routine by which a selected one of the first plurality of peripheral subsystems operatively linked to the central processing subsystem.

The invention also includes a terminal system a system bus is created to which a memory subsystem is connected, which service routines in saves a read-only memory. A central processor

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The subsystem is also connected to the system bus line. This subsystem contains a microprocessor for generating a plurality of specific address signals in response to the occurrence of a microprocessor interrupt request signal there. Further, a plurality of peripheral device subsystems are connected to the system bus line which is an external request interrupt signal line has, which in common with each of the existing in a plurality peripheral device subsystems and with the central processor subsystem connected is. The system bus line also contains an external acknowledgment interrupt signal line, which are in series with each of the existing in a variety of peripheral devices and is connected to the central processing subsystem. There is one of the many peripheral ones available Equipment subsystem a '.. n first signal level the external request interrupt signal line. The one in question is a ^ subsystem of in a multitude existing peripheral driver sub-systems gives on the Occurrence of the first signal level on the external handshake interrupt signal line towards a plurality of address signals via the system bus line in order to modify the particular address signals concerned. These modified address signals are sent to the memory in order to have a first memory location to read out in the relevant memory in which a first word of the operating routine is stored. This The first word and the following words of the relevant operating routine are sent to the central unit, in order to activate the one subsystem in question of the plurality of peripheral subsystems.

The invention also creates a terminal system, which works with a shared bus line timing cycle. This system comprises a system

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bus line, which has a control bus line for transmitting control information, an address bus line for has the transmission of address information and a data bus line for the transmission of data information. The address bus line and the data bus line are subject to such timing control, that control signals are provided, the central processing unit (CPU) cycles and direct memory access (DMA) cycles produce. There is also a memory subsystem with system management during CPU cycles and the DMA cycles effectively connected. A central processing unit subsystem connected to the system bus is with effectively connected to the memory subsystem during CPU cycles to provide data between the central processor subsystem and to be able to transmit to the storage sub-system at an address storage location in the relevant Memory subsystem referred to by the central processor subsystem. Furthermore, a variety of peripheral subsystems connected to the system bus with the memory subsystem during the DMA cycles effectively connected to data provided between a subsystem of a plurality of peripheral Subsystems and the memory subsystem to transfer, including an address storage space in the memory subsystem identified by the relevant one of a plurality of peripheral Subsystems is designated. Finally, a timing device is provided which has a split bus line timing cycle generated and which is connected to the control bus. This timing controller generates control signals including an address bus line timing signal and a data bus line timing signal. These timing signals are the Central processor subsystem fed to the CPU cycle for the address bus line and for the data bus line to create. The timing signals concerned also become the plurality of peripheral subsystems

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to generate the DMA cycle for the address bus line and for the data bus line. The concerned Data bus line timing signals are one step in time from the address bus line timing signal offset certain amount.

In accordance with a preferred embodiment of the invention, a cathode ray tube display system includes a central processing subsystem with a microprocessor, a read-only memory (ROM) and a large number of optional or additional peripheral devices. An additional peripheral device receives access or access to the system by a specific Address initiated by the microprocessor is modified. The particular modified in question Address denotes that memory location in the read-only memory which contains the service routine which is an additional set-up operation in the system executes.

The priority of the device is determined by its location in an auxiliary device feedback interrupt signal chain set. One that responds directly to the feedback or acknowledgment signal from the central processor subsystem Facility subsystem has the highest priority. The next facility subsystem, which is responsive to the acknowledge signal from the device subsystems with the highest priority the next highest priority. The facility subsystem at the end of the handshake chain has the low first priority.

With reference to the preferred embodiment of the invention, each accessory facility subsystem is included connected to a common additional signal line capable of carrying an external request interrupt signal. An accessory subsystem requests one

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Interrupt by setting an interrupt request flip-flop. This flip-flop in turn sets a synchronization flip-flop if there is no additional external acknowledgment interrupt signal. The synchronization signal activates the additional external request interrupt signal line. If the external request signal line is assigned to the central processing subsystem, then this results in the microprocessor generating a first dedicated address. The link means responsive to that particular address, generates the additional setup Qulttungs interrupt signal, which in turn is delivered to each additional device, external to the additional request interrupt signal line is connected, wherein the respective signal first to the Zusätzeinrichtungs subsystem with the highest priority is fed. The highest priority accessory receiving the accessory handshake signal responds with its address signal which modifies the first particular address and which also prevents lower priority accessory subsystems from responding to the accessory handshake signal.

During the next CPU cycle, the microprocessor generates a second dedicated address. These address signals are sent to the device that sent a response to an arbitration flip-flop to set which the interrupt request flip-flop resets and resets the synchronization flip-flop at the end of this second CPU cycle.

During both CPU cycles, the ancillary equipment subsystem is its identification address signals to the bus line, whereby the first and second determined Address can be modified in such a way that a

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unique read only memory address is generated which is indicative of its interrupt service routine.

The central processing subsystem and a plurality of peripheral subsystems are common on a system bus line connected. The arrangement in the central processing subsystem accepts interrupt signals the other sub-systems and selects an interrupt sub-system on a certain priority basis by generating an address and sending it to the system bus line, this address being the peripheral Designates the device whose interruption has been recorded or accepted. In the preferred embodiment this address is used to create a firmware routine (which is not part of the invention) in a To identify read-only memory ROM in order to process the interruption in question.

The interrupt signal from one subsystem is fed to an encoder, as are the other interrupt signals from the other subsystems. The encoder gives sends an interrupt request signal to the central processing unit CPU and generates a 3-bit address code. The central unit generates a specific address which, in the preferred embodiment, is given in hexadecimal form FFF8 is. This address is sent out by the relevant central unit via the system bus line. The address will recorded by the interruption arrangement, which generates an IRQACK acknowledgment signal, which is used to enable, of a decoder. When the interruption signal is received by means of a keyboard, cathode ray tube display device or generated by the communications subsystem, which is the output signal of the relevant decoder is set, then the three address bits mentioned above are transmitted via the Address bus line sent out in hexadecimal form FFFX, i.e. as an even address.

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If the interrupt signal is received by an external communication option or by a peripheral accessory has been generated, then an acknowledge signal is sent from the requesting interrupt Additional device added. The additional device in question sends the low-order bits via the address bus line, on which you can use the higher-order address bits in the hexadecimal form FF can be combined to produce the hexadecimal address FFXX, an even address.

On the next CPU cycle, the central unit generates the hexadecimal address FFF9. In this case generated the subsystem addresses the address FFFY or FFYY, which is an odd address, i.e. the one incremented by one above address.

In a CRT display system, there are many Memory cycles required to refresh the display. With a 24 lines and 30 characters per line Refresh rate at 60 Hz is a Minimum of 115, 200 bus cycles required. When displaying higher density and when displaying additional Signs of visible additions, this refresh rate can be much higher. Other peripheral Devices operating in a DMA mode, such as disk storage controllers, also bring Requirements with regard to the system bus line data rate. The arrangement divides the system bus line timing into alternating CPU cycles and direct memory access (DMA) cycles. With the preferred In the embodiment, the duration of each CPU cycle and each DMA cycle is typically 508.5 ns. the DMA cycles are used by the peripheral subsystems for data transfer with the memory.

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The system bus line timing is further in Address phase and a data phase split. These two phases are offset from each other by a period of time, which is typically 305 ns. This means that the address phase is in alternating CPU and DMA cycles is divided, which are typically 508.5 ns each, with the data phase in alternating CPU and DMA cycles that lag the address phase by the above-mentioned 305 ns. One on a frequency 19.66 MHz oscillator provides the basic time for the system bus line linking device, by controlling a number of shift registers which are connected in series and which provide the timing pulses or deliver clock pulses which a number of timing flip-flops in a fixed order set and reset. A CPUADR flip-flop defines the CPU address phase in the set state, and in the reset state, the relevant flip-flop defines the DMA address phase.e of the system lead cycle. The CPUDAT flip-flop defines the CPU data phase when it is set, and when it is reset it defines it relevant flip-flop the DMA data phase of the system bus line cycle fixed.

Other timing flip-flops set a number of further signals on the system bus line; these flip-flops are described in detail below will.

The invention is explained in more detail below, for example, with the aid of drawings.

Fig. 1 shows the timing of the system bus line cycle in the preferred embodiment of the invention.

Fig. 2 shows, in an overall block diagram, the system according to the invention.

3 illustrates in a block diagram the address bus and data bus signal lines of the

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system concerned.

4 shows a timing and control unit in a logic diagram.

Fig. 5 shows in a time diagram the course of system bus line signals η.

Fig. 6 shows in a logic diagram a central processing unit s interrupt system.

7 shows an additional interruption system in a logic diagram.

Fig. Θ shows signals of the additional interruption system in a timing diagram .

In the preferred embodiment of the invention is the system bus timing as illustrated in FIG. 1 into an address phase 1 and a Data phase 3 subdivided, the data phase 3 lagging the address phase 1 by a period of time which is in is typically 305 nanoseconds. The two DMA and CPU cycles are typically 508.5 ns long. Consecutive CPU cycles are around 1.017 / US separated from each other.

A central processor 4 as shown in Fig. 2 operates during the CPU cycles. Peripheral subsystems 14a to 14f are effective by prior definition during the DMA cycles. A cathode ray tube subsystem 12 is through prior definition only effective during DMA-1 cycles as the cathode ray tube display is a continuous update from the storage subsystem 10 required.

FIG. 2 illustrates the overall system which comprises a timing and control subsystem 2, the Central processing unit (CPU) subsystem 4, a keyboard and switch subsystem 8, the memory subsystem 10, the Cathode ray tube control and direct memory access (DMA) connector 12, an external one

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Communication option 25 and a number of peripheral accessories, which are typically the accessories to I4f, which is operated on a bidirectional Data bus line 16, to an address bus line 18 and are connected to a control bus line 20.

The timing and control system 2 generates the cycle timing control signals for the address bus line 18 and for the data bus line 16, as shown in FIG. 1, specifically for the address phase 1 and the Data phase 3. In addition, the relevant signals for the control bus line 20 are generated.

The memory subsystem 10 includes RAM memory random access that has 8192 word storage locations. The subsystem 10 also includes a ROM read-only memory with 20A80 word storage locations. The ROM memory stores microprogram subroutines that control the overall system control operation. The memory areas of the RAM memory are made up of or in registers, buffers and word memory areas set. The memory subsystem 10 is during the CPU cycles and the DMA bus line cycles in operation. The contents of the memory address memory locations identified by the signals BUSAOO-15 + 00 are received over the address bus line 18 and a data word CPUDO-7 + 00 sent out via the data bus line 16. During a memory write cycle, the data word CPUDO-7 + 00 added via data bus line 16.

The signal lines BUSAOO-15 denote each of the 16 address lines the address bus line 18. With BUSAOO-15 + indicates that a signal line carries a binary signal 1 if the signal is on the line in question carries a high signal level. With BUSA00-15 + 0Ö is

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determined that the address signals BUSAOO-15 + on the OO bus line are available.

The CPU subsystem 4 operates on the data bus line 16 and the address bus line 18 during the CPU cycle time together to receive signals from the memory subsystem or a peripheral device 14a to I4f to read out or to write signals into these devices. The CPU subsystem 4 controls the overall system operation by means of the microprogram subroutines contained in the ROM memory subsystem 10 are stored. The CPU subsystem 4 takes micro words over signal lines CPUDO-7 + 00 on the data bus line 16 on the occurrence of the address signal BUSAOO-15 + 00, which via the address bus line 18 is sent out from the CPU subsystem 4. The CPU subsystem 4 can also include areas of the memory subsystem 10 read out or update, namely at the memory location indicated by the signal BUSAOO-15 + 00 which has been sent out from the CPU subsystem 4 over the address bus line 18.

The microprogram subroutines do not form part of the invention. They are therefore only described to the extent that than is necessary for an understanding of the operation of the overall system.

The keyboard and switch subsystem 8 provides information in the form of data words or control codes the data bus line 16 from during the CPU cycle time. This information was as a result of manual operation the keyboard or as a result of manual operation of the switches or as a result of the delivery of Check Routines of the CPU Subsystem 4. The relevant Information is processed by the microprogram control of the CPU subsystem 4.

The communication subsystem 6 operates during the CPU cycle time. It works in synchronous or

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Asynchronous operation and can transmit or receive information. Main or host systems can communicate with the communication sub systems 6 be connected. Therefore, all of the information arrives on the data bus line 16 during the CPU cycle time through the communication subsystem 6 under microprogram control in the case that the information is to be transmitted to the relevant main system.

The cathode ray tube memory device and direct memory access (DMA) interconnect device 12 operate during the DMA-1 cycles of FIG The control information and the data characters for the display are sent from the memory 10 via the data bus line 16 to the cathode ray tube controller and DMA connector 12 with respect to each displayed line. A number of additional devices, such as buffered _printers, floppy disks, an extended memory or HDLC communication devices, are connected to the system in the form of the additional devices I4a-I4f. These adjuncts are operated to communicate with memory subsystem 10 during the DMA 2-4 cycle time. Each additional device I4a-I4f is internally wired for a certain cycle time DM2, DM3 or DM4.

Certain signals BUSAOO-15 + 00 address areas in the Storage Subsystem 10 RAM memory. These areas are provided as registers. The addresses concerned are decoded as line signals and via the address bus line 18 issued to the individual subsystems to indicate to the respective subsystem that access to a specific register in the memory 10 takes place. These signals are not essential for understanding the invention, although they are described in detail where necessary to understand their operation.

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The timing and control subsystem generates and receives control signals over a control bus line 20. These signals are further described below.

CPUADR-OO CPU Address Control This signal defines the DMA and CPU bus cycle timing of the address bus line. When the signal of the low level occurs, the CPU address lines are connected to the address bus line, and when it occurs of the high level, the DMA address lines are linked to the address bus line 8.

CPUDAT-OO CPU data control This signal defines the DMA and CPU bus cycle time controls. When the low level signal concerned occurs, the central processing unit CPU controls the direction and purpose of the data bus line 18. When the high level signal concerned occurs, the DMA devices control the data bus line 18.

BUSRWC-fOQ bus line read / write control This signal defines the type of data transfer on the data bus line 16. It is available or effective during the CPUADR period for the relevant phase of the bus line cycle. During the CPU phase, the relevant signal indicates, as logic signal 1, that data are to be read out from a device, such as from the communication subsystem 6 or the memory subsystem 10, and passed on to the CPU subsystem 4 via the data bus line. The signal indicates, as logic signal 0, that data are to be written from the CPU subsystem 4 to the device or the memory subsystem via the data bus line. This shows during the DMA phase

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Signal as logic signal 1 to read that data from the memory subsystem 10 and to the Additional DMA device 14a to I4f via the data bus line 16 are to be sent. As logic signal 0, the signal indicates that data is being sent to the memory subsystem 10 are to be sent out via the data bus line 16 from the DMA device 14a to I4f.

MEMSTR-OQ Memory Sampling This signal provides the internal timing pulses for the memory subsystems during the CPU and DMA bus line cycles.

DEVSTR-OO Setup start. This signal is used as a clock pulse by the additional devices 14a to I4f.

BUSQ10-00 Bus line scanning 1 This signal is used by the additional devices 14a to I4f as a clock pulse.

BUSO30 + bus line scanning 3

This signal enables the signal output of the memory subsystem 10 during a read operation, if a link signal 1 during the CPU and DMA bus line cycles exist. The signal is also for the auxiliary devices 14a to I4f for the time control available.

BUSQ30 bus line scanning 3

This signal activates as logic signal 0 the cathode ray tube controller and DMA connector during DMA bus cycle cycles 12 during the write operation.

DMAREQ DMA request

There are four DMA request signal lines. The signal line DMAREQ + 01 is the cathode ray tube controller and allocated to the DMA connector. The signal lines DMAREQ-02, DMAREQ-03

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and DMAREQ-04 are available for special additional devices 14a to I4f. As illustrated in Fig. 1, there are four DMA bus cycle time slots DMA1, DMA2, DMA3 and DMA4. A subsystem requests its assigned DMA bus cycle by having it its DMAREQ signal emits 0 as logic signal.

DMAKXO- DMA acknowledgment

Four DMA acknowledgment signals DMAK10-, DMAK20-, DMAK30- and DMAK40- define their respective time slots on the control bus line by inserting a Output link signal zero.

EXTIRQ-OO External interrupt request This signal indicates as logic signal 0 that an additional device 14a to I4f is an interrupt device which requests operation of the CPU subsystem 4.

PRIACK-05 External Interrupt Acknowledgment This signal acknowledges the external interrupt request as link signal 0.

BRESET-OO Bus Line Reset This signal is used by the CPU subsystem 4 to clear registers and reset flip-flops in the system. The relevant signal is effective as logic signal 0.

BUSREF + OO bus line refresh

management

As logic signal 1, this signal triggers a memory refresh cycle. It's for a DMA1 cycle active every 16 microseconds.

Referring to Figure 3, there is shown a detailed block diagram of the system. The relevant block diagram is in the Figures 3a to 3e illustrate. The subsystems according to

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Fig. 2 are shown separately in Fig. 3a to 3e. First of all, reference is made to FIG. 3a. The timing and control subsystem 2 includes an oscillator 2-4 and timing and control logic 2-2. The oscillator outputs a square wave signal to the timing and control logic 2-2 , which in the preferred embodiment occurs at 19.66 MHz. The timing and control logic 2-2 emits the logic signals which are used for signal timing of the address bus line 3, the data bus line 16 and the control bus line 20.

The timing and control logic 2-2 generates two timing signals CPUPH1 and CPUPH2, which determine the timing Effect control of a microprocessor (CPU) 4-2. The microprocessor 4-2 constituting a central processing unit is a microprocessor named MC68A00 from Motorola, as described in specification DS9471 from 1978 Motorola Semiconductors, 3501 Ed Bluestein Blvd., Austin, Texas, 78721.

The DPU subsystem 4 comprises the microprocessor 4-2 which generates the address signals CPUAOO-15 + 00 and which the Generates and receives data signals CPUD0-7 + 0A. The address signals CPUA1-4 + 00 are fed to a driver 4-4, enabled by an output signal of a NAND gate 4-12 will. The address signals CPUA5-8 + 00 are fed to a driver 4-6, which by an output signal of a AND gate 4-14 is released. The address signals CPUAOO, 9-15 + 00 are fed to the input of a driver 4-10, which is enabled by a signal CPUADR + appearing on the control bus line 20, which is shown in the timing and control logic 2-2 is generated. The address signals CPUAO-15 + 00 become the input side the interrupt and priority logic 4-14, provided the address of the central processing unit 4-2 is in hexadecimal form FFF8 or FFF9 is present. These address locations are modified in an interrupt device 4-24,

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to denote the subsystem which is an interrupt of the CPU subsystem requests which one Request interruption of CPU subsystem 4. The address signals CPUAOO-15 + 00 become, if they are in the Hexadecimal form denoting the storage locations EOXX, fed to the decoder 4-8. The address EOXX denotes a Registers in the memory subsystem 10.

The logic signal CPUADR + is fed to the AND gates 4-12 and 4-14. The link signal IRQACK-, which Another input of the AND gate 4-12 is fed, occurs with a low level when the central unit 4-2 responds to an interruption and sends the address FFF8 or FFF9 to the interruption and priority logic 4-24. This suppresses the output of the Driver 4-4 the signals BUSA1-4 + 0B and outputs the signals BUSA1-4 + 0C from the interrupt unit 4-24 to the address bus line 18 free. The logic signal PRIAK-05, which is a further input of the AND element 4-14 occurs during a low-level external device interruption, i. when the signal EXTIRQ-OO occurs on the control bus line with a low level. As a result, the output On the side of the drivers 4-4 and 4-6, the output of the signals BUSA1-8 + 0B to the address bus line 18 is suppressed. The " External additional device 14a to I4f according to FIG. 3c receives the signals BUSA1-8 + 00 from the address bus line on the input side 18 supplied. The output signal of the driver 4-10, namely the signals BUSAOO, 9-15 + OB, occurs the address bus line 18 when the logic signal CPUADR + occurs with a high level. The signal CPUADR + controls the timing of the address output signals of the central processing unit 4-2 on the address bus line 18th

The data signals CPUD0-7 + 0A occur between the central processing unit 4-2 and the connection point 16-1 on the data

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bus line 16, which is connected to the B input of a transceiver 4-18 is connected. The link signal CPURWC + occurs between the central processing unit 4-2 and the direction input (DIR) of the transceiver 4-18. When the signal CPURWC + occurs with a high level, data are sent to the central unit 4-2. If the signal CPURWC + occurs low, then data are received from the central unit 4-2. The logic signals CPUDAT + and INBDAT- are the The input side of a NAND element 4-16 is supplied, the output signal of which, namely the link signal ENBDAT-, is supplied to the enable input side of the transceiver 4-18. The link signal INBDAT- is on Output signal of decoder 4-8; it enables the transceiver 4-18 when the central unit 4-2 addresses a register in memory 10 which is used by the cathode ray tube controller and the DMA connector 12 is associated.

The storage subsystem 10 according to FIG. 3t> has a ROM read-only memory 10-2 comprising 2OK words and a ROM memory 10-4 comprising 8K words with random Access to. The ROM memory 10-2 consists of ten circuits of the type 2716, as it is in the Intel data catalog published by Intel Corporation in 1977. Each ROM memory circuit 10-2 stores eight bits in each of the 2048 address storage locations. The ROM memory 10-4 consists of 16 circuits of type 2104A as described in the aforementioned Intel data catalog. Any RAM memory circuit 4-2 stores one bit in each of 4096 address locations.

The address bus line 18 outputs the signals BUSAOO-15 + 00 to the input side of a register 10-6, whose output signals BINAOO-15 + the input side of a register 10-8 are fed. The output signals BINAOO-10 +

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are supplied to the address input terminals of the ROM memory 10-2, and the signals BINA11-15 + become the The input side of a ROM selection logic 10-12 is supplied. The ROM selection logic 10-12 selects one of ten ROM memory chips 10-2 off. The signal BINAOO-10 + selects one of 2048 address locations in the selected ROM memory chip 10-2 off.

The output signals M1CM0-7 + 0A of register 10-8 become a RAM selection logic 10-20 issued on a first cycle, and the output signals ΜΞΜΑ0-7 + 0Β are the RAM select logic 10-20 supplied on a second cycle. The output signals MEMO-5- of the RAM selection logic 10-20 are the RAM memory 10-4 to select one of 4096 address locations. The first and second cycle selection logic is not shown since it is not essential for an understanding of the invention. The registers 10-6 and 10-8 are enabled by the following logic circuit. The control bus line 20 conducts this Signal MUMSTR- to the input side of a NOR gate 10-16, whose output signal is increased by 40 ns by means of a delay line 10-14 delayed and after inversion by means of an inverter 10-18 the release input of the Register 10-6 and 10-8 is supplied.

The output signals of the ROM memory 10-2 and the RAM memory 10-4, namely the data signals ROMDO-7 + and RAMD0-7 + 0A, are fed to a register 10-10 via a junction 16-2, which during the period is enabled, during which the bus line enable signal BUS30 + occurs with a high level. The output signal of the register 10-10, the data signal BUSD0-7 + 0B, is transmitted via a connection point 16-3 according to FIG. 3d the B connection of a transceiver 12-14 and to the Α-connection of a transceiver 4-18 according to Fig. 3a submitted. The transceiver 4-18 connects the data

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output of the memory 10 with the data bus line 16 for the purpose of connection to the central unit 4-2. Of the Transceiver 12-4 is at the data output of memory 10 connected to the data signals BUSD0-7 + 0B to the cathode ray tube controller and the DMA connection see notice 12.

The keyboard and switch subsystem 8 of Fig. 3a comprises a keyboard 8-2, a plurality of switches 8-4, a multiplexer 8-6 and a multiplexer 8-8 _# The keyboard 8-2 and the switches 8-4 are connected to the inputs of multiplexers 8-6 and 8-8. The outputs of the multiplexers, which emit the data signals CPUD0-7 + 0D and CPUD0-7 + 0E, are connected to the connection point 16-1 of the data bus line 16. The multiplexer 8-6 is enabled by a decoded address signal PIA1EN- which is generated by the decoder 4-8. The multiplexer 8-8 is enabled by the output signal of the NAND gate 8-10, the input signals of which are the signals PIA2EN-, which are generated by the decoder 4-8, as well as the signal CPURDD- and an output signal of the central unit 4-2. Under the control of the central unit 4-2, an address signal CPUAOO-15 + 00 in the form of the hexadecimal address E010, which is received by the decoder 4-8, results in the linkage ssignal PIA1EN- as link signal 0 enabling the multiplexer 8-6 . In a corresponding manner, the hexadecimal address E020 causes the logic signal PIA2EN- to appear at a low level in the decoder 4-8, whereby the multiplexer 8-8 is enabled when a logic signal CPURDD-, the data signal read out, occurs at a low level. The logic signal CPURDD- is generated by a NAND element 8-12 from the input signals CPUVMA +, which indicate the presence of a valid address on the address bus line 18, from the signal CPURWC +, which is a write-in process

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into the central processing unit 4-2, and as the CPUPH2 timing signal generated. The address line signal CPUAOO + becomes a select terminal 1 of the multiplexer 8-6 is supplied to the input side, and an address line signal CPUA01 + becomes the input side of a select terminal 2 of the multiplexer 8-6 and a selection terminal of the multiplexer 8-8. These address signals select the keyboard and / or switch outputs for connection to connection point 16-1 of the Data bus line 16 off.

The communication subsystem 6 according to Fig. 3e comprises a universally applicable synchronous-asynchronous receiver-transmitter unit, referred to below only as a USART device 6-2, a baud frequency generator 6-4 and an external device such as a modem 6-6. the USART device 6-2 represents a communication interface device of the type 8251 from Intel Baud frequency generator 6-4 supplies the receive clock timing control signal RCVCLK and the transmit clock timing control signal XMTCLK for the USART device 6-2. The baud frequency values are loaded into the baud frequency generator 6-4 under the control of the central unit 4-2. the Central unit 4-2 sends a hexadecimal address EO30 via the address bus line, which is stored in the decoder 4-8 is decoded as signal LDBRG1. The central unit 4-2 sends the coded baud frequency signals over the data bus line 16 to the baud frequency generator 4-6. These signals are used to clock-controlled data from the USART device 6-2 to the modem 6-6 via the signal line XMITDA or from to supply the modem 6-6 with data received via the signal line RCVDAT by clock control of the USART device 6-2.

The USART device 6-2 is activated by signals CPUDO-7 + 00 connected to the data bus line 16. If the USART

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Device 6-2 is addressed, the address signal CPUA01 + of the central processing unit 4-2 occurs with a high level and control information is on the Data bus line 16. The low level address signal CPUAO1 + indicates that data information is present on the data bus line 16. The USART facility 6-2 reads the information from the Data bus line 16 if the link signal CPURDD, the output signal of the NAND gate 9-12 is given by 102. The USART device 6-2 writes or outputs information to the data bus line 16 when the logic signal 8251 WT, the output signal of a NAND gate 6-8, occurs with a low level. The inputs of the NAND gate 6-8 are the signals CPURWC-von an inverter 6-10 and SRBIT9 + and a timing pulse from the timing and control logic 2-2. The timing sampling signal MEMSTR + from the output of timing and control logic 2-2 shown in Figure 3a causes the data signals CPUD0-7 + 0C to be keyed into the USART device 6-2.

Referring to Fig. 3d, the cathode ray tube controller and DMA connector 12 include one Cathode ray tube controller 12-2, a character generator and an image display device 12-10 and an address counter 12-14, a register 12-12, a driver 12-16 and a transceiver 12-4. Of the Counter 12-14 is loaded from the central unit 4-2, the hexadecimal addresses E031 and E032 via the address bus line 18 gives up. As a result, the logic signal LDADDH +, the output signal of the decoder 4-8, is high Levels occur, whereby the register 12-12 is enabled. The address location E031 of the ROM memory 10-2 according to Fig. 3b stores the eight high order bits of the Start address of the RAM memory 10-4 for the picture display character. These high order bits are extracted from the

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Read out ROM memory 10-2 via the register 10-2 and the transceiver 12-4 according to FIG. 3d and stored in register 12-12 as signals CRTDO-7 + 10. The signal CRTDO + 10 shows the timing and control logic 2-2 to initiate a system reset operation when decoder 4-8 a signal TCRSL- is generated. This link arrangement is illustrated in Figure 4b. On the next CPU bus line cycle, the central processing unit 4-2 sends the select address E032 indicating the corresponding location of the ROM memory 10-2, and the eight bits lower Values are read from the ROM memory 10-2 and via the register 10-10 and the transceiver 12-4 supplied to the counter 12-14. The output signals DMA08-15 of the register 12-12 are also in stored in the counter 12-14 since the enable signal LDADDL appears at a high level. The character generator and the image display device 12-10 are activated every DMA1 cycle. The output of the counter 12-14, the memory address BDMAO-15 + 00, occurs on the Address bus line 18 via a driver 12-16, the connection point 18-1 according to FIG. 3b, the register 10-6, the register 10-8 and the RAM memory 10-4. The data output signals RAMD0-7 + 0A are assigned to the register 10-10, the connection point 16-3 according to FIG. 3d, the transceiver 12-4, the connection point 16-4 for the cathode ray tube controller 12-2 as the data signal CRTD0-7 + 0A and the character generator and the blinking display device 12-10 as signals CGBITO-6 fed. The signal BUSAK1-, the output signal of a NAND element 12-18, switches the counter 12-14 further, to designate the next address storage location of the RAM memory 10-4. The timing signals SRBIT4- and SRBIT2 + from the timing and control logic 2-2 according to FIG. 3a become the input side of the NAND gate 12-18, as well as the bus line acknowledge signal BUSAK1, which is from the output of a

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AND gate 12-20 is delivered. The interrupt and priority logic 4-24 asserts an image request signal VDMARQ and a signal DMAK10, which the DMAI bus. 1 defines cycle time control. These signals are fed to the input side of a NAND gate 12-24, whose output signal VIDACK + is fed to the input side of the AND gate 12-20. The further entrance the AND gate 12-20 is supplied with a signal CPUADR-, which is the output signal of an inverter 12-22, the input signal of which is the timing control signal CPUADR + from the control bus line 20.

The counter 12-14 counts the rising edge of the signal BUSAK1-. The timing control signal CPUADR- occurs with a high Level up to begin a DMA cycle. The link signal DMAK10- occurs during the duration of the DMA1 cycle low. When the cathode ray tube controller and DMA connector 12 request a DMA cycle, then that occurs Request signal DVMARQ- with a low level, whereby the signal VIDACK + at the output of the NAND gate 12-14 occurs at a high level. As a result, the signal BUSACK1 + will appear at the output of the AND gate 12-20 with a high level, since the timing signal CPUADR- occurs with a high level. The signal BUSACK1 + at the output of the AND gate 12-20 causes the keying of the output signal of the driver 12-16, the address signals BUSAOO-15 + OA, in relation to time to the DMA1 address bus line cycle, namely, since the timing control signal CPUADR- the DMA timing on the Address bus line 18 defines.

The logic signal BUSAK1-, the output signal of the NAND element 12-18, normally occurs at a high level on. The signal in question is brought to a low level at the beginning of the DMA1 cycle of the address bus line 18, if the time control signals SRBIT2 + and SRBIT4-ge: aäß Fig. 4 occur at a high level. The linkage

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signal BUSAK1- will then occur with a high level when the timing control signal 3RBIT4- has a low level assumes, thereby incrementing the address stored in counter 12-14.

Up to six additional devices 14a to I4f can be connected to the data bus line 16, on the address bus line 18 and be connected to the control bus line 20. Any additional device may include additional priority and interrupt logic 14-2, a DMA register and facilities 14-4 and a memory 14-6 included. The additional priority and interrupt logic 14-2 is on the signal lines BUSA01-08 + 00 of the address bus line 18 and on the signal lines PRIACK-05, DMAREQ2 to DMAREQ4 and EXIRQ the control bus line 20 is connected. The additional devices are connected with the signal lines DMAK20-, DMAK30- or DMAK40- connected or wired to operate on bus line cycles DMA2, DMA3 or DMA4 will.

The DMA registers and devices 14-4 of Figure 3c are on the address bus line 18 via a register 14-18 and on the data bus line 16 via a driver 14-10 and a register 14-8 connected. The control signal BUSRWC is applied to the control bus line 20 via the driver 14-20 supplied to the memory 10 to provide an indication in the event that the peripheral devices of the auxiliary devices 14a to I4f will carry out a read operation or a write operation with respect to the memory 10. The DMA register and the devices 14-4 are also connected directly to the control bus line 20. The memory 14-6 is connected to the address bus line 18 through the register 14-18, and also it is on the data bus line connected via a register 14-12 and a register 14-14 and connected directly to the control bus line 20

The driver 14-10 and the register 14-14 are during

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of the DMA cycles enabled by the control signal CPUDAT-. Drivers 14-16 and 14-20 are during the DMA cycles enabled by the control signals CPUAD-. The DMA registers and facilities in question 14-4 and the memory 14-6 of their corresponding additional devices 14a to I4f are connected to the data bus line 16, the address bus line 18 and the control bus line 20 under the control of their respective ones Additional priority and interrupt logic 14-2 connected, which in conjunction with the interrupt and Priority logic 4-24 is working. The relationship between the peripheral accessories 14a to I4f, the The data bus line 16 and the address bus line 18 are explained in more detail in a different manner.

The special additional devices are wired in such a way that they are available on a specific cycle of the Cycles DMA2 to DMA4 according to FIG. 1 can be operated. The additional devices interrupt the central unit CPU in that .sie output a signal EXTIRQ- with a low level to the control bus line 20, whereby the Interrupt and priority logic 4-24 is signaled that an additional device 14a to I4f an operation requested by the central unit 4-2. The additional devices 14a to 14f give that of the relevant request signal assigned to a specific additional device DMAREQ2-4 with a low level in order to avoid the other additional devices, which are switched or wired in this way, that they are operating on a particular DMA cycle indicate that the auxiliary device in question the bus line has requested.

The additional devices are not described in detail here, as they provide a complete understanding of how they work these devices are not required for an understanding of the invention; the relevant additional devices are only explained to the extent that this is necessary for an understanding of the full range

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is required in which the invention operates. A description of the control signals is above he follows.

In Fig. 4 the detailed logic or linkage of the timing and control logic 2 is illustrated, the time control signals for or on the address bus line 18, the data bus line 16 and the control bus line 20 generated. A timing diagram of the associated signals is shown in FIG.

The output of the oscillator 2-4 is shown in FIG. Each oscillator cycle is 50.85 ns in the preferred embodiment. This value is chosen so that it is compatible with the baud frequency generator 6-4 according to FIG. However, the invention described herein is not limited to this value of the oscillator cycle time.

Twenty oscillator output cycles of 1.017 / Us put one CPU and DMA cycle fixed; they are designated as time slots 0-19 in FIG.

4, the 19.66 MHz output of the Oscillator 2-4 fed to the clock terminal of a shift register 2-6. The output signals of the shift register 2-6, namely the time control signals SRBITO + to SRBIT9 +, are illustrated in FIG.

The signal CPUPH1 + and the signal CPUPH2 + are called Clock signals used for the central unit 2-4. The output signal CPUPH1 + of an AND gate 2-8 then also occurs high level when the timing signal SRBITO + with high level occurs and when the signal CPUPH2- is high. When the time control signal SRBITO + assumes a low level during the time slot 10 of FIG. 5, then the output signal CPUPH1 +

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of the AND gate 2-8 a low level, the output signal CPUPH1- of the inverter 2-10 leads a high level, as well as the output signal SRBITO- of the inverter 2-16. Since both input signals of the AND gate 2-12 have a high level, the output signal CPUPH2 also occurs with a high level. When the signal SRBITO- occurs at a low level, the output signal CPUPH2 of the AND gate 2-12 becomes a low level assume, whereby the output signal of the inverter 2-14 will assume a high level. This will make the output signal CPUPH1 of the AND gate 2-8 occur with a high level. The timing signals CPUPH1 and CPUPH2 of the Central processing unit 2-4 continue the cyclical operation, as illustrated in FIG.

The time control signals CPUADR + and CPUADR- at the output of a flip-flop 2-18 lead to the generation of the timing signals for the address bus line 18, through the Control of the drivers 4-4, 4-6, 4-10 according to FIG. 3a, as well as of the driver 12-16 according to FIG. 3a and the drivers 14-16 and 14-20 according to FIG. 3c. The output of the oscillator 2-4 is applied to the clock input of flip-flop 2-18 and the timing signal SRBIT4 + is applied to the CD input fed. The flip-flop 2-18 will respond to the next signal rise of the output signal of the oscillator 2-4 is set in response to the rise of the timing control signal CRBIT4 +. The flip-flop 2-18 will rise to the next of the output signal of the oscillator 2-4 is reset in response to the fall of the timing signal SRBIT4 +.

In Figure 5, the address outputs are CPUAOO-15 + of the central processing unit 2-4 illustrates, using the timing signals CPUPH1 +. and CPUPH2 +, des Signals CPUADR-, which causes further scanning or linking of the address signals CPUAOO-15 + 00, and of the BUSAOO-17 signals appearing on the address bus line 18 have been generated, indicating the presence of a

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valid CPU address.

In Fig. 5 is also the valid DMA address BUSAOO-17 ' shown for the case that the timing signal CPUADR-mlt high level occurs. This valid DMA address is output from the output of the driver 12-16 according to FIG. 3d, and also from the output side of the drivers 14-16 and 14-20 of the auxiliary devices 14a to I4f as shown in FIG. 3e.

A flip-flop 2-20 generates the timing signals CPUDAT- and CPUDAT + on the data bus line 16. The flip-flop 2-20 is activated on the rise of the clock signal of the oscillator 2-4 are set to the clock cycle in which the timing signal SEBITO + occurs with a high level. That in question Flip-flop is reset on the rise of the clock signal of the oscillator 2-4 towards the clock cycle, in which the timing signal SRBITO + has a low level. In Fig. 5 the signal CPUDAT- is indicated, which defines the DMA data cycle when it occurs high and which defines the CPU data cycle when it occurs at a low level. The transceiver 4-18 according to FIG. 3a controls the timing on the Data bus line 16 during the CPU cycle, through the control of the enable connection by means of the output signal ENBDAT + of the NAND element 4-16, which is controlled accordingly by the time control signal CPUDAT + will. The CPUDAT- signal causes the DMA cycle time control for the data bus line 16 by controlling the outputs of the register 14-14 according to FIG. 3c and the Driver 14-10 by means of the CPUDAT- signal and by controlling the write input of the cathode ray tube controller 12-2 according to FIG. 3d. The output signal BUSAK1-02 of a NAND gate 12-28 occurs during DMA1 cycle of FIG. 5 with a low level. The output signal VIOWRT- of a NAND gate 12-30 occurs

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then with a low level when the logic signal BUSO30- occurs with a low level, whereby the DMA cycle time on data bus line 16 for the DI4A1 image display cycle from cycle time 6 to Cycle time 11 according to FIG. 5 is set.

The timing signals SRBIT2 + and SRBIT4 + become the input side of an AND gate 12-26 as shown in FIG. 3a supplied, whose output signal T05T12 + is supplied to the input side of the NAND gate 12-28, whereby the output signal BUSAK1-02 is generated.

The memory strobe signal MEMSTR- is generated by a flip-flop 2-22. The timing signals SRBIT6 + and SRBIT9 + are fed to the input side of an exclusive-OR gate 2-32 according to FIG. 4a, its output signal TX7TX9 is fed to the CD connection of the flip-flop 2-22 according to FIG. 4b. The flip flop is going up on the rise of the clock signal of the oscillator 2-4 is set on the cycle in which the TX7TX9 timing signal occurs at a high level. The flip-flop in question reacts to the increase in the clock signal of the oscillator 2-4 reset to the cycle in which the timing control signal TX7TX9 is low. The signal MEMSTR- of FIG. 5 illustrates the timing of the flip-flop 2-22. The signal MEMSTR- becomes fed to the output control terminal of register 10-10 shown in FIG. 3b; it controls the individual appearance of the data signals BSD0-7 + 0B. Referring to Figure 5, the signals illustrate BUSDO-7 +, iDMA data reading, and CPU data read this scheduler. The signal ptA-Datenlesen is transferred to the signal (valid DMA address) occur, and the CPU data read signal is turned on the occurrence of a signal (valid CPU address). The output signal MEMSTR + of the flip-flop 2-22 according to FIG. 4b is a timing signal for the USART device 6-2 according to FIG. 3e.

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A flip-flop 2-28 according to FIG. 4b generates the timing control signals BUSO30. The timing signals SRBITO- and SRBITA + become the input side of an exclusive OR gate 2-38 fed whose output signal TX1TX4 to the CD connection of the flip-flop 2-28 is supplied. The flip-flop 2-28 is set at cycle time 5, i.e. the cycle after the signal SR4 + occurs with a high level, that is the timing control signal BUS030- according to FIG Flip-flop is reset at cycle time 11, that is during the cycle after the SRBITO + signal goes low. As described above, this sets Signal BUSO30- a DMA1 cycle on the data bus line 16 during a CRT controller write cycle 12-2 fixed. The BUSO30 + signal also controls the data output duration of the memory system on the data bus line 16 during a memory read operation by the output of the register 10-10 according to FIG Fig. 3b is controlled. The BUSO30 + signal has a similar effect Timing control functions in memory 14-6 and the DMA registers and devices 14-4 of the additional devices 14a to 14f according to FIG. 3c.

A flip-flop 2-26 generates the device scan signal DSVSTR- for use in the auxiliary devices 14a to I4f. The flip-flop in question is through the same Time control signals set and reset like the MEMSTR flip-flop 2-22; it effects timing of the additional devices 14a to I4f for the address bus line 16 and the data bus line 18.

A flip-flop 2-24 sets the timing for the refresh memory 10 and for the memory 14-6 in the Additional devices 14a to I4f by the signal BUSREF + fixed.

A flip-flop 2-30 according to Fig. 4a generates the timing

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signal BUS010- for the additional devices 14a to I4f. The signals SRBIT2- and SRBIT7 + are fed to the input side of the exclusive-OR gate 2-34, the output signal TX3TX7 to the CD connection of the flip-flop 2-30 is fed. The flip-flop 2-30 is reset on the cycle after the signal SRBIT2 + rises and set to the cycle after the next SRBIT7 + signal rises. The timing signal SRBIT2- is activated using an inverter 2-52 is generated, which inverts the signal SRBIT2 +.

The bus line write control signal BUSRWC +, which is at the output a NOR gate 2-46 occurs, is based on the signal CPURWC + and a signal from the central unit 4-2 generated. The signal CPURWC + is inverted by an inverter 2-50, the output signal of which is CPURWC- ii input side of the NOR gate 2-46 is supplied. The signal CPUADR + is applied to the other input terminal of the NOR gate 2-46 supplied. During a CPU bus cycle, the CPUADR + signal occurs high, causing the output signal BUSRWC is controlled by the signal CPURWC-, which then occurs at a low level, when information is read out from the memory 10 and fed to the central processing unit 4-2, whereby the signal BUSRWC + occurs on the control bus line 20 at a high level. When the CPUADR + signal occurs at a low level, this indicates a DMA cycle, the output signal of the NOR gate 2-46 then with a high level occurs. In this case, the additional devices 14a to 14f generate the signal BUSRWC + on the control bus line 20, which occurs with a low level when data is in the memory 10 from an additional device 14a to I4f are to be registered. A 330 ohm resistor 2-52 holds the signal line BUSRWC + high when an accessory device 14a to I4f has an inactive DMA cycle.

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A system reset device 2-54 according to FIG. 4a generates a reset signal for resetting all Flip-flops in the Timing and Control Subsystem In addition, the central unit 4-2 can thereby use all the registers in the additional devices 14a to I4f delete that it sends an address to the decoder 4-8, which then generates a signal TCRSL- through which a register 2-56 is enabled, which stores the signal CRTDOO + 10 for the data bus line 16 and which emits the relevant signal on the output side as signal BRESET-OA, which is fed to the input side of a driver 2-48 will. The driver 2-48 outputs the aforementioned control signals to the control bus line 20.

The interrupt and priority logic 4-24 takes interrupt requests from the various subsystems that are connected to the bus line. A fixed priority is given by the interruption and Priority logic 4-24 established.

According to FIG. 6, a signal EXTCOM-one is generated by the subsystem with the highest priority, an additional communication device Input of a register 4-38 supplied. An output INTPR1-00 becomes the input terminal 5 one Encoder 4-40 supplied.

The data acquisition operation of the communications subsystem 6 has the second highest priority and the data transfer operation has the third highest priority on. A signal RCVINF-a is used for the recording operation Input of the register 4-38 supplied. An output INTPR1-01 is input terminal 4 of the encoder 4-40 fed. A signal XMTINF- is an input for the transmission or transmission operation of the register 4-38 supplied. An output signal INTFR1-02 is supplied to the input terminal 3 of the encoder 4-40.

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The keyboard subsystem 8 has the fourth highest priority. A signal KYBINF- becomes an input of the register 4-38 supplied. A signal INTPR1-02 is applied to the input terminal 2 of the encoder 4-40.

The cathode ray tube subsystem 12 has the fifth highest priority. A signal SPINTF- becomes a Input of the register 4-38 supplied. An output signal INTPR1-04 is the input terminal 1 of the Encoder 4-40 supplied.

The peripheral additional devices 14a to I4f have the lowest priority. A signal EXTIQ- is fed to one input of the register 4-38. An output signal INTPR1-05 is applied to input port 0 of encoder 4-40.

Encoder 4-40 is a priority type 74148 encoder with eight input lines and three output lines. The coded output signals are the highest for the input signal to be fed to the encoder 4-40 Priority effective.

An output signal CPUIRQ- from the encoder 4-40 is applied to the input terminal of the central processing unit 4-2 as shown in Fig. 3a. As a link signal 0, this signal enables the central unit 4-2 to terminate the current command or the instruction that has just been provided, and with suitable control, the central unit 4-2 switches to interrupt operation. The central processing unit 4-2 outputs the signals CPUAOO-15 + 00 to the CPU address bus line 19 in the hexadecimal form FFF8 in the first CPU cycle and in the hexadecimal form FFF9 in the second CPU cycle.

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The signals CPUA8 + to CPU15 + become the input side a NAND gate 4-44 supplied; they appear as logic signals 1 if the hexadecimal address FFXX occurs on address bus line 18. If the hexadecimal signals XXF8 and XXF9 on the Address bus line 18 is present and when a signal CPUVMA + of the central processing unit 4-2 occurs as a link signal 1, whereby the presence of a valid Address is displayed, then the input signals of a NAND element 4-46 appear as logic signals 1. The signals CPUAO1 + and CPU02 + appearing as logic signals 0 become the input side of a NAND element 4-78 supplied. The output signal CPU102, which is fed to the NAND gate 4-46, occurs as logic signal 1. The two input signals for the NAND gate 4-48 are logic signals 0, which cause the output signal IRQACK + to be output as logic signal 1, which indicates that the central processing unit 4-2 has acknowledged the interruption.

The output signals ADDAO1-, ADDA02- and ADDA03-, the so are coded to indicate the subsystem that requested the interruption will be the inputs a decoder 4-12 and via inverters 4-54, 4-56 and 4-58 the inputs of a driver 4-64 as signals ADDA01 +, ADDA02 + and ADDAO3 + supplied.

The IRQACK + signal is sent to an enable AND input of the Decoder 4-42 and an input of a NAND gate 4-66. The signal ACKENA, the output signal of a Timing NOR gate 4-50 occurs as logic signal 0 when the timing signals SRBIT4 + and SRBIT9 + occur as logic signals 1. That Signal CPUADR + OA is fed to one input of NAND gate 4-66; it indicates a CPU bus cycle when there is occurs as logic signal 1.

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If the subsystem requesting an interrupt is from an internal subsystem, then the Output signals COMACK- and PRIACK-, which occur as logic signals 1, the inputs of a OR gate 4-68 supplied. The output signal PRIACK-05 is used as logic signal 1 to another Input of the NAND gate 4-66 supplied. The output signal MYVECT- gives a driver as logic signal 0 4-64 free, and it also outputs the signals BUSA01 + 0C to BUSA04 + 0C to the address bus line 18, whereby that subsystem is indicated to the system, which causes an interruption. As described above, is the hexadecimal signal FFFX on the address bus line the starting address of an interrupt service routine that the microprocessor will execute. This is done using D-type flip-flops 4-30, 4-32, 4-34 and 4-36 by the interrupt request signals INTROO +, KYINT1 +, YMITIN + and RCVRIN +, respectively, from the cathode ray tube subsystem 12 from which Keyboard subsystem 8 and from the communications subsystem 6 set ago.

The flip-flops 4-30 to 4-36 are masked or prevented from setting under the control of the central processing unit 4-6. The relevant central unit generates the signals CRTDO2-O5 + 1O via the data bus line 16. These signals are fed to a register 4-80. In addition, the CPU 4-2 gives an address to the address bus line from, this address being decoded in the decoder 4-8 according to FIG. 3a as signal TCR2SL, by which register 4-80 is enabled. The output signals VIDINT, KYSINT, XMTINT and RCVINT are fed to the inputs of the OR gates 4-76, 4-74, 4-72 or 4-70. If these signals occur as logic signals 0, then the outputs of the OR gates 4-70 to 4-76 lead Link signals 0, which prevents the flip-flops 4-30 to 4-36 from setting, since the reset

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Input connections of the relevant flip-flops logic signals 0 are supplied.

The flip-flops are usually reset then if one of the output signals PRIACK-01 to PRIACK-04 of the decoder 4-42 is output as logic signal 0. This becomes the corresponding output of the OR gate 4-70 to 4-76 causes a logic signal 0 to be output, whereby the corresponding flip-flop 4-30 to 4-36 is reset.

If the central processing unit 4-2 acknowledges an interruption, a D flip-flop 4-60 is set at the time SRBIT7 +. If the output signal INTACK is a logic signal 1, then the output signal of a NAND gate is 4-62 output as logic signal 0, causing the other subsystems to interrupt until termination are prevented from processing the interruption.

If the interruption is from the peripheral accessory 14a to I4f, the output signal will be PRIACK-50 of the decoder 4-42 emitted as logic signal 0. As a result, the output signal PRIACK-05 of the OR gate 4-68 is output as logic signal 0. Reference is now made to FIG. 3a. The input signal PRIACK-05 of the AND gate 4-14, as logic signal 0, makes the driver 4-6 ineffective. Besides, the Driver 4-4 ineffective due to the input signal IRQACK- of the AND element 4-12, which occurs as logic signal 0 made. According to FIG. 6, the logic signal PRIACK-05 which occurs at the input of the NAND element 4-66 the driver 4-64 made ineffective. The bus address signals BUSA01-08 are received from the interrupt option delivered as described above.

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- yf-Si-

The signal COMCK-OO carries out operations in connection with the external additional communication device 25 in the appropriate way, in which the signal • PRIACK-50 in connection with the peripheral additional devices 14a to I4f performs operations.

Referring to Fig. 6, the CPU cycle that follows the cycle in which the CPU 4-2 the Hexadecimal address FFF9 has delivered to the address bus line 18, the delivery of a further address to the Inputs of the NAND gate 4-44 and the NAND gate 4-46 lead to the fact that the signal IRQACK + occurs as logic signal 0, whereby the flip-flop 4-60 at the time SRBIT7 + is reset. This enables register 4-38 at the time SRBIT1 + for the Recording of further or other interrupt signals.

Referring to Fig. 7, when the accessory device 14-88 requests access to the bus line, it is switched to the interrupt request signal line emitted a logic signal 1, whereby a D flip-flop 14-30 is set. The output signal appearing as logic signal 1 MYIRQS is fed to the input of an AND gate 14-36. Since the PRIACK-05 signal appears as logic signal 1 when no additional device 14a until I4f causes an interruption, the other input of the AND element 14-36 carries a logic signal 1 via inverters 14-32 and 14-34. The output of AND gate 14-36 becomes the J terminal of a JK flip-flop 14-38 which is asserted during the rise of the CPUADR- signal. This signal will be the CLK terminal of the flip-flop 14-38 via a NAND gate 14-44 and the inverter 14-46.

The output signal MYIRQF is the inputs of a NAND gate 14-54 and an inverter 14-90 supplied.

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The output signal of the inverter 14-90 causes the output of the signal EXTIRQ as logic signal 0 as Link signal 0, whereby an interruption of the Central Processor 4-2 is requested as described above. The central unit 4-2 can prevent the accessory 14-88 from being interrupted by hitting the interrupt mask signal line emits a logic signal 0, which prevents the setting of the flip-flop 14-38. this takes place in that a certain address signal, the address EXXX in hexadecimal form, is sent out, the from the address bus signals BUSAO-15 + 00 in the additional address selection logic 14-91 is decoded. This enables a register 14-40 and a through Pre-wiring given signal BUSDXX via the data bus line 16 and the register 14-40 output.

The EXTIRQ signal is fed to the input of the register 4-38 as logic signal 0 (FIG. 6). The output signal INTPR1-05 is used as logic signal 0 dem Terminal 0 of the encoder 4-40 supplied. The output signal CPIRQ- is used as logic signal 0 of the central unit 4-2 fed. The CPU 4-2 sends the hexadecimal address upon completion of its operation FFF8 to the address bus line 19 of the central unit. These signals are the inputs of the NAND gates 4-44 and 4-46 supplied; they lead to the generation of an acknowledgment signal IRQACK +, which the decoder 4-42 releases. The address signals ADDAO1, ADDA02- and ADDA03- all occur as logic signals 0, whereby the Output signal PRIACK-50 given as logic signal 0 will. As a result, the output signal PRIACK-05 of the OR gate 4-68 is output as logic signal 0.

030028/0821

According to FIG. 7, the input signals of an AND element 14-56 appear as logic signals 1. The signal PRIACK-05 is fed to one input via the inverter 14-32, the signal CPUADR- is fed to a further input via the inverters 14-48 and 14-50, and the signal MYIRQF is still the other input of the AND gate 14 -56 fed. The output signal MYIRQA is a logic signal 1, which is fed to the input of an OR gate 14-62. The output signal of this logic element enables the drivers 14-66 and 14-68. A switch bank 14-76 is preset to provide eight unique address bits for identifying the additional device 14-88. These signals are applied to input port 0 of multiplexers 14-64 and 14-72. The control signal CPUADR- is applied to the selection terminal of the multiplexers 14-64 and 14-72. Input port 0 is selected for the CPU cycle and input port 1 is selected for the DMA cycle.

The control signal DEVSTR- is the input of a NAND gate 14-60 fed. The output signal DEVSTR + is fed to the clock input of the flip-flop 14-52, whereby this Flip-flop is set when the DEVSTR + signal rises. The output signal MYIRQG occurs as logic signal 0 on; it is fed to the K terminal of flip-flop 14-38, which is reset with the occurrence of the next rise of the control signal CPUADR-, whereby the signal EXTIRQ occurs with a high level.

During the DMA cycle, the memory address generator 14-82 outputs the memory 1Q address, that is the signals BDMAO-15 + 00, when the additional device is effectively operating or connected to the bus line. The operation of the generator 14-82 is similar to the counter 12-14, the register 12-12 and 12-16 of the driver according to Fig. 3d.

030028/0821

The signal BDMAO-15 + 00 is input terminal 1 the multiplexers 14-64 and 14-72 are supplied. The output signals of the multiplexers 14-64 and 14-72 are fed to the input side of the drivers 14-66 and 14-68. The signals BDMAO, 9-15 + 00 become the inputs of the drivers 14-70 and 14-78 fed. An OR gate output signal is fed to the enable pins of drivers 14-66, 14-68, 14-70 and 14-78. The drivers 14-66 and 14-68 are enabled during the CPU cycle when the MYIRQA signal occurs as logic 1 signal and the additional device outputs the signals BUSA1-8 + 00 to the memory 10, which are indicative of the low-order hexadecimal digits of the ROM 10-2 address the firmware routine that handles the interrupt.

Drivers 14-66, 14-68, 14-70, and 14-78 are during of the DMA cycle released by the MYDMAA signal, which occurs as logic signal 1, when the additional device the address signals BUSAO-15 + 00 to the Memory 10 emits during the data transfer via the data bus line 16.

During the second CPU cycle, the relevant central processing unit 4-2 sends the hexadecimal address FFF9 via the CPU address bus line 19, with that as a link signal 1 occurring signal BUSAO + which is fed to one input of an AND gate 14-58. That as Logic signal 1 occurring signal MYIRQA is the other input of the AND gate 14-58, the J connection a JK flip-flop 14-52.

The EXTIRQ signal becomes each priority and interrupt logic 14-2 of the auxiliary devices 14a-14 I4f supplied in the system. Any auxiliary device requesting an interrupt pulls the EXTIRQ signal to a logic signal 0, in that they correspond to it

030028/0821

of the flip-flop 14-38 is set. The interruption and Priority logic 4-24 according to FIG. 6 responds in that it outputs the signal PRIACK-05 as logic signal 0. The PRIACK-05 signal is through the NAND gate 14-54 according to FIG. 7 of each additional device priority and interrupt logic 14-2 of the auxiliary devices 14a to 14f in a "circular Chain "switched. The priority of the additional devices is determined by the location of the respective additional device set in the "circular chain". Since the signal PRIACK-05 is in series with the additional devices is hard-wired, has the first additional device, with respect to which the signal PRIACK-05 is wired or connected is the highest priority, while the fifth option has the fifth priority, etc .. It should be noted that in the event that the signal PRIACK-05 as logic signal 0 is the NAND gate 14-54 is supplied and that the flip-flop 14-38 is set, the output signal of the NAND gate 14-54 occurs as link signal 1, whereby additional devices within the circular chain below of the additional device under consideration are due to the response to their corresponding interruption acknowledgment are prevented.

Referring to Figure 8, which illustrates a timing diagram of an interrupt requesting accessory, the MYIRQS signal is set to the 1 state. This sets the MYIRQF signal when the CPUADR- signal rises. The EXTIRQ signal is output as a logic 0 signal when the M ¹ ZIRQF signal is a 1 logic signal. The EXTIRQ signal, as logic signal 0, causes the CPUIRQ signal to appear as logic signal 0, which causes the central processing unit 4-2 to transfer the hexadecimal address FFF8 to the address bus line (CPUAXX) during a

030028/0821

Output the CPU cycle using the CPUADR signal. The hexadecimal address FFF8 is determined by the logic, and the signal IRQACK is generated, which is the additional device acknowledgment signal PRIACK-05 as Link signal 0 emits. As a result, the signal MYIRQA is used as logic signal 1 with the dropping of the Signal CPUADR- asserted, causing the option bus address signal BUSA1-8 is output via the address bus line 18. In addition, the INTACK signal is output as logic signal 1, whereby the Interruption of further subsystems with higher priority is prevented.

The hexadecimal address FFF9 is generated by the central processing unit 4-2 and delivered to the address bus line during the next CPU cycle. As a result, the MYIRQF + signal will occur as logic signal 0 when the DEVSTR- signal drops. In addition, the address signal BUSA1-8 is returned to the external address bus line. On the issued during the previous CPU cycle address signal BUSA1-8 towards an even address has been displayed. During this CPU cycle, the address signal BU31-8 indicates the next address. This address is increased or incremented by bringing a logic signal 1 into the position BUSAOO + OO. The signal MYIRQA converts the signal MYIRQS into a 0 signal as logic signal 0, and it also causes the output of the signal MYIRQF + as logic signal 0 (EXTIRQ as logic signal 1) or the rise of the signal CPUADR-. The signal MYIRQG + is emitted as logic signal 1 when the DEVSTR- signal drops. The IRQACK signal is retained as logic signal 0 in the third CPU cycle, as a result of which the INTACK signal is output as logic signal 0 at time SRBIT7.

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2952328

Thus, the invention provides a cathode ray tube display system created, which is controlled by a microprocessor and which a variety of peripheral devices, all of which are jointly connected to a system bus line. An arrangement provided in each peripheral device activates a single interrupt signal. A single acknowledgment response signal for all facilities enables the interrupting device to transmit its address signals to the system bus line, whereby a firmware routine is initiated that makes the interrupting device effective with the system close.

The arrangement in the cathode ray tube display system enables the time division of the system bus line between the microprocessor (CPU) and a direct memory access device (DMA) without the Reduce the performance of the central processing unit by dividing the system bus cycle into an address phase and a data phase is divided.

The cathode ray tube display system has a vectorial interruption. A system interrupts the operation by sending a request signal sends out to the CPU subsystem. The arrangement in the CPU subsystem creates a control memory address, the is modified by that arrangement which is initiated by the requesting devices, the Generate vector address. This vector address calls a firmware subroutine, which is the interrupt processed for the requesting entities.

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Claims (1)

DIPL. ING. HEINZ BARDEHLE Munich, PATENT ADVOCATE File number: My reference: ** 298 " Claims Terminal system, characterized in that a system bus line (16, 18, 20) is provided, that a memory subsystem (10) is effectively connected to the relevant system bus line (16,18,20) is, that a central processor subsystem (4) is connected to the system bus line, which with the Memory subsystem (10) is so operatively connected that a transmission of address signals via the relevant system bus line can be made which addresses are characteristic for a Storage space in the relevant storage subsystem (10), that a first plurality of peripheral subsystems (14a to I4f) is provided, which with the system bus line are connected and with the central processor subsystem (4) and the Memory subsystem (10) operatively connected and receiving a plurality of interrupt request signals generate in the event that they request access to the storage subsystem (10), and that the central processor subsystem (4) on the occurrence of the relevant plurality of Interrupt request signals to modify the address signals, wherein the modified address signals are characteristic of a first start address memory location, which is used to generate an interrupt routine through which a selected sub-system the first multitude of peripheral sub- 030028/0821 ORIGINAL INSPECTED systems (14a to I4f) with the central processor sub system (4) can be effectively connected. 2. System according to claim 1, characterized in that a second plurality of peripheral subsystems is connected to the system bus line (16,18,20) that the relevant second plurality of peripheral subsystems with the central processor subsystem (4) and the memory system (10) is operatively connected and generates an interrupt request signal that the central processing subsystem (4) an interrupt acknowledge signal in response to the relevant interrupt request signal generates that the second plurality of peripheral subsystems respond to the respective interrupt acknowledge signal to modify the address signals and that the modified address signals are characteristic of a second start address memory location, such that a selected Subsystem of the second plurality of peripheral subsystems having the central processing subsystem (4) is effectively connectable. 3. System according to claim 2, characterized in that the central processor subsystem (4) has an interrupt device to receive the interruption request signals from the relevant first plurality and the second plurality of peripheral subsystems and for creating one Central processor signal and a central processor device which is connected to the interrupt device and which is responsive to the occurrence of the central processor signal generated address signals which are characteristic of the in question upcoming memory location, the interruption device responding to the occurrence of the address signals 030028/082 i , 952326 the respective address signals in accordance with a selected one of the interrupt request signals modified. 4. System according to claim 3, characterized in that the interruption device is a memory device for storing the plurality of interrupt request signals that contains the relevant memory device is connected to a coding device, which is responsive to the occurrence of the Interrupt request signals generated coding signals which are characteristic of a selected interrupt signal with higher priority from the interrupt signals that with the coding device is connected to a decoder device which reacts to the occurrence of the selected Coding signals towards the interruption acknowledgment signal generated that with the decoder device a Selection device is connected, which on the occurrence of the acknowledgment signal out a display in the Case provides that the interrupt request signal in question from the second plurality of peripheral subsystems, and that with the encoder and the selector a first driver device is connected, which reacts to the occurrence of the relevant selected coding signals hin modifies the address signals in the event that the interrupt request from of the first plurality of peripheral subsystems is created. 5. System according to claim 4, characterized in that the second plurality of peripheral subsystems (8) comprises a switch device which allows certain coding signals to be generated with the relevant switch device a second driver 030028/0821 device is connected, which is able to respond to the acknowledgment signal, which is characteristic is for the interrupt request from the relevant second plurality of peripheral subsystems, and that the particular coding signals concerned modify the address signals allow, wherein the modified address signals are indicative of the second start address memory location. 6. Terminal system, in particular according to one of the claims 1 to 5 »characterized in that a system bus line is provided on which a memory sub system is connected, which stores operating routines in a read-only memory that a central processor subsystem is connected to the relevant system bus line, which a Contains microprocessor that is used to generate a variety of specific address signals to the Occurrence of a microprocessor interrupt request signal serves that a plurality of peripheral device subsystems is connected to the relevant system bus line, the includes an external request interrupt signal line which, in common with each of the in a A plurality of provided peripheral device subsystems and the central processing subsystem are connected is that the system bus line also serially sends an external handshake interrupt signal each of a variety of peripheral devices and the central processing subsystem being any one of a variety of peripheral device subsystems a first signal level to the relevant external request interrupt signal line to dispense that the subject is one of the sub-systems provided in a variety 030028/0821 peripheral driver sub-systems on the occurrence of the first signal level on the external handshaking signal line towards a plurality of Allowed to output address signals via the relevant system bus line, in such a way that the "relevant certain address signals are modifiable, and that the modified address signals to the memory for reading out the content of a first memory location of the memory concerned can be delivered in which a first word of the operating routine is stored, the first in question Word and the following words of the operating routine to the central unit to activate the b — a subsystem that meets in a variety provided peripheral subsystems. System according to claim 6, characterized in that the plurality of subsystems concerned are one peripheral device that generates an interrupt request signal in the event that an access to the memory is requested that the interrupt device on the occurrence of the relevant Interrupt request signal out a first signal level to the external request interrupt signal line outputs that the interruption device to the occurrence of the first signal level on the external acknowledgment signal line hin generates a request breach address signal and that an address generating means is provided that on the occurrence of the relevant request interrupt address signal the multitude of address signals via the system bus line for modifying the relevant address signals sends out. 030028/0821 8. System according to claim 7, characterized in that the interruption device is an interruption start device for storing the interrupt request signal and one with interrupt synchronizer connected to the starting device contains the interrupt request signal in question at the start of a CPU cycle stores in the case that the external handshake interrupt signal line carries a second signal level, and which generates a synchronization signal which the output a first signal level via the external request interrupt signal line causes, and that a device fulfilling an AND function is provided on the occurrence of the synchronization signal in question and the first Signal level on the external handshake interrupt signal line hin generates the request break address signal at the beginning of the relevant CPU cycle. 9. System according to claim 8, characterized in that the address generating device comprises a first device for generating the plurality of address signals and one with the respective first device contains connected driver device, which is responsive to the occurrence of the relevant request interrupt address signal the multitude of address signals via the system bus line for modification the specific address signal sends out. 10. System according to claim 9, characterized in that the plurality of peripheral device sub-systems form a first peripheral device sub-system having a first priority associated with the central processing subsystem and which on the occurrence of the central 030028/0821 unit generated external acknowledgment interruption signal out a first plurality of address signals creates a second peripheral device sub system is provided with a second priority, which with the first peripheral Device subsystem is connected and which is linked to that of the first peripheral device subsystem generated external handshake interrupt signal to a second plurality of address signals is generated, and that an n-th peripheral device subsystem having an η priority with the peripheral (n-1) th device subsystem and that of the peripheral (n-1) th device subsystem generated external acknowledgment interrupt ssignal towards an n-th plurality of address signals generated. 11. System according to claim 10, characterized in that each of the provided in a plurality of peripheral Facility Subsystems includes a priority facility responsive to the occurrence of the Synchronization signal towards a first signal level to the external handshake interrupt signal line outputs in such a way that the plurality of subsystems with higher priority are prevented from accessing the address external interrupt signal. 12. Terminal system, in particular according to one of the Claims 1 to 11, with a divided bus line time control cycle, characterized in that one System bus line with a control bus line (20) for the transmission of control information, with a Address bus line (18) for the transmission of address information and with a data bus line (16) for the transmission of data information it is provided that the address bus line and the data bus line 030028/0821 are subjected to such a time control that control signals for generating control center unit of S (CPU) cycles and of direct memory access φΜΑ) cycles that a memory subsystem (10) with the system bus line that one is operatively connected to the system bus line during the CPU cycles and the DMA cycles central processor subsystem (4) connected to memory subsystem (10) during CPU cycles is so operatively connected that a data transfer between the central processor sub system and an address memory part of the memory subsystem, which is carried out by the Central processing subsystem is referred to that a plurality of connected to the system bus line peripheral subsystems connected to the memory subsystem during the DMA cycles is that a data transfer between one of the provided in a plurality of peripheral subsystems and an address storage location of the memory subsystem, which is provided by a which is designated in a plurality of provided peripheral subsystems, and that with the Control bus line (20) a time control device (2) is connected, which is used to generate the divided bus line timing cycle and the control signals including an address bus line timing signal and generating a data bus line timing signal, the respective timing signals the central processor subsystem for generating the CPU cycle for the address bus line and serve for the data bus line and wherein the timing signals of the relevant plurality of peripheral subsystems for generating the DMA cycle for the address bus line and for the data bus line can be supplied, the data bus line timing signal from the address 030028/0821 bus line timing signal is offset by a certain amount. 13. System according to claim 12, characterized in that the time control device contains a clock device, which generates successive pulses that the timing device with a shift register device is connected, through which a certain sequence of pulses is generated, being selected Pulses of the particular sequence of pulses in question can be delivered to the storage device, and that the memory device generates the timing control signals by which the CPU cycle can be generated in the case is that the memory devices are in a first state during the DMA cycle generated in the event that the storage devices are in a second state. 14. System according to claim 13, characterized in that the memory means the address bus line timing signal and the data bus line timing signal for the purpose of generating the divided bus line timing cycle generated by the CPU cycle for the address bus line and the DMA cycle for the address bus in alternating cycles that the CPU cycle for the data bus line and the DMA cycle for the data bus line in alternating cycles and that the CPU cycle for the address bus line and the CPU cycle for the data bus line are offset from one another in time by a certain amount, the DMA cycle for the data bus line is offset in time by the specified amount. 15. System according to claim 14, characterized in that 030028/0821 - ίο - that the relevant specific amount of time by which the data bus line lags the address bus line, 305 ns. 16. System according to claim 12, characterized in that the plurality of peripheral subsystems concerned a cathode ray tube display subsystem (12) which communicates with the memory subsystem (10) is operatively connected during certain cycles of the DMA cycles that an indication of one in the relevant memory subsystem (10) stored information can be carried out. 17. Method of creating a split bus timing cycle in a terminal system, in particular according to one of claims 12 to 16, with a System bus line, which contains a control bus line, an address bus line and a data bus line, with a memory subsystem effectively connected to the relevant system bus line, with an on central processor subsystem connected to the system bus line, which is operatively connected to the storage system in question, with a plurality of peripheral subsystems which are connected to the system bus line and which are connected to the memory subsystem can be effectively connected, and with a time control device connected to the control bus line, comprising a clock generator, a shift register and a plurality of storage elements thereby marked, a) that successive clock signals are generated from the output of the clock signal generator, b) that the relevant successive clock signals are fed to the shift register, c) that a plurality of shift register signals generated by the shift register in question 030028/0821 is, the relevant plurality of shift register signals as logic signals 1 during a first specific number of the clock signals and as logic signals 0 during a second determined Number of clock cycles is output, d) that a first memory element is set in a first state in the event that a first signal of the shift register signals in logic state 1 is, while the relevant first storage element is set to a second state in the event that the relevant first signal of the shift register signals in logic state O in the case is that the relevant first memory element is controlled by clock signals, e) that the output signal of a second memory element in a second state in the case is set that a second signal of the shift register signals as logic signal 1 occurs while the second memory element in question is in a second state in the case is set that the relevant second shift register signal occurs as logic signal 1 in the event that the relevant second memory element is controlled by the clock signals, f) that the output signal of the first memory element to the central processor subsystem is output in the event that the first storage element is in the first state, while the output of the first storage element to the plurality of peripheral subsystems in the event that the first memory element is in the second state is located g) that the output signal of the second memory 030028/0821 elements is passed to the central processor subsystem in the event that the second Storage element is in the first state while the output signal of the second storage element to the plurality of peripheral subsystems in the event that the second storage element is in the second state, h) that the address signal of the central processor subsystem by the output of the first Storage element is forwarded in the event that the first storage element in the first State is such that one address bus line CPU cycle is produced, i) that the plurality of peripheral subsystem address signals is forwarded by the output signal of the first memory element in the event that the first in question Storage element is in the second state such that one address bus line DMA cycle is produced, j) that for data transfer between the central processor subsystem and the main memory subsystem Characteristic signals are forwarded by the output signal of the second memory element in the event that the second memory element in question is in the first state, such that a Data bus line CPU cycle is generated, and k) that for a data transmission between one of the provided in a plurality of peripheral Subsystems and the main memory subsystem identifying signals by the output signal of the second memory element in question are forwarded in the event that the relevant second memory element is in the second state, such that a 030028/0821 - 13 data bus line DMA cycle is produced. 18. The method according to claim 17, characterized in that the time division of the bus line cycle thereby takes place a) that the first memory element in question is in the first state with the first shift register signal is brought such that the address bus line CPU cycle is generated and that the second memory element is brought into the first state with the second shift register signal, such that the data bus line CPU cycle is generated with the second shift register signal lags the first shift register signal by 305 ns, and b) that the first memory element is set in the second state with the first shift register signal becomes such that the address bus line DMA cycle is generated, the second storage element being brought into the second state with the second shift register signal, such that the data bus line DM cycle is generated. 030028/0821