DE2628358A1 - Pattern recognition using electrical signals - has actual and required patterns arranged to transfer comparative data to summation logic unit - Google Patents

Abstract

The pattern recognition system consists of an actual pattern detector (1) with an electrical signal connection (2) leading to the actual pattern register (3). This is used in conjunction required pattern register (4). Both patterns transfer data patterns by links (5, 6) to a comparator (7) which totals the differences and sends them on to a summation unit (8). The system is designed to accommodate integrated circuit chips so that production samples may be compared with a master pattern. The summation circuits used are programmed to operate on the (X, Y) co-ordinate system to identify incorrect arrangements in a 2 dimensional array.

Description

Arrangement for automatic recognition of a pattern,

in particular for detecting the position of an image pattern. The invention relates to an arrangement for the automatic recognition of a pattern, in particular for position recognition a bilamuster by comparing the actual pattern with a predeterminable target pattern.

Such arrangements for comparing an actual pattern with a predeterminable one Target patterns are used in particular for controlling manipulators and positioners needed.

This must be from a variety of patterns of different shapes and size a pattern with a predetermined shape is automatically found and for example be brought into a precisely predetermined position in a processing machine.

Especially with miniaturized electronic components such as BED-Chi-s or transistors are used to improve the accuracy and speed of detection extremely high demands are made, which have not yet been satisfactorily solved could become. The clear recognition of a pattern through a simple edge measurement of light / dark transitions often not possible. To the optical Problems such as contrast, distortion, blurring due to height deviation and tilting of the object to be measured, there is also one caused by the production process in the case of the LED chips Disturbance of the actual pattern.

In this way, the contact surfaces to be determined can be replaced by the previous one Functional test appear visually significantly disturbed. Additional reflections, which are caused e.g. by dust, conductive adhesive or grinding marks further complicating pattern recognition.

The invention is therefore based on the object of providing an arrangement for to create automatic recognition of a pattern, which in terms of accuracy and the speed of recognition also for the contacting of LED chips is sufficient.

This task is carried out with an arrangement of the type mentioned at the beginning solved by an actual pattern detector for outputting an electrical signal sequence, whose cycle-wise successive electrical signals are grid points of an actual pattern grid are assigned, an actual value comparison memory connected to the output of the actual pattern detector a setpoint comparison memory for clockwise pushing through of the electrical signal sequence for the storage of predeterminable target pattern values, their storage locations corresponding Storage locations of the actual value comparison memory are assigned, one between actual value comparison memory and nominal value comparison memory connected actual pattern / nominal pattern comparison arrangement with at least one output for matching sample values and through a summing unit, which is connected to the output of the actual pattern / nominal pattern comparison arrangement.

In addition to the automatic recognition of image patterns for positioning, The arrangement according to the invention can classify, quality control and the like also for the automatic recognition of other patterns, such as acoustic patterns, used will. Due to the spatial shift of the actual pattern detector The electrical signal sequence output by one raster point at a time is the correspondence of the individual signals with the corresponding signals of the stored target pattern determined in real-time operation by adding the sum after each shift pulse of all matching sample values.

This process is repeated up to the last grid point of the grid field, so that the maximum number of matching Pattern evaluator a measure of the degree of similarity between the actual pattern and the target pattern results.

When comparing an actual pattern f2 (x, g) at the point x2, y2 with a specified target pattern f ¢ (x, y) at the point x1, y1, the aforementioned type of processing of the electrical signals can be mathematically derived from one of the displacement # , # of the actual pattern dependent function Y ~ \) dF can be derived, where! = x2 - x1 and X = y2 - y1.

This function forms a minimum if the cross correlation function contained therein forms a maximum. The size of the absolute minimum of the function V (t,) <) gives a measure of the similarity between the target pattern £ 1 (x, y) and the actual pattern f2 (x, y), while the position f, V of the minimum determines the shift between f1 (x, y) and f2 (x, y).

The correlation principle described enables a very high level of accuracy in recognizing patterns. Another advantage of the arrangement according to the invention results from the real-time processing of the electrical signals and the resulting associated extremely short processing time.

Preferably there is also a memory for storing the previously largest sum of matching sample values determined in the summing unit and one maximum query connected to the summing unit and the memory for comparison of the successive shift pulses of the actual value comparison memory determined sums of matching sample values provided.

As a result, the sum of the corresponding Sample values are compared with the stored sum and the absolute maximum of the Correspondence of the grid points of the actual pattern with the nominal pattern found will.

In a preferred embodiment of the arrangement according to the invention is the totalizer with a threshold switch for comparing the determined Sum of matching sample values with a predeterminable similarity threshold value tied together. The specifiable similarity threshold defines a sufficient similarity between the actual pattern and the target pattern and thus enables a high degree of flexibility in the various application cases of pattern recognition.

The actual value comparison memory and the setpoint comparison memory can be read out in parallel, with their associated outputs through Comparison logics are interconnected. After each shift pulse for the Pushing through the electrical signal sequence can in this parallel comparison arrangement the degree of agreement of the samples to be compared; invert simultaneously, i.e. can be recorded extremely quickly.

The actual value comparison memory and the setpoint comparison memory can also be read out serially, with their outputs using a comparison logic are connected to each other.

After each shift, impulse for pushing through the electrical Signal sequence circle the signals to be compared in the shift register and the Setpoint comparison memory once each with high frequency. For consecutive detection the degree of agreement of the to be compared Sample values then only a comparison logic is required.

The actual value comparison memory, the actual pattern / nominal pattern comparison arrangement and the setpoint comparison memory can also be connected in series, serial Comparison units be combined, with the outputs of the intermediate counter in parallel are led to a summing unit. This serial-parallel mixed form can be used with less Effort can be realized than the purely parallel comparison arrangement and leads to shorter processing times than with the purely serial comparison arrangement.

The actual value comparison memory is preferably a shift register. Such standard logic modules are for pushing through the electrical signal sequence particularly suitable.

The summing unit can consist of several in the manner of a cascade connection arranged adders exist. In such arrangements, the addition times are very short.

The arrangement formed according to the invention is intended in particular for Recognition of an image pattern be suitable. In such an application, the The actual pattern detector is preferably an image converter that scans according to a line raster. is In addition, a pixel counter controlled by the pixel clock of the image converter is provided, from the status of this pixel counter at the point in time at which the absolute maximum similarity occurs, the spatial shift between the actual pattern and the target pattern is derived will. The coordinates determined in this way can then be used for positioning the workpiece or a tool.

In the following, embodiments of the invention are based on the Drawing explained in more detail.

It shows Figure 1 shows the basic structure of an arrangement for recognizing any pattern in a simplified representation, FIG. 2 the representation an actual pattern / nominal pattern comparison arrangement for binary patterns, FIG. 3 the evaluation the signal sequence supplied by an image converter according to the correlation principle described in a schematic representation, FIG. 4 the functional principle for finding the correlation maximum using the example of a special image pattern, FIG. 5 shows the block diagram of an arrangement for automatic position recognition of a workpiece, FIG. 6 shows the circuit diagram of a first embodiment of the correlator of Figure 5, Figure 7 an embodiment for the summing unit of FIG. 6, FIG. 8 the circuit diagram of a second embodiment of the correlator of FIG. 5 and FIG. 9 shows the circuit diagram of a third embodiment of the correlator of FIG. 5.

FIG. 1 shows an actual pattern detector 1 which can be any actual pattern scans and converts the detected grid points of an actual pattern grid into an electrical Signal sequence 2 implements.

This electrical signal sequence 2 is fed to a shift register 3 serving as an actual value comparison memory and shifted through at a shifting cycle predetermined by the sampling frequency of the actual pattern detector 1. The nominal pattern to be compared with the actual pattern is programmed in a nominal value comparison memory 4. For the comparison between the actual pattern and the nominal pattern, each data output 5 of the shift register 3 is assigned to a corresponding data output 6 of the nominal value comparison memory 4. The Bit-Muoter of the shift register 3 and the nominal value comparison memory 4 are shifted against each other with each shift pulse so that after each shift pulse all memory location contents assigned to one another are recorded in an actual / target pattern comparison arrangement 7 and the respective sum of the individual comparison results in a connected one Summing unit 8 can be determined. The largest sum determined in the summing unit 8 within a complete cycle of all the raster points of the actual pattern raster represents the best correspondence between the actual pattern and the target pattern. The data outputs 5 and 6 assigned to one another are fed to the inputs of a comparison gate 9, the output 0 of which indicates the agreement or does not indicate the agreement. The following truth table results for the exclusive NOR gate shown with inputs A and B and output X: AWAY 0 0 1 0 1 0 1 0 0 1 1 1 The correspondence of memory location contents assigned to one another can, however, also be evaluated by other logic elements. In the case of AND gates, for example, the sum of matching sample values of a valency, for example illuminated pixels, is determined as the correlation maximum. On the other hand, the minimum of non-matching sample values can also be evaluated in the case of exclusive OD »lv gates or NAND gates.

Different types of comparison functions can be used for multi-valued target and actual patterns be programmed in an addressable read-only memory, with the data outputs 5 and 6 are led to the address lines of the read-only memory and from the to the information pending at the data outputs the address for the in the read-only memory programmed comparison result is formed. Preferably the function x = (A - B) 2 can be programmed into the read-only memory, whereby A = a1. 2 + a1. 21 + + am. 2m B = b. 20 + b1. 21 + + bn. 2 ai = (o, l) and b; = (o, 1).

FIG. 3 shows the evaluation of the data supplied by an image converter binary signal sequence according to the correlation principle in a schematic representation. That The actual pattern is captured by an image converter with 6 x 6 pixels. In the illustrated Line grids with the pixels BpO to Sp35 represent the illuminated ones in the drawing Image points shown filled in black represent the pattern to be found. The origin of the coordinates is placed in the pixel BpO. The electrical supplied by the imager Signal sequence, which by the vertically arranged sequence of the pixels BpO to 3p35 is shown figuratively, is fed to an actual value comparison memory 11 and pushed forward by one shifting cycle each time. As actual value comparison memory 11, for example, a shift register is suitable. The target pattern with which the actual pattern is to be compared includes one indicated by the dot-dash line 12 limited programming area with a total of nine memory locations Ss0 to Ss8. These memory locations correspond to the nominal value comparison memory 13, the corresponding memory locations through the vertically arranged row of memory locations Ss0 to Ss8 are shown. Each memory location of the setpoint comparison memory 13 is assigned a corresponding memory location of the actual value comparison memory 11, as indicated by arrows 14 and 15. Matching locations are checked after each shift pulse by an actual pattern / target pattern comparison arrangement 16 and their respective sum is determined by a counter 17 connected to it. If the count of the counter 17 is greater than the count of a previous one Shift clock, it is transferred to a memory 18. This is done after each Shift clock of the counter reading of the counter 17 with that stored in the memory 18 Counter reading compared by a maximum query 19. That way after a largest sum of matching memory location contents found during full scrolling, is thereupon by a threshold switch 20 connected to the maximum query 19 checks whether it reaches or exceeds a predefined similarity threshold value. If this is the case, a coordinate memory is released via the maximum query 19 21, which the coordinate feed quantities 22 for correct positioning of the object or a tool. The coordinates are determined by a Pixel counter 23, which counts the number of times before the occurrence of the absolute correlation maximum, the signals or the pixels shifted through the actual value comparison memory 11 detected and divided according to the grid division in x, y coordinates. In which In the case shown in the drawing, the absolute correlation maximum becomes z 229 = 9 determined, i.e. after 29 shift clocks VT, 9 memory locations assigned to one another are correct of the actual value comparison memory 11 and the setpoint comparison memory 13 match. After 29 shift cycles, the Coordinates for x = 5R and y = 4R determined, where R is the grid dimension of the line grid is.

In Figure 4, a predetermined target pattern is indicated by the dash-dotted line Line 25 and a programming area, which is divided into a grid field with 5 lines and 6 columns are shown by the dash-dotted line 26. That through The actual pattern captured by an image converter is shown by hatched areas, where the actual pattern 27 at the place of the Eorre- lation maximum and the actual pattern 28 shifted by one raster point to the correlation maximum Location is shown. The actual pattern 29 represents a control detected by the image converter which corresponds to the nominal pattern 25 in partial areas. The ones about the lined up Lines of the grid field plotted digital signal sequences are each with f1 for the target pattern 25, with f2 (27) for the actual pattern 27, with f2 (28) for the actual pattern 28 and designated by f2 (29) for the disturbed actual pattern 29. A comparison of the course these digital signal sequences result in the sum of the corresponding pixels for the actual pattern 27 ELÜ = 30, for the actual pattern 28 zÜ = 20 and for the disturbed actual pattern 29 E 8 = 27. With the sum of the matching pixels E2 = 30 thus found a clear correlation maximum. Despite the disturbance at f2 (29) the correlation maximum E 0 = 27 lies at the same point as at f2 (27).

Figure 5 shows the block diagram of an arrangement for automatic Position detection of a workpiece. The workpiece is recorded via a Diode matrix camera 30 with 50 x 50 pixels. The one from the diode Matrtx camera 30 output video signal 31 is in an analog-to-digital converter 32 into a digital Signal sequence 33 converted to the input of a 50 x 18 bit comprehensive Shift register 34, which serves as an actual value comparison memory, is performed.

Shifting the digital signal sequence 33 through the shift register 34 takes place with the pixel frequency specified by the diode matrix camera 30 1 of 100 kHz. 18 x 18 storage locations of the shift register 34 have one data output indicated by arrow 35. The pattern to be found is a nominal pattern programmed in a target value comparison memory 36, in which also 18 x 18 memory locations have a data output indicated by arrow 37.

In this case, one data output of the shift register 34 is in each case one Data output of the setpoint comparison memory 36 assigned arranges. The bit patterns of the shift register 34 and the setpoint comparison memory 36 are shifted against each other by the pixel clock T1 in such a way that after each shift pulse T1 all associated and matching memory location contents in one Determined actual pattern / nominal pattern comparison arrangement 38 and, for example, with a Frequency of 20 14 Hz can be given to a summing unit 79. The shift register 34, the nominal value comparison memory 36, the actual pattern / nominal pattern comparison arrangement 38 and the summing unit 39 form a correlator 100, the highest count of the Sumruierwerkes 39 represents the absolute correlation maximum. For investigation a maximum table 40 and an 8-bit memory 41 serve for the correlation maximum. The counter reading of the summing unit 39 determined after a pixel clock is also included the largest count of previous pixel clocks stored in memory 41 compared by the maximum query, as shown by the arrows 42 and 43 is. If the newly determined counter reading of the summing unit 39 is greater than that in the memory 41, the transfer 45 takes place via the enable 44 of the new count on the memory 41. In this way, the memory 41 the largest number of matching memory location contents after each complete image cycle at. A threshold switch 46 checks the absolute maximum of the matches and sets the minimum required similarity using a similarity threshold between the actual pattern and the target pattern. If this minimal similarity is achieved, in this way the release 47 of a coordinate output 48 takes place. To determine the coordinates is in a controlled by the pixel clock T1 pixel counter 49 the number of with 50 pixels fully run through the image lines and the number of pixels of the image line that has not yet been fully passed through, up to the point in time at which the correlation maximum is reached. The number of image lines and pixels results in the current pixel coordinates, which are in the coordinate output 48 are stored, provided a correlation maximum and the specified similarity threshold value are achieved. With each new maximum value those in the coordinate output 48 stored coordinates by the pixel coordinates assigned to the new maximum overwritten, so that after a complete scrolling through the image the absolute maximum assigned coordinates are stored. The on the implemented as 14 bit memory Coordinate output 48 adjacent coordinate quantities 50 are digital coordinate delivery quantities for positioning the workpiece in relation to a tool or for positioning of a tool in relation to the workpiece. The control of the automatic Detection of the position of the workpiece is carried out by a sequence control 51, the Start is indicated by arrow 52. The pixel clock is sent to the sequence control 51 T1 and the image clock 23 of the diode matrix camera 30 out, while they in turn to control the shift register 34 and the pixel counter 49 enables the clock 1.

FIG. 6 shows the circuit diagram of a first embodiment of the correlator 100 of FIG. 5. The illustrated correlator comprises a serial and parallel readable thrust register 340, a target value comparison memory 360, an actual pattern / target pattern comparison arrangement 380 and a summing unit 390. The comparison of the storage location contents of the shift register 340 with the memory location contents of the setpoint comparison memory 360 takes place purely parallel. For this purpose, the output from the analog / digital converter 32 of FIG. 5 is used digital signal sequence 33 with the pixel clock T1 through the shift register comprising n stages 340 pushed. The n parallel outputs of shift register 340 are on, respectively an input of an exclusive NOR gate of the n exclusive NOR gates Actual pattern / nominal pattern comparison arrangement 380 performed, with the assignment being carried out the letters a, b, c, d, y and z are indicated. The other inputs of the exclusive NOR gates are each with a data output of the setpoint comparison memory, which also has n levels 360 connected. While the setpoint comparison memory 360 in the Drawing is shown as a switch field, any other memory types, in particular read-only memories are used. The outputs of the exclusive NOR gates are led to the summing unit 390, at its output after each shift pulse T1 the sum of the matching memory location contents is given as a binary number will.

In FIG. 7, an exemplary embodiment for the summing unit 390 is shown FIG. 6, the actual pattern / nominal pattern comparison arrangement 380 of Figure 6 is partially shown for a better overview. The totaling unit shown is designed for a correlator with n = 15 stages and consists of four 1-bit adders 60, two 2-bit adders 61 and a 3-bit adder 62, which in the manner of a cascade connection are arranged. To simplify the graphic representation are only two of the total of four 1-bit adders 60 are shown.

FIG. 8 shows the circuit diagram of a second embodiment of the correlator 100 of FIG. 5. The correlator shown includes a serial read-in and read-out Shift register 341, a nominal value comparison memory 361, an actual pattern / nominal pattern comparison arrangement 381 and a summing unit 391. The comparison of the storage location contents of the shift register 341 with the memory location contents of the setpoint comparison memory 361 takes place purely serial. For this purpose, the output from the analog / digital converter 32 of FIG. 5 is used digital signal sequence 33 led to the input 63 of the shift register 341 and with the pixel clock 1 applied to the shift pulse line 64 is pushed through. Of the Input 63 and output 65 of shift register 341 are linked to one another, so that the information stored in each case after each shift pulse T1 once can circle, as indicated by arrow 66. For this circling the Information is a second shift pulse line 67 is provided, which by a Clock T2 is controlled. In the same way is as seriall a- and readable shift register designed target value comparison memory 36t of Output 69 linked to input 68, for example from a programmable Read-only memory 70 a stored nominal value can be entered. So that Circling the information in shift registers 341 and 361 in synchronism with the clock T2 can take place, their shift pulse lines 67 are bw. 72 merged.

The actual / target pattern comparison is carried out by an exclusive NOR gate, which forms the actual / target pattern comparison arrangement and with its inputs is connected to the outputs 65 and 69 of the shift register 341 and 361, respectively. Are when circling the information in each case in the last stages of the shift register 341 and 361 are identical to the existing memory location contents, the exclusive NOR gate opens and gives a corresponding signal to the summing unit 391. In the case of a one-off The summing unit 391 thus shows circles of information after each shift pulse T1 shows the sum of the matching memory location contents. For a quick one In comparison, the frequency of the clock T1 should be as high as possible. With n-level Requirement 22> 21 applies to shift registers 341 or 361. n.

FIG. 9 shows the circuit diagram of a third embodiment of the correlator 100 of FIG. 5. The correlator shown is for one of the 50 × 50 pixels of the diode matrix camera 30 of FIG the programming area 16 x 18 pixels, i.e. 18 lines with 16 pixels each includes. The programming area is divided into three groups, with the group 1 lines 1 to 6, group 2 lines 7 to 12 and group 3 lines 13 to 18 are assigned. The output from the analog / digital converter 32 of FIG digital signal sequence 33 is shifted with the pixel clock 1 through a shift register, which consists of eighteen 16-bit actual shift registers that can be read in and out serially 75 and eighteen 34 bit actual value shift registers 76 which can be read in and read out serially. set is. The 16 bit actual value shift register 75 and the 34 bit actual value shift register 76 are connected in series in an alternating sequence, with each of the 16-bit actual value shift registers 75 of a 16-pixel line of the programming area and each of the 34 bit actual value shift register 76 the remaining 34 in a row of the diode matrix camera is assigned to lying pixels. The 34 bit actual value shift register 75 capture thus not the programming area and are therefore as empty registers without connections trained for comparison. The setpoint forgetting memory consists of a total of eighteen 16-bit setpoint shift registers 77 which can be read in and out serially, of which six in each case connected in series one of the groups 1 to 3 of the programming area assigned. Accordingly, the information is read in via a programmable read-only memory 78, which has an output 79 for group 1, an output 80 for group 2 and an output 81 for group 3. 16-bit actual value shift register 75 and 16-bit setpoint shift register assigned to one another 77 together with an exclusive NOR gate 82 and a counter 83 each form serial comparison units 84 which, in the same way as that shown in FIG serial comparison unit are constructed. The outputs 85 of the counters 83 are parallel to a summing unit 86, which, for example, in the same way as the Summing mechanism shown in FIG. 7 can be constructed. The 9 bit output 87 of the Summing unit 86 gives after each pixel clock T1 the sum of all matching Sample values as a binary number. The actual pattern / target pattern comparison is therefore carried out for the individual lines of the programming area serially and otherwise in parallel. These serial-parallel mixed form of the comparison of the actual sample values with the nominal sample values is for the arrangement shown in Figure 5 for automatic position detection of a Workpiece preferred, as it is extremely easy to recognize a saga allows a short time, the shift register 75 by appropriately arranged and addressable writing Read memory, preferably semiconductor memory, the shift registers 76 by the same or by addressable read-only memories can be replaced. If the latter is the case, the read-only memory 78 is omitted.

The one shown in the block diagram of FIG. 5 and the associated FIG Arrangement for automatic Sage detection of a workpiece was used for position detection used by BED chips on automatic contacting machines with very good success. The searched The main feature of the 400 x 400 / um large LED chips is their circular contact surface, which has a diameter of 100 µm and is accurate with respect to a bonding tool must be aligned. For this purpose, the image of the enlarged via a microscope is used BED chips captured by the diode matrix camera. At a frame rate of T1 from 100 3dIz a scrolling takes place in 25 ms. Since the evaluation circuit is based on the When the beginning of a picture cycle is synchronized, the coordinates are available at the latest available after 50 ms. With the help of the determined coordinates, either the corresponding LED chip or the bonding tool into the one required for contacting Position brought. The accuracy of the position detection is even with disturbed Images + 1/2 grid points of the diode matrix camera. With an image area of 400 x 400 / um gives the value + / um. Is the deviation between the actual sample and the target sample so large that several maxima of the evaluated correlation function have the same amplitude the position coordinates of the first maximum are output.

This is the minimum similarity specified by the similarity threshold is not reached, the "no chip" signal is output.

10 claims 9 figures

Claims (10)

Claims-1., Arrangement for automatic recognition of a pattern, in particular to identify the position of an image pattern by comparing the actual pattern with a predeterminable nominal pattern g e -k e n n n n z e i c h n e t by an actual pattern detector (1, 30) for outputting an electrical signal sequence (2, 31), whose clockwise successive electrical signals are assigned to grid points of an actual pattern grid, a actual value comparison memory connected to the output of the actual pattern detector (1, 30) (3, 34) for clockwise T) pushing through the electrical signals (2, 31), a setpoint comparison memory (4, 36) for storing predeterminable target pattern values and their storage locations corresponding memory locations of the actual value comparison memory (3, 34) assigned are, one between the actual value comparison memory (3, 34) and the setpoint comparison memory (4, 36) switched actual pattern / nominal pattern comparison arrangement (7, 38) with at least an output for matching sample values and a summing unit (8, 39), that is connected to the output of the actual pattern / nominal pattern comparison arrangement (7, 38) is. 2. Arrangement according to claim 1, characterized g e k e n n z e i c h n e t 2 that in addition a memory (41) for storing the largest so far in the summing unit (39) determined sum of matching sample values and one to the totalizer (39) and the memory (41) connected maximum query (40) to compare the with successive shift pulses of the actual value comparison memory (34) determined sums matching sample values are provided. 3. Arrangement according to claim 1 or 2, characterized in that g e k e n n -z e i c h ne t that the summing unit (39) with a threshold switch (46) for comparison of the determined sums of matching sample values with a predeterminable similarity threshold value connected is. 4. Arrangement according to one of claims 1 to 3, characterized g e -k e n n z e i c h n e t, -that the actual value comparison memory (340) and the setpoint comparison memory (360) can be read out in parallel and through their associated outputs Comparison logics (380) are interconnected. 5. Arrangement according to one of claims 1 to 5, characterized g e -k e n n s e i c h n e t that the actual value comparison memory (341) and the nominal value comparison memory (361) can be read out serially and their outputs (65, 69) by a comparison logic (381) are connected to each other. 6. Arrangement according to one of claims 1 to 3, characterized g e -k e n n z e i c h n e t that the actual value comparison memory (34), the actual pattern / nominal pattern comparison arrangement (38) and the nominal pattern comparison memory (36) to series-connected, serial Comparison units (84) are combined with intermediate counters (83) and that the Outputs (85) of the intermediate counter (83) are fed in parallel to a summing unit (86). 7. Arrangement according to one of the preceding claims, characterized g e It is not indicated that the actual value comparison memory (340, 341) is a shift register is. 8. Arrangement according to one of the preceding claims, characterized g e it is not indicated that the summing unit (39, 86) consists of several in the manner of a Cascade arranged adders (60, 61, 62) consists. 9. Arrangement according to one of the preceding claims, characterized g e It is not shown that the actual pattern detector (30) is a line raster scanning imager is. 10. The arrangement according to claim 9, characterized in that g e k e n n z e i c h -n e t that, in addition, a pixel counter controlled by the pixel clock of the image converter (30) (49) is provided.