DE2609064A1 - Digital processor hardware structure reconfiguration circuit - has bit field transfer unit containing 2 bit, byte and half word addressable data registers of word length - Google Patents

Abstract

A circuit for effecting the reconfiguration of the hardware structure of a programmable digital processor in the event of permanent storage and/or switching component defects is designed for the smaller possible error correction time expenditure. Reconfiguration is achieved by reducing the structure so that defective components are not used and their functions are transferred to similar components. A bit field transfer unit contains two bit, byte, and half word addressable data registers of word length connected together via a highway. Words can be transferred between the registers during a machine cycle and rearranged so that only non-defective bit positions are used.

Description

Circuit arrangement for performing reconfigurations of the hardware

product structure of a programmable digital computer (bit field transfer unit) The invention relates to a circuit arrangement for carrying out reconfigurations the hardware structure of a programmable digital computer when permanent Defects in memory and / or switchgear components on a reduced structure, in which the defective components are not used and their functions are similar intact components are transferred.

For the economical use of digital computers and the correct Performing the operations prescribed by the user is a high level of availability and integrity are essential. That will be despite the finite lifetime and Susceptibility to failure of the large number of electronic circuits and storage elements, from which the computer is built, through redundancy in the form of additional circuits or codes reached that allow sporadic malfunctions or permanent ones Diagnosing defects in the individual hardware components and the resulting defects Correct errors or mask them from the start.

There are methods for implementing error-detecting and error-correcting Codes, error diagnosis and correction by means of suitable test and correction circuits as well as error masking, e.g. known through triple modular redundancy.

In connection with the development of multiprocessor computing systems is another method of achieving a high tolerance for hardware defects has been proposed, which is referred to as 'graceful degradation'. she consists therein, in one made up of several identical processors and memory segments System those processors and memory segments in which permanent hardware defects occur, no longer assign or

the functions originally assigned to them by the system to the same type to transfer intact modules and thus the overall available hardware structure to reduce. This has a reduction in computing power - possibly to the replacement of the defective modules - the consequence, but does not lead to a complete one System failure.

The principle of 'gracefui degradation' can be transferred to the regular one two-dimensional cellular structure of the working memory or the one-dimensional Bit slice structure of the processor of a computer system, if suitable facilities are available to logically switch off defective cells or bit slices and their To perform functions through intact cells or I3itplatten of the same type permit. This enables 'graceful degradation' also in single-processor systems to be carried out with unsegmented work storage. This is an emulation problem in which the complete structure of the computer in the event of defects in memory cells or in processor bit slices through suitable reconfiguration to a reduced one Structure is emulated, and that is therefore solved on the level of microprogramation must become.

The invention is based on the task of reducing a predetermined Computer structure on error-free working components with the help of micro-programmed Reconfiguration through suitable circuitry additions in the computer in this way to support that the additional expenditure of time for the implementation of error-correcting Micro-operations are kept as low as possible.

This object is achieved according to the invention in that a bit field transfer unit that the bit field transfer unit is connected between the processor and the main memory essentially from a bit-, byte- and half-word addressable first data register of word length and a bit, byte and half-word addressable second data register of word length that the first and the second data register via data transmission paths are connected in such a way that each bit, byte or half-word extractable from the first data register and into a predetermined one Bit, byte or half-word position of the second data register can be used, so that a first data word that occurs as a result of the use of one or more defective circuits or memory elements contain erroneous bits or bit fields by inserting correct ones Bits or bit fields in a second data word in error-free bit or bit field positions are provided, can be completed, or that from a first data word Before using defective components, the bits or bit fields that coincide with a defect extracted and in a second data word in error-free bit or bit field positions can be used.

An advantageous embodiment of the invention is that the Data buffer register of the memory on the output side with the inputs of the first data register and is connected to the inputs of the second data register, so that a data word transferable from the data buffer register to either of the two data registers is that the outputs of the second data register with the inputs of the data buffer register and the inputs of the memory address register are connected so that a Data word from the second data register either into the data buffer register or the memory address register is transferable.

The advantages of the circuit arrangement according to the invention are that the decomposition of data words necessary for error correction into individual Bits or bit fields and their correct positioning when inserted into a second Data word or

the assembly of data words from individual bits or bit fields can be performed with a minimum of additional micro-surgical steps, and that by the arrangement of the bit field transfer unit at the interface between RAM and processor during data transfer Errors in the respective source module can be corrected before the data word is transferred to the sink module and data words are adapted to the defect before transfer to a defective sink module can be.

An embodiment of the invention is shown in the drawing and is described in more detail below.

1 shows a schematic representation for correcting bit plane defects in the working memory, Fig. 2: a block diagram of the bit field transfer unit and its Arrangement at the interface between processor and main memory.

To illustrate the mode of operation of the circuit arrangement according to the invention the principle of microprogrammed reconfiguration based on the correction of Defects in the main memory and the correction of processor defects in detail explained.

The basic building block of a main memory is generally a module consisting of an arrangement of 2k binary # memory cells with consecutive Addresses, e.g. a core memory matrix or a semiconductor memory chip (MOS). A Memory of 2N (N »k) words capacity and 2n (3 <n« N) bits word length therefore made up of 2N-k blocks of 2n of these modules that make up the cover the same address range. The address decoding logic exists accordingly of two stages, the first of which is the respective memory block and the second identifies the memory word within a block. An address trunk consisting of N lines supplies the address code to the address decoding logic, and one Data bus line of 2n lines takes over the data transport between the memory cells and the data buffer register of the memory.

According to this physical structure of the memory there are three idealized defects to which all defects that actually occur are attributed can distinguish.

1) The defect of a memory module causes the failure of a bit plane segment in an address range between the addresses g. 2k and (g + 1) ~ 2k-1.

2) The defect in a line within the data bus caused the failure of the corresponding complete bit plane.

.3) The defect in a line within the address bus the failure of a total of 2N 1 memory cells in a periodic pattern are distributed over the entire address range.

The basic method for correcting the first two defects consists of special correction bit fields for memory areas with defective bit planes in another suitable memory area, and there those bits of complete data words that coincide with the defective bit planes. Correspondingly, a data word read from such a memory area must go through Bits from the correction bit field are completed, and from one in this memory area The data word to be written must have the error-coincident bits extracted and separately written in the correction bit field.

In the case of the defect of bit plane segments of length 2k, it can it is assumed that there are still blocks of length 2k in the memory, in which complete data words can be saved without errors. One or more Contiguous blocks of this type are used as the correction bit region in the Correction bit fields can be created as follows: The defect of a memory module in the address range g ~ 2k ...

(g + 1) ~ 2k-1 refers to a storage capacity of 2k bits contained in one Correction bit field of 2k n words can be accommodated.

To simplify the addressing of the correction bit fields becomes independent on the number of bit segment defects actually occurring for each of the 2N k physical memory blocks a correction bit field in a contiguous memory region of 2h (h = 0,1,2, ...) physical blocks whose start address is an integer Multiples of 2h + k should be reserved. Starting at this base address will be the following address space is subdivided into 2N fields of Zk n memory words in such a way that that the i-th field contains the correction bits of the i-th physical memory block and, more precisely, that the j-th word in the i-th field, and in it the l-th bit, is the error coincident Bit ues under the address = i ~ 2k + j. 2n + e stored data word contains. This means that the address of the correction bit can be taken directly from the address of the data word can be derived themselves.

As shown in Fig. 1, the first N-k bits of the address are identical to the address of the correction bit field relative to the base of the correction bit region CBR, the following k-n bits address the word within the correction bit field CBF, and the last n bits address the bit within the word.

In order to carry out this correction procedure, it is also necessary to create an error table in a suitable third place in the memory, as entries the addresses of the physical memory blocks with bit plane defects and the respective Contains numbers of the defective bit planes.

The correction is now carried out as follows. Should a data word under the physical address p is read, a memory access with done at this address. At the same time, the error table is used to determine whether the generated address contains a defective bit plane segment. Is that the case, then a second memory access is carried out with an address specified by Add the most significant N-k bits of the address p to the least significant N-k Bits of the base address of the correction bit region CBR is formed. From the under this Address read out word is made using the least significant n bits of the address p extracted the correction bit and in the data word read out at address p inserted in the bit position under the corresponding entry in the error table is specified.

If a bit plane fails completely, the specified correction method are modified to the extent that in this case there is nowhere in the memory a complete Data word and consequently the correction bit fields in the previous Form cannot be created. Therefore the correction bit fields only memory half-words used, namely left half-words, if the bit plane failure occurs is in the right half of the word and vice versa. This will be the same for the whole Correction bit region required address space doubled, but the addressing mechanism r smus is essentially retained.

The defective line within the address trunk line can result be corrected in a similar manner. -As the available address space is independent of the Bitpositicn of the defect shrinks to half, becomes a pseudo address space between the addresses O and 2N 1 assigned by the memory management, i.e. all Addresses whose most significant bit contains a 0.

This pseudo address space can be mapped to the actual physical address space still available due to the defect by adding the address bit, that coincides with the defective address line, in the most significant address bit position is used before the memory is addressed if the defective address line does not coincide with the most significant bit anyway.

The corrective methods for these three types of memory defects is here in common that a bit from a suitably specified bit position of a first Data word extracted and into a likewise specified bit position of a second Data word is used. In the case of defects in several bit planes, this can be several Concern bit positions. So it is also conceivable to use the specified method the basis of nibbles (contiguous fields of four bits), bytes (fields of eight bits) or half-words.

In principle the same methods can also be used for the Correct errors caused by defective bit slices in the processor. In the event of a defective bit slice, the arithmetic / logical functional unit can E.g. for logical operations that are carried out bit by bit via the operand data words the operation to be carried out as usual, in which case the defective one A faulty bit in the result word is to be expected in the binary position corresponding to the bit slice is. To correct this, the operation can be carried out with, for example, one or more Binary digits to the left or right shifted operands are repeated, so that the bit coinciding with the defective bit slice in the first operation is now is calculated on an intact bit slice. This bit is then turned off extracted from the result word obtained and converted to the correct binary position in the result word obtained in the first operation. Alternatively, it is possible and for arithmetic operations with carry formation, the operations to be executed on operand half-words, with the left half of the arithmetic / Logical unit is used when the defective bit slice is in the right one Half is and vice versa. It becomes necessary from a first data word E.g. the right half of the word closed extract and in a second Insert the data word in the left half of the word.

With a view to the fastest possible execution of the total for Correction of a defect necessary micro-operations, it is necessary to change the bit or bit field transfers, if possible within a machine cycle, by a special one To let the bit field transfer unit unwind. Because of their double function of correction from memory and processor defects, this unit is expediently at the interface arranged between processor and memory.

A schematic representation of the bit field transfer unit is shown in FIG. 2.

Two data registers are essential components of the bit field transfer unit R1 and R2, which in the exemplary embodiment each comprise 32 binary digits. For execution of a bit (field) transfer becomes the data word from which the bit (field) is extracted should, in the data register Rl, and the data word in which the bit field is inserted is to be loaded into the data register R2. A complete data location can be over the 32-line data bus B7 from the data buffer register MBR of the memory is loaded both into the data register R1 and into the data register R2 will.

Via a second data bus, also consisting of 32 lines B4 can transfer the data word contained in the data register R2 into the memory address register MAR as well as in the data buffer register MBR. In the exemplary embodiment facilities are provided for both individual bits and bytes (fields of eight bits) and half-words from the data register Rl into the data path register R2. These devices are a data line Bl, which consists of a single line for transmission of a bit, a data bus line B2, consisting of 8 lines, over which a byte can be transmitted and a data bus B3 for transmission a half-word and a 5-bit address register A1 for addressing individual bits, Bytes or half-words in the data register Rl, a 5-bit address register A2 for Address individual bits, bytes or half-words in the data register R2 and a 2-bit control register BB, with the help of which between bit addressing (BB is set to 00) and byte addressing (BB is set to 01) and half-word addressing (BB is set to 10) can be. The address registers A1 and A2 can encompass five lines Data bus B5 from the five least significant binary digits of the data buffer register MBR are loaded while the control register BB from the control unit of the computer is set via line B6.

If the control register BB is set to 00, all five bits the address registers A1 and A2 for addressing one of the 32 binary digits of the registers Ri or R2- used. In the case of byte addressing, i.e. if the control register BB is set to 0i, only the most significant two bits become the pegister A1 and A2 are used to address one of four bytes in registers R1 and R2. In the case of half-word addressing, i.e. when the control register BB is set to 10 is just there; Most significant bit of the address registers A1 and A2 for addressing one of two half-words of the data registers R1 and R2 is used. The address decoder are not shown in FIG.

The mode of operation of the bit field transfer unit should now be based on the Reading out a data word from a data word impaired by a bit plane defect Storage area are explained.

The processor generates a physical address, the code of which is in both the memory address register MAR and the data buffer register MBR is loaded If by comparison with the error table it is found that the address is in a If there is a defective memory area, the five least significant bits of the address are which also indicate the bit position of the correction bit in the associated correction bit word, transferred to the address register A1. In addition, the control unit also makes the Control bit BB set to 00. After the memory access has been carried out, this is in the incorrect data word in the data buffer register that coincides with the bit plane defect MBR, from where it is transferred to the data register R2. Now in the processor the address calculation for the correction bit word carried out, the memory access with This address is carried out and the correction bit word is loaded into the data register R1. The processor also obtains from the appropriate entry in the error table the address of the bit position of the bit plane defect and sets this in the address register A2 a. The address contained in the address register A1 is 21, that in the address register The address contained in A2 is 12.

The addresses contained in the address registers A1 and A2 are now decoded, the content of the 21st binary digit of the data register R1 on the data bus B1, and from there to the 12th binary digit of the register R2. accepted. The data register R2 now contains the corrected data word, which is now back in the data buffer register MBR is loaded, from where it can be taken over by the processor.

When transferring bytes, only the most # significant two bits of the address registers A1 and A2 are decoded, the addressed byte of the data register R1 is transmitted to the data bus B2, from where it is fed into the by the content of the address register A2 addressed byte of the data register R2 is accepted. This The process is schematic for the transfer of the byte between the binary digits 8 and 15 of the data register R1 and the binary digits 24 and 31 of the data register R2 indicated.

The bit field transfer unit can make more sense through various measures Way to be added. It is conceivable the unit with one two to four registers to equip extensive buffer memory for correction bit words. This allows the Access to several consecutive addresses, such as for example Running through instruction sequences # is the case, repeated memory accesses to obtain the corresponding correction bits, and thus the program run be accelerated.

The advantage of arranging the bit field transfer unit at the interface between the processor and the working memory lies in the fact that the defects in the processor and / or errors in data words caused in the memory during transfer via the interface corrected can be and that data words a defect before transfer can be adapted into the corresponding unit.

It is therefore also possible to use several processors at this interface, e.g. to connect channels or additional memory segments, their possible defects could also be corrected by the bit field transfer unit. The control the unit is expediently taken over by the control unit of the processor, the control via the memory buffer register MBR.

Claims (4)

Circuit arrangement for carrying out reconfigurations the hardware structure of a programmable digital computer when permanent Defects in memory and / or switchgear components on a reduced structure, in which the defective components are not used and their functions are similar intact components are transmitted, characterized in that a bit field transfer unit (1) that the bit field transfer unit is connected between the processor and the main memory (1) Essentially consisting of a bit, byte and half-word addressable first data register (Rl) of word length and a bit, byte and semi-word addressable second data register (R2) consists of word length, since, J the first and the second data register via data transmission paths (Bi to B7) are connected in such a way that each Bit, byte or half word can be extracted from the first data register (R1) and converted into a predetermined bit, byte or half-word position of the second data register (R2) can be used is, so that a first data word that is due to the use of one or more defective Circuits or memory elements contain faulty bits or bit fields Insertion of correct bits or bit fields in a second data word in error-free Bit or bit field positions are provided, can be completed, or that from a first data word before using derekter components with a Defect extracting coincident bits or bit fields in a second data word can be used in error-free bit or bit field positions. 2. Circuit arrangement according to claim 1, characterized in that the data buffer register (MBR) of the memory on the output side with the inputs of the first data register (R1) and with the inputs of the second data register (R2) is connected so that a data word from the data buffer register (MBR) is optional transferable to each of the two data registers (R1, R2) is, that the outputs of the second data register (R 2) with the inputs of the data buffer register (MBR) and the inputs of the memory address register (MAR) are connected so that a data word from the second data register (R 2) optionally into the data buffer register (MBR) or the memory address register (MAR) can be transmitted. 3. Circuit arrangement according to claim 1 and 2, characterized in that that the first data register (R 1) has a first address register (A 1) with decoding logic and the second data register (R 2) a second address register (A 2) with decoding logic is assigned that each of the two address registers (A 1, A 2) n binary digits and each of the data registers (R 1, R 2) has 2 binary digits, so that with the contents the address registers (A 1, A 2) each Rinarstelie of the respectively assigned data register (R 1, R 2) is addressable that at least one control register BB) on the input side via a data line (B 6) is connected to the control unit of the computer and from Control unit can be set, and on the output side to the control inputs of the first and second address registers (A 1, A 2) is switched so that over the same Addressing devices also have contiguous fields of 8 bits (bytes) and of 2 bits (iialbworte) are addressable so that the outputs of the least significant fl Binary digits of the data buffer register (MBR) via the data bus tB5) the corresponding inputs of the n binary digits of the first and second address registers (Al, A2) are connected. 4. Circuit arrangement according to claim 1 to 3, characterized in that that a first data line (B1) consisting of a conductor on the output side with each Binary digit of the first data register (Rl) is connected in such a way that the content an addressed binary digit of the first data register (R1) into the addressed Binary digit of the second data register (R2) can be transmitted that a second data line (B2> consisting of eight conductors on the output side with each of the 2n3 byte fields of the first data register (R1) and on the input side with each of the 2n 3 byte fields of the second data register (R2) is connected in such a way that the content of an addressed Byte field of the first data register (R1) into the addressed byte field of the second Data register (R2) can be transmitted, and that via a third data line (BB) consist of 2 conductors in the same way half-word fields from the first data register (R1) can be transferred to the second data register (R2).