DE2538362B2 - Input circuit for a comparator that works with hysteresis - Google Patents

Description

feeds (or removes) in such a way that the first differential amplifier (9, 6) flowing base current of the first transistor (19) has the same value as that when balanced second differential amplifier (2, 5) flowing base current of the third transistor (27).

2. Circuit according to claim 1, characterized in that the second current source (28, 51, 53, 49, 45; 28, 51, 53, 49, 69, 67, 45) has a further transistor (49) of the first conductivity type with an emitter circuit Forward current gain factor B \ and an additional transistor (45) of the second opposite conductivity type in common emitter circuit with emitter circuit _{forward current gain factor B 2} , the bases of the further and the additional transistor being galvanically connected, the collector of the additional transistor with> o the emitters of the third and the fourth transistor (27, 29) is interconnected and a current of the magnitude / 1 is fed to the emitter of the further transistor (49).

3. A circuit according to claim 2, characterized v marked, characterized in that the first current source includes a current mirror amplifier (28, 51, 21, 23) having input (28) and first and second outputs (the collectors of transistors 21 and 53), the first output is connected to the emitter of the first and the second w> transistor (19, 17) and the second output is connected to the emitter of the further transistor (49).

The invention relates to a circuit as it is assumed in the preamble of claim 1.

it "f" _J_. ■ * YY 11 nil.

9 1 1 1 ¥ I IT ilF ^ & T ^ fi On · "^ I τΛ I ■ *% *" Ί ^ l r% t "f» f \ I> ^ Λ v \ ^ f \ ψ ^ η I ' ll Π or

iiuUllg,> * I.IUV.II 111 wants UlIVJ UtIOUIUHI OVIIUIlUlIg several different transistorized differential amplifiers, namely those that are built with NPN transistors and those that are built with PNP transistors. The PNP transistors in integrated circuits are usually constructed using the lateral technology and the NPN transistors using the vertical technology. Integrated lateral transistors have significantly lower current amplification factors than integrated vertical transistors. There are therefore in a circuit with z. B. parallel signal paths, one of which via a differential amplifier with PNP lateral transistors and the other via a differential amplifier with NPN vertical transistors leads to the ratios in terms of base biasing or switching currents for the PNP transistors different than for the NPN transistors, so that one must reckon with asymmetries and, in addition, an error signal can occur due to different voltage drops at the internal resistance of the input signal source. Furthermore, since the transconductance g _{m of} a differential amplifier is directly proportional to its gain factor and is also proportional to the bias current supplied to the interconnected emitters of its transistors, the gains of the NPN and PN P differential amplifiers become different when their source currents differ.

So far, great efforts have been made to correct certain errors in transistor amplifiers caused by Changes in the base input current or the gain with the bias ratios or the Are temperature related. These problems have been addressed individually and resolved for individual amplifiers been. For example, US Pat. No. 3,530,391 describes a differential amplifier circuit which has such problems by means of thermal coupling of the individual transistors and independent setting options seeks to solve for bias, symmetry and reinforcement. The circuit has two independent of each other biased differential amplifiers, one with transistors that are complementary to the other is constructed. These two differential amplifiers are interconnected to form a single overall differential amplifier, which has a better common mode behavior and a higher stability of its output potential should show. The desired balancing of the base currents of the various Trans'storen are however, restrictions which are based on the discrete, non-integrated components are, and the balancing is furthermore due to the possibility of errors due to the numerous independent Adjustment elements difficult. Since the known circuit neither active bias circuits for the two base differential amplifiers, still active connectors between the bias circuits or automatic compensation measures are used for changes in transistor parameters For a satisfactory function it is essential that the PNP and NPN transistors are for each other are chosen to fit each other. However, there are monolithic integrated circuits Possibilities practically not.

In US-PS 35 51 832 a transistor differential amplifier is described, the base input currents with The help of complementary transistors are compensated, which are also like a differential amplifier are interconnected. The circuit is dimensioned so that in each case a compensation transistor Base current for one of the differential amplifier transistors

ren supplies so that the input signal source is unloaded However, changes in the transistor gain cannot be compensated for with this measure.

Finally, from US-PS 38 16 761 one of two Complementary differential amplifiers constructed comparison circuit known which hysteresis properties, thus showing a dead zone. Such circuits solve the problem of ambiguous or indeterminate output signals with certain input signal conditions. With soietien circuits, however, they already occur initially mentioned error signals due to different voltage drops at the internal resistance of the Input voltage source, which is derived from the different current amplification factors of the NPN resp. PNP transistors in connection with the bias currents of each differential amplifier pair result. measures to reduce the base input current differences for the two complementary differential amplifiers are missing here, instead the two differential amplifiers work with different bias currents (Emitter current sources), which at the same time stabilizes the gain factors.

The object of the invention consists in specifying measures to compensate for unequal gains or base currents of two complementary differential amplifiers in one working with hysteresis Comparison circuit. This object is achieved by the features specified in the characterizing part of claim 1 solved.

Through the invention, the base input currents of the two interconnected differential amplifiers are matched to one another, so that not only the asymmetrical load on the input voltage source when driving one or the other differential amplifier is eliminated, depending on the polarity of the input voltage, but also one transistor of the one differential amplifier at the same time The base quiescent current of the complementary transistor of the other differential amplifier connected to it supplies and thus the input voltage source is not loaded at all by the base currents. You can therefore also use a relatively high-impedance input voltage source without fear of errors. Another advantage of the invention is the equalization of the gains of the two differential amplifier trains by adding a PNP amplifier behind the NPN differential amplifier and an NPN amplifier behind the PNP differential amplifier. The operating currents of the NPN differential amplifier and the PNP differential amplifier can now differ, namely a factor is chosen which is proportional to the current gains β (in the basic emitter circuit) of their respective NPN or PHP transistors in order to balance the base input currents and thus making the transconductance gain of the two differential amplifiers unequal by the same factor. If, for example, lateral PNP transistors with lower amplification and vertical NPN transistors with higher amplification are used in an integrated circuit, then with cascade connection of the PNP differential amplifier with lower transconductance with an NPN amplifier stage with higher current amplification practically the same overall amplification results as with the cascade connection of the NPN differential amplifier with a higher transconductance with a PNP amplifier stage with a lower current gain.

Another feature of the invention is that Using active circuits to connect the bias circuits of the two differential amplifiers, so that their bias currents behave like the current amplifications measured in the basic emitter circuit of the NPN and PNP transistors. The advantage of this measure is that the desired cancellation the input base currents at the common input connection and / or the equalization of the overall gain of the two differential amplifier trains due to the self-balancing property of the active ones Bias circuit is maintained automatically.

Further developments of the invention are given in the sub-statements marked.

The invention is explained below with reference to the representations of exemplary embodiments explained in detail. It shows

F i g. 1 shows the circuit diagram of a comparison circuit designed according to the invention,

F i g. 2 shows the circuit diagram of a further embodiment of the invention and

3 shows a block diagram of a third embodiment the circuit arrangement according to the invention.

A comparator arrangement of the general type according to FIG. 1, but without the prestressing arrangement according to the invention, is described in detail in US Pat. No. 3,816,761.

The simplified voltage comparator 1 according to FIG. 1 includes a differential amplifier 9 and a differential amplifier 2. The differential amplifier 9 is equipped with NPN transistors 17 and 19 and in the following referred to as "NPN differential amplifier". The differential amplifier 2 is provided with PNP transistors 27 and 29 equipped and hereinafter referred to as "PNP differential amplifier". The prerequisites are all PNP transistors lateral transistors and all NPN transistors vertical transistors. The amplifier 2 receives a low-level reference voltage at its input 13, and the amplifier 9 receives at its input 11 has a high-level reference voltage. The connection 15 is the signal input to which the signal which is to be compared in its value with the high and the low reference voltage.

The NPN differential amplifier 9 contains NPN transistors 17, 19 and 21 and PNP transistors 23 and 25. The transistor 23 is connected as a diode and has its base and collector connected to the base of transistor 25 and the collector of transistor 17 and with his Emitter connected to a positive voltage source + V. The emitter of the transistor 25 is connected to the voltage source + V and its collector is connected to the collector of the transistor 19. The base of the transistor 17 is connected to the high reference voltage input 11. The base of the transistor 19 is connected to the signal input 15 and to the base of a transistor 27 of the PNP differential amplifier 2. The emitters of the NPN transistors 17 and 19 are connected to the collector of the transistor 21, the base of which is connected via a terminal 28 to a bias circuit (not shown in FIG. 1).

Dc PNP differential amplifier 2 contains PNP transistors 27 and 29 and NPN transistors 31 and 33. The transistor 31 is connected as a diode, i. H. interconnected with base and collector. This common Terminal is connected both to the collector of transistor 29 and to the base of transistor 33. The EiViiiici of the transistors 3i and 33! Attach to one

Reference potential point, for example ground, and the collector of transistor 33 is connected to the collector of the Transistor 27 connected. The base of the transistor 29 is connected to the low reference voltage input 13 connected. The emitters of the transistors 27 and 29 are connected in common to the current source 3.

In the amplifier 9, the operating currents of the transistors 17 and 19 are determined by the collector current of the Transistor 21 is determined. The transistors 23 and 25 are connected as a current mirror, so that they are active Form collector loads for transistors 17 and 19 or a current source.

In the amplifier 2, the operating currents of the transistors 27 and 29 are passed through the current source 3 certainly. The transistors 3i and 33 are connected as current mirrors so that they have active collector loads which act as a current sink for the transistors 27 and 29.

Two diodes 35 connected in series between the voltage source + V and the collector of transistor 19, 37 prevent the transistor 19 from becoming saturated.

A PNP transistor 39 is provided for gain compensation of the amplifier 9, the base of which is connected to the collector of the transistor 19 and its collector to the voltage comparator output Vo. A PNP current limiting transistor 41 has its collector connected to the emitter of transistor 39, its base to the current source 3 and its emitter to the voltage source + V.

For gain compensation of the amplifier 2, an NPN transistor 43 is provided, which is used as an amplifier in Emitter circuit with its base to the collector of transistor 27 and its collector to the Voltage comparator output Vo is connected.

The current source 3 includes FNP transistors 45 and 45 47 and N PN transistors 49, 51 and 53. The transistor 47 is connected as a diode and with his Emitter to the voltage source + V as well as the collector and base to both the base of the 4 « Limiter transistor 41 and the collector of transistor 49 are connected. The transistor 49 is with its base to the base of transistor 45 and its emitter to the collector of transistor 53 connected. The transistor 53 has its emitter connected to ground and its base connected to the Terminal 28 for a bias current arrangement (not shown in Fig. 1) is connected. The transistor 45 is with its emitter to the voltage source + V and with its collector to the interconnected Emitter of transistors 27 and 29 connected. The transistor 51 is connected as a diode and has a base and Collector connected to the bias terminal 28.

The operation of the voltage comparator 1 will be briefly explained below, while the by the Current source 3 effected base current equalization is discussed in more detail.

It is assumed that the connections 11 and 13 are supplied with reference voltages, namely the connection 11 a higher potential than the connection 13 turns transistor 39 on. The transistor 43 is then blocked, so that the output voltage Vb assumes a positive value which is slightly greater than + V. When the input voltage at connection 15 falls below the lower potential at connection 13, transistors 19 and 39 are blocked and transistor 2i is switched on. This in turn makes the transistor 43 conductive and clamps the output voltage V _{0 to} the ground potential. If, on the other hand, the voltage at terminal 15 is between the two reference voltage potentials (at terminals 11 and 13), then the transistors 19, 39, 27 and 43 are all blocked, and the output terminal formed by the junction of the collectors of the transistors 29 and 43 takes enters an indefinite state: this is called a dead zone.

If a current of size 2 I ₀ flows in the collector of transistor 21, an emitter current of I ₀ each flows from transistor 17 and from transistor 19 in the balanced state of this amplifier 9 (the same base input currents of the transi disturb 17 and 19), that the two transistors are the same in their geometry and have the same current gain factors (ß \ i and £ 19). If one assumes that the beta values are high, i.e. B + 1 is approximately equal to B , then the base currents (lev, / βΐ9 ^ of transistors 17 and 19:

/'IN THE

In the current source 3, the emitter current of the transistor 49 is equal to 2 I ₀ . The base current Im? this transistor is therefore:

/ '49

This base current flows from the base of the transistor: 45, so that its collector current (Ica5,

/.45 =

+ 2 / _{(1 ,; 43}

/ '40

The collector current of transistor 45 forms the operating current for amplifier 2. Since the gain factor /? 45 of PNP transistor 45 is lower than that of N PN transistor 49, the operating current flowing into the interconnected emitters of transistors 29 and 27 is less than 2/0 (see equation 3), i.e. h is less than the current flowing from the interconnected emitters of the transistors 17 and 19 of the differential amplifier 9. If the amplifier 2 is in the balanced state and if mar assumes that the current amplification factors of the transistors 21 and 27 are the same (as is the case with a monolithic integrated circuit), then these transistors have a base current (Ιβά Imi, each of:

'«29 -'« 27 - -; -

/ '29

7-. (4)

t '

In order to make the balanced base bias currents of the transistors 17, 19 equal to the balanced base currents of the transistors 27, 29, the beta current amplification factor /? ₄ s of transistor 45 of current source 3 is equal to the current amplification factors /? 27 and 029 of transistors 27 and 29, so that:

'«29 - '« 27 ⁼

/ '49

Furthermore, the current amplification factor ßw of the transistor 49 is made equal to the current amplification factors ß \ 7, j3i9 of the transistors 17 or. 19 so that

Equation (6) is obtained by substituting 0 ₄ <t for 0i7 in equation (1) taking into account the equality of the result with equation (5). Under these conditions is then

- / S29 = - i ^r fl27 = / ß! 7 = / fl19,

d. H. the base currents of the transistors 17, 19 in the balanced state of the amplifier 9 are from same amount and opposite polarity as the base currents of the transistors 27, 29 in the balanced State of amplifier 2. This results in the same but oppositely polarized signal currents at the high or low comparison level. If so, in other words, the input signal applied to terminal 15 is equal to the high reference voltage applied to terminal 11, then that of the signal source bias current drawn for transistor 19 is equal to that from the reference voltage source for biasing of the transistor 17 taken "reference current", and these currents are also of the same size, however of opposite direction to bias transistors 27 UBd 29 when the input signal is am Terminal 15 is equal to the low reference voltage lying at terminal 13. Furthermore, if the Inputs 11 and 13 are connected to each other, no base current to or from the. Signal source (not shown) in the balanced state, since the base current of transistor 19 is the base current of transistor 27 cancels.

A current limitation at the output of the voltage comparator 1 is given by the transistor 41. The limitation takes place when the emitter of the transistor 39 requires a current which is greater than 2/0. The transistor 41 then goes out of saturation and begins to develop a collector-emitter voltage drop Vce to limit the current.

In order to maintain an output balance between the amplifiers 9 and 2, a gain compensation must be provided at the corresponding outputs. A gain imbalance results from the fact that the source current of amplifier 2 differs from the source current of amplifier 9. The Gm value (transconductance) of a differential amplifier is directly proportional to the magnitude of the source current supplied to the amplifier. The gain factor of the amplifier, in turn, is G _n , directly proportional

If the operating currents for the NPN differential amplifier 9 and the PNP differential amplifier 2 were of such a size that the amplifiers 2, 9 had the same gain factors before setting to basic input current compensation, then a drop in the operating current supplied by the source for the amplifier 2 would result in a corresponding decrease in the gain of this amplifier. A gain compensation must therefore be introduced in order to equalize the gain factors between amplifiers 2 and 9 if comparator 1 is to be balanced. As already mentioned, gain compensation for amplifiers 9 and 2 is carried out by transistor 39 and transistor 43, respectively As an alternative to supplying the amplifier 2 with a current that is less than 2 / o, the amplifier 9 can be fed with an operating current of greater value and the amplifier 2 with a current ^r , 2 / o. However, this alternative is not as desirable as that of Figure 1 because the increased current can create accuracy problems, decreased reliability due to increased heat generation, and so on.

ίο The above-described method of NPN-PNP base current compensation in the balanced state can also be used with a voltage comparator 4 with NPN and PNP differential amplifiers 6 or 5 in a quasi-Darlington circuit, as shown in FIG. 2 shown. The 5 voltage comparator 4 corresponds to the voltage comparator 1 according to FIG. 1, but with the addition of NPN transistors 57 and 59 as collector-connected amplifiers to form quasi-Darlington circuits with the NPN transistors 17 or respectively. 19, addition of PNP transistors 61 and 63 as collector-connected amplifiers to form quasi-Darlington circuits with the PNP transistors 29 and 27, respectively, addition of a PNP transistor 55 to the PNP transistor 39 to form a Darlington circuit with this Transistor, addition of an NPN transistor 65 to form a Darlington circuit with the NPN transistor 43 and addition of a diode 38. Since the collectors of transistors 61,63,67 and 39 are connected to ground, these components can be vertical or Use lateral transistors. In order to ensure that * the base currents of the PNP and NPN Darlington differential amplifiers 5, 6 are made equal, the current source 3 according to FIG. Modify I by inserting the PNP transistor 67 and the NPN transistor 69, as shown in FIG. The emitter of transistor 45 and the collector of transistor 69 are connected to the voltage source + V. The emitter of the transistor 67 is connected to the base of the transistor 45, its collector to ground and its base to the base of the transistor 69. The operation of the comparator circuit according to FIG. 2 is essentially the same as that of the comparator circuit according to FIG. 1.
The comparator circuit according to FIG. 2 can be built in integrated form or with discrete circuit elements. The process of equalizing the base input currents of the NPN and PNP differential amplifiers 6 and 5, respectively, will now be explained. The NPN transistor 21 of the NPN differential amplifier 6 is

so biased that a source operating current of 2 k can flow through the interconnected emitters of the NPN transistors 17 and 19. As a result, assuming high beta values, so that B + 1 is approximately equal to B , the base current feg flowing into the NPN transistor 59 has the following magnitude:

where 019 is the beta current gain of the NPN transistor 19 and 059 is the beta current gain of the NPN transistor 59. When the amplifier 6 itself is balanced, the current gain factors 057.017 of the NPN transistors 57 and 17 are 0 ₅ 9 and 019, respectively. Therefore, the base input current Igst of the transistor 57 is / 559.

The transistor 53 of the current source 7 is biased so that it has a collector operating current of the

Size 2 / ο removes. When transistor 49 has a Beta current amplification factor jj «, then flows into his Base a base current / «9 of the following size:

'«49 -

As a result, the base current / «, 9 of the NPN transistor 69 has the following size:

/ '49 / '(i9

where / ta is the current amplification factor of the NPN transistor 69 is. The emitter current A * 7 of the PNP transistor 1 -5 67 is therefore

2 ! "Fa

I c 1.1 =

(10)

where /? 67 is the current gain of this transistor. The collector current is accordingly
of PNP transistor 45:

20th

2 /, j // (, 7 // 45

'c45 = ---; ■ - "■ .

/ '49 I '<> 9

(H)

where ^ 45 is the current gain of this transistor is. The source current supplied to the differential amplifier 5 is / ^ 5. To get the matched jo To make the base input currents of the amplifier 5 equal to those of the amplifier 6, the following relationships must be made the beta current amplification factors are given:

35

/ '49 = / '19 = ^: / '17 (12)

40

If these relationships of the gain factors exist, then we get:

(16)

/ '(W = / '59 = ■ - / '57 (13) / '■ (, 7 = / ν * == / 'M (14) / '45 = f'21 = ^: / '27 (15)

_ 2 / ,, / ^ ₂₇
'«■ 45 ~~ 7, ;;

/ '19 / '59

and the base current / «3 of transistor 63 is:

——

/ '19P59

9) ·

(17)

55

The corresponding base input currents in the balanced state of the NPN and PNP differential amplifiers 6 and S are therefore the same size and in opposite directions. This results in signal currents of the same magnitude and opposite polarity at the high and low comparison levels. In other words, when the input signal applied to terminal 15 is equal to the high reference voltage applied to terminal 11, that of the signal source for biasing the

Current drawn from transistor 59 is equal to that of the reference voltage source for biasing the transistor 57 taken "reference current", and these currents are just as large, but more opposite Direction for biasing transistors 63 and 61 when the input signal applied to terminal 15 is equal to the terminal 13 applied low reference voltage. Furthermore, if the inputs 11 and 13 are connected together, no power to or from the signal source when the input signal denotes has the same value as the voltage at inputs 11 and 13, since the base currents of transistors 59 and 63 cancel each other out.

F i g. 3 shows an embodiment of the circuit arrangement according to the invention, in which the first and the second differential amplifier 71 or 73 with transistors of the same or the opposite Line type can be equipped. If it is only desired, the sizes of the basic inputs 75 and 77 of the first differential amplifier 71 in the balanced state flowing base bias currents in the base inputs 79 and 81 of the second differential amplifier 73 in the balanced state flowing base bias currents to make the same, these inputs do not need to be in any way with one another to be connected for the invention to be effective. The output 83 of the first differential amplifier is also required 71 is not connected in any way to the output 85 of the second differential amplifier 73 be. A circuit arrangement of this type can be used, for example, to control the output current a bridge circuit as it is used for the measurement of heat, smoke and mechanical loads etc. is used, the bridge being hole value converters such as thermistors, ionization chambers, May contain strain gauges, etc. In such an application, the load on the Source are kept symmetrical by the amplifier input currents, so that when loaded by the one or the other amplifier the same errors result.

In the embodiment according to FIG. 3, a first current source 87 supplies an operating current of a given size to the first differential amplifier 71, while a second current source 79 supplies an operating current to the second differential amplifier 73, the size of which is equal to the operating current of the first current source 87 times the ratio of the beta -Current amplification factor of the second differential amplifier 73 to the beta current amplification factor of the first differential amplifier 71. When these currents are set to the stated ratios, the base bias currents of the amplifiers 71 and 73 have the same magnitude in the balanced state.

If it is desired to make the gain factors of amplifiers 71 and 73 equal to one another, gain compensation can be achieved by adding an amplifier 91 to output 83 of first differential amplifier 71 and adding a further amplifier 93 to output 85 of second differential amplifier 73. The design of the gain compensation amplifiers 91 and 93 is determined by the design of the corresponding differential amplifiers 71 and 73

For this purpose 2 sheets of drawings

Claims (1)

Patent claims: 1. Input circuit for a comparator operating with hysteresis, with a first differential amplifier, which contains a first and a second transistor of a first conductivity type, the interconnected emitters of which are connected to a first current source, and with a second differential amplifier, which has a third and a fourth transistor of the of the opposite, second conductivity type whose interconnected emitters are connected to a second current source, and with a common connection of the bases of the first and the third transistor to the input of the circuit, characterized in that the first and the second transistor (19 and VJ, respectively) have an emitter circuit forward current gain factor of B \ each, that the third and fourth transistors (27 and 29) each have an emitter circuit forward current gain factor of B2 Φ B \ , that the first current source (21, 51, 28) corresponds to the emitters of the first and second transistor (19, 17) a practically constant current of size / | removes (or supplies), and that the second current source (28, 51, 53, 49, 45; 28, 51, 53, 49, 69, 67, 45) is dimensioned such that it is the emitters of the third and fourth transistor (27,29) a practically constant current of magnitude