DE2524050C3 - Digital front / back link integrator - Google Patents

Description

55

The invention relates to a quantizing front / back path integrator in the preamble of Claim t specified type. Such a route integrator is known (book by W. Simon, "The numerical control of machine tools", Carl Hanser Verlac, Munich, 1971, p 52; DL-PS 72 289).

That in the aforementioned book by Simon The line integrator shown works with two phase-shifted pulse trains, which in the case of the optical Scanning of an impeller attached to a rotating part or the like by means of two side by side arranged light barriers are generated. The direction of rotation of the rotating part is made up of the two Pulse series recognizable by which of the two pulse series opposite the other pulse series leads, for which it is only necessary to determine whether during a pulse of the one pulse series a rising or falling pulse edge of the other pulse series occurs. To this end owns the known route integrator two signal branches, each equipped with a differentiator, which are each connected to one of two counting inputs of a counter via an AND element and each of the first of the two series of pulses are applied. The AND gates of the two Signal branches are also connected to a common third signal branch, which is connected to the second Pulse series is applied. When both series of pulses occur, only that AND element is used conductive that occurs during the application of a pulse of the second series of pulses that occurs during this pulse Occurring pulse edge of the first pulse series in the form of an output signal of the assigned differentiating element receives. Since one AND element is the up counting input and the other AND element is the Is assigned to the down counting input of the counter, the counter counts according to the (through the conducting AND element) ascertained direction of rotation of the rotating part upwards or downwards.

The same circuit principle as in the above-mentioned line integrator is also the basis of the line integrator according to DL-PS 72 289, which only uses bistable multivibrators instead of RC-Geder as differentiating elements, which allow the line integrator to be designed in integrated circuit technology. However, both line integrators are structurally relatively complex due to the need for two differentiating elements and, due to their counter's two separate counter inputs, have a comparatively high susceptibility to interference that is coupled, for example, from the counter's power supply to its counter inputs.

The object of the invention is accordingly to provide a route integrator of the type mentioned at the beginning to create which is more simply constructed and has a higher immunity to interference.

According to the invention, the object is achieved with a route integrator of the type mentioned at the beginning the features specified in the characterizing part of claim 1 solved.

Advantageous refinements and developments of the route integrator according to claim 1 are in the Claims 2 to 4 characterized.

The route integrator according to the invention has only a single differentiating element and a counter with only a single clock signal ip.gang. so that next to a structural simplification also a higher immunity to interference compared to those mentioned at the beginning State-of-the-art route integrators are guaranteed.

The invention is explained in more detail with reference to the drawings. It shows

Fig. 1 Pulse diagrams of the converters Wi and W ₂ , the signals "UP / DOWN" and "CLOCK" to be processed from them and the effects on the counter reading,

Fig. 2 is a basic functional diagram of the

Counter electronics,

F i g. 3 shows a possible embodiment of the in FIG. 2 drawn differentiation level,

Fig. 4 shows the practical structure of the entire pulse processing with only one integrated circuit.

An example of a pulse sequence which provides an arrangement of a mechanical transmitter with two mechanical-electrical converters corresponding to the above-mentioned conditions is shown in FIG. 1, lines a and b. The signal of the converter W, shown in line a, unlocks a counter as long as it is in the on status W, +. At the same time, the signal from W _{2 shown} in line b is used to initiate the counting up by one place with each of its positive flanks, as indicated in line b. With forward movement of the scanned medium, e.g. B. of the film, the signal from IVi has the effect that the counter is only _{unlocked during the positive edges of the signal from IV 2} , but is locked during the negative edges (values in brackets in line a), ie it is per division of the mechanical encoder counted up by exactly one.

Reading the timing diagram of Fig. 1 from right to left, you get the timing of the signals when the medium moves backwards. _{Since the positive edges obtained from W 2} when moving forward become negative edges when moving backwards, the counter is unlocked in this case precisely during the negative edges of the signal from W _2, i.e. it counts down.

Regardless of the counting direction, the switchover point is always in the same place, in other words, the counting is phase-locked and hysteresis-free.

Applied to the film frame count, it is possible to set this switching point exactly to the position of the To put a picture change, so that without exception always the picture number of the picture just viewed is displayed will.

It is particularly noteworthy that even with frequent changes de; Direction of movement, especially at small back and forth movements around the switching point, no "electronic slip" occurs Stumbling of the counter by one or more steps is therefore impossible.

The electronic circuit principle, which has the properties just described, is shown in FIG. 2.

An integrated up / down counter Z is used as the counter, which has a separate input »ENABLE«,>, UP / DOWN «and» CLOCK «. Can therefore be used z. B. a SN 74 LS 168 N ₁ SN 74 S 168 N, SN 74 LS 190 N or SN 74 190 N for decimal counting or an SN 74 LS 169 N, SN 74 S 169 N, SN 74 LS 191 N or SN 74 191 N for binary counting.

All of the counters mentioned can be cascaded and differentiated in the manner shown in FIG essentially in their cut-off frequency, the set inputs and the logical control values for the UP / DOWN input.

The signal from W can be given directly to the enable input of the first counter. The signal from W ₂ is suitably differentiated in stage D so that effective clock pulses for the counter or the counter chain are derived from both signal edges, as shown in FIG. 1 line d are marked. Furthermore, the signal from W _{2 is} passed to the UP / DOWN input of the counter via a timing element Ti (cf. FIG. 1, line c). The time delay of T · is dimensioned in such a way that it corresponds at least to the delay experienced by the clock signal in the differentiating stage D.

The differentiation stage D is shown in FIG. 3 expediently constructed so that the signal from W ₂ on the one hand directly, on the other hand via a timing element T ₂ and an inverter / to the two inputs of an exclusive-OR gate G is fed. This arrangement has the effect that with each level change of the signal from W ₂ the logic levels at the two inputs of G become the same for a short period of time, namely for the time which _{corresponds to the signal propagation time via the timing element T 2} and the inverter /. By the exclusive-or function of the output G of G takes for just this short time the status of the 0th This short negative pulse is used as a clock pulse for the counter.

The entire signal processing described can be implemented with the aid of a single integrated module. If exclusive-OR gates are used for the exclusive-or gate G, the inverter / and the row elements Ti and T ₂ , the entire signal processing according to FIG LS 86 N or SN 74 86 N).

In this case there is _{the possibility of inverting the logic status of the UP / DOWN signal via gate C 1} , so that the assignment between feed direction and counting direction can be reversed as required.

1 sheet of drawings

Claims (4)

Patent claims: 1. Quantizing forward / backward path integrator, in particular film frame counters for cutting and rewinding tables as well as film scanners and projectors, with an angular quantizer rolling on the path to be measured, consisting of a mechanical encoder with a regular division corresponding to the underlying resolution, which is divided into two , transducers which scan the pitch and whose effective scanning point spacing is smaller than the on-sector and also smaller than the off-sector of the mechanical encoder, whereby ^; the on-status of the output signal of one converter, which correlates with the one-sector, unlocks a forward / backward counter and the signal of the other converter increases the count of the counter by one with a positive edge during the on-status and with a negative edge during the On status lowers the count of the counter by one or vice versa, characterized in that an integrated up / down counter (Z) with separate inputs "ENABLE", "UP / DOWN" and "CLOCK" is used as an up / down counter, or a cascade of such counters (Z) is used, the signal of one mechanical-electrical converter (Wi) being given to the ENABLE input of this counter (Z) and the signal of the other converter (W ₂ ) on the one hand via a timer (Ti ) is fed to the UP / DOWN input of the counter and, on the other hand, to a differentiating stage (D) which generates effective CLOCK pulses for the counter (Z) from both signal edges. 2. Route integrator according to claim 1, characterized in that an exclusive-OR gate (G) is used as the differentiating stage, to whose two inputs the signal of the first converter is given via two different paths, a direct and a second via an inverter ( I) and a timer (T ₂ ). 3. Route integrator according to claim 2, characterized in that for the exclusive-OR gate (G) the inverter (!) And the timing elements (Ti and T ₂ ) gates (G \, G2, GS, G «) of a single integrated Quadruple exclusive-OR blocks can be used. 4. Line integrator according to claim 3, characterized in that the second input of the exclusive-OR gate (G ₃ ) used as a timing element (Ti) is controlled by an external logic signal.