DE2500057A1 - CIRCUIT ARRANGEMENT FOR STABILIZATION OF INTEGRATED CIRCUITS - Google Patents

Description

Circuits

The invention relates to a circuit arrangement for stabilization integrated circuits.

Monolithic circuits, such as those used in power amplifiers, sometimes require NPN and PNP bipolar transistors. The monolithic integrated circuit transistors are commonly fabricated in N-type epitaxial silicon disposed on a P-type silicon substrate. Vertical NPN transistors can be easily fabricated using P-type base diffusion in the N-TyD epitaxial layer and N-type emitter diffusion in the P-TyD base. The N-type epitaxial layer forms the collector electrode of one such NPN transistor. The substrate is in NPN

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Transistor arrangements used only for isolation functions. A P + type insulation diffusion generally surrounds everyone NPN transistor and forms an isolation.

PNP transistors, which are mostly difficult in the epitaxial layer of the N-type usually have either a lateral one or a vertical structure. Vertical substrate PNP transistors have collector electrodes formed from the P-type substrate material, and have base electrodes, which are formed of the N-type epitaxial material. The P diffusion, which is the base electrodes of NPN transistors forms the emitter electrodes of substrate PNP arrays. Thus, the collector material of the NPN arrangements forms the Base of substrate PNP arrays, and base diffusion for the NPN array forms the emitter electrode of substrate PNP arrays. Because the collector of a substrate-PNP arrangement is the substrate itself, the collector cannot be loaded or charged and must be connected to the negative supply. Consequently, such transistors can only can be used in an emitter follower arrangement.

Substrate Darlington arrangements have a driver transistor and an output transistor. The drive transistor has an emitter which is connected to the base of the output transistor, and has a collector, which is connected to the negative Ehergieversorgungsleiter. The base of the driver transistor is connected to the Darlington input or the driver terminal. The emitter of the output transistor is connected to the output terminal of the Darlington arrangement and the collector of the output transistor is connected to the negative power supply conductor.

The emitter current gain bandwidth product (f ^) formed as a monolithic integrated circuit substrate PNP transistors is low in typical cases and is for example in the order of 3 to 30 MHz. Consequently

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problems arise when attempts are made to use these transistors to be used in Darlington arrangements for conducting large currents through impedances which have capacitive reactances. if a purely capacitive load to the output terminal of a substrate PNP Darlington follower circuit connected, the reactance of the capacitive load shows the tendency to a negative resistance the input terminal of the Darlington pair. This negative resistance obviously tends to be an oscillation to create.

If a load resistor continues to be connected in parallel with the load capacitance is, then the impedance with which the input terminal of Darlington substrate PNP transistors is applied, of one negative resistance converted into inductive reactance. This inductance in connection with stray capacitances in the circuit at the input terminal of the Darlington arrangement, which from the collectors would evidently create a resonance circuit. Positive feedback through the resonance circuit also leads openly

visibly to an undesirable oscillation.

A known solution to overcoming this instability problem is to increase the base resistance or output substrate of the Darlington PNP array. This can be done by that a resistor is used to connect the emitter of the driver transistor to the base of the transistor from output. This resistance must have a large value, on the order of 10 kilo ohms. The base current of the 'output transistor must flow through this great resistance. Since the value beta of a PNP substrate transistor is relatively low, for example 20, the PNP substrate output transistor requires high Base currents to promote high load currents. Generate such base currents however, a large voltage drop across the base resistor. As a result, the load voltage cannot be driven into the negative supply potential because of the potential drop that occurs at the base

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Resistance occurs in series with the load.

Another known solution to the instability problem requires that a capacitor be placed between the input terminal of the Darlington arrangement and ground or a low level conductor. If this capacitor has a large value, on the order of 300 picofarads, its reactance will apparently mask the undesirable impedance reflected from the load on the input terminal of the Darlington arrangement. The disadvantage of this technique lies in the fact that the capacitor occupies a large part of the mold area, when it is formed on the wafer or the wafer. Integrated circuit capacitors have capacities of about 0.1 picofarads over an area of about 0.000625 mm (square mil). Thus, a 500 picofarad capacitor requires an area of about 1.8 mm (3000 square mils), which is an undesirably large area

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means. If the capacity is outside the disc / platelet

lines are required to make connections. Thus, external capacitors either add cost to the integrated circuit because they require additional lead connections or limit the electrical function that can be performed because leads are required for such functions. Furthermore , it is desirable, with a view to improved market opportunities, to reduce the number of external components that are required for the use of an integrated circuit.

The object of the invention is to create a circuit arrangement of the type mentioned at the outset which takes up particularly little space with an extremely high output.

The invention relates to a stabilization circuit which increases the effective value of a capacitor and the structure of such a capacitor. The stabilization circuit can have a transistor which has a base which is connected to the capacitor

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Sator is connected, and which has an emitter, which is connected to the point at which an increased effective capacity is to be created. According to a preferred Embodiment of the invention, the transistor is part of a bias network. The point or circuit node at which the increased capacitance is desired may be the Base electrode of the input transistor of a PNP substrate Darlington follower circuit which has input and output transistors.

A conductor is provided for the condensate build-up a first region of a semiconductor material of a first conductivity type is formed which has an insulation region and has a part formed by a base diffusion, which is used in the manufacture of NPN transistors. A second region of semiconductor material of a second conductivity type forms an integral part of the first region and forms one plate of the capacitor. This second one Area can be made by emitter diffusion, which used in the manufacture of NPN transistors. A layer of silicon dioxide covers and forms the second area the dielectric of the capacitor. A metallization layer Above the silicon dioxide forms the other plate of the capacitor, which is connected to the base electrode of the first transistor can be. The isolation area connects the second area or the plate to the substrate, which is a further connection to earth or a negative power supply terminal.

According to the invention, a stabilization circuit is thus created which increases the effective value of a capacitor, the invention also relating to the construction of the monolithic capacitor. The stabilization circuit comprises a transistor which has a base which is connected to the capacitor and which has an emitter which is connected to a

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Point is connected at which an increased effective capacity is to be created. The capacitor structure is suitable for to be used in monolithic integrated circuits which have diffused isolation areas. A first record of the capacitor is formed by a metallization layer, while the second plate of the capacitor can be produced by emitter diffusion in the insulation diffusion. One Base diffusion, which is conductively connected to the emitter diffusion and to the insulation diffusion, promotes the connection of the second plate of the capacitor to the substrate.

According to the invention, the essential advantage that an integrated circuit configuration is created can be achieved by which enables the effective capacitance of a small capacitor over its actual capacitance value.

Furthermore, according to the invention, the advantage can be achieved that a technique for increasing the effective capacity of a small Capacitor can be used to stabilize an otherwise unstable circuit.

The invention is explained below, for example, with reference to the drawing described; in this show:

Fig. 1. a circuit diagram of an amplifier circuit, which in a monolithic integrated circuit is used that uses a frequency stabilization circuit that has a Capacitor arrangement according to one embodiment of the invention can contain and

Fig. 2 shows a cross section through a semiconductor form, which is an embodiment of the capacitor arrangement according to the invention illustrated.

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In Fig. 1, a circuit diagram of an amplifier circuit is shown, which illustrates a way in which the Invention can be carried out. More precisely, the amplifier circuit / according to FIG. 1 has a positive power supply terminal 12 which is connected to a conductor 14, and a negative power supply terminal 16 connected to the negative power supply conductor 18 is connected. The reference voltage terminal 20 (V ^). Is designed such that it picks up a potential which lies between those potentials which the power supply terminals 12 and 16 are supplied. The reference voltage can be provided by any of a variety of known circuits. The input terminal 21 is designed such that it receives an input signal, which may be a sinusoidal signal, which has a tone frequency.

The transistor 22 has an emitter which is connected to the power supply conductor 14, and a base which is connected to the reference voltage terminal 20 is connected. The diode-connected transistor 24 has an emitter which is attached to the conductor 18 is connected, as well as a base and a collector which are connected in a known manner so that one Diode is formed. The collector and the base of the transistor 24 are connected to the collector of the transistor 22. Of the Transistor 26 has an emitter attached to the conductor and has a base which is bit connected to transistor 24. . ■

The bias network 28 includes a transistor 30, a Resistor 33 and a resistor 35. The resistor 33 is led from the collector to the base of the transistor 30, and the resistor 35 is led from the base to the backer of the transistor 30. The collector of transistor 30 is connected to the emitter of the signal amplifier transistor 32, the collector of which is connected to the conductor 14. The basis of the

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Transistor 32 is connected to input terminal 21 and to the base of NPN output transistor 34. The emitter of the Transistor 34 is connected to output terminal 41.

The terminal 37 of the PNP Darlington circuit 36, which the PNP substrate transistors 38 and 40 is also connected to output terminal 41. The base of the input transistor 38 is connected to the collector 27 of the transistor via the terminal 39. The collectors of transistors 38 and 40 are connected to the Power supply conductor 18 connected, and the emitter of the transistor 38 is connected to the base of transistor 40. The emitter of transistor 40 is connected to terminal 37.

In operation, the transistor 22 delivers a current via the diode 24, which the current source transistor 26 in the conductive state offset. The base of transistor 32 is through the signal driver circuit (not shown) biased such that transistor 32 operates as a class A amplifier. Consequently a constant current flows through the "N /" bias network 28. The base-emitter voltage of transistor 32 and the voltage on "Nv" network 28 bias the NPN driver transistor 3 ** · and the PNP-Darlington pair 36.

Show the positive amplitudes of an AC input signal the tendency to add to the positive bias supplied to the bias transistor 34 by the "NV" network 28 so that more current is sent to the power supply conductor 14 via the output terminal 36 and to a load, which has a resistance component or ohmic component 43 and a capacitive Component 42 may have. Alternatively, the negative amplitudes of the AC input signal offset the Darlington pair 36 in a more conductive state and put the transistor 34 in a less conductive state, see above that the voltage at the output terminal 41 shows the tendency to decrease in size or amplitude, so that thereby a decrease the instantaneous magnitude or amplitude of the voltage and the current caused by the electrical load.

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The problem of frequency instability is discussed below. Without the capacitor 44, the circuit operates properly under a purely ohmic or resistive load. Under a purely capacitive load, however, with the musty capacitor 42 from terminal 41 to the negative power supply conductor frequency instability problems arise. More precisely, when the amplifier input signal current at the terminal 21 changes, the current in the PHP substrate elements of the Darlington pair 36 increases and decreases, whereby f-. of the PNP elements is changed. When a certain bias voltage is present, the impedance with which the base of the PNP transistor becomes is applied, obviously to a negative resistance. This condition in conjunction with other impedances at the terminal or connection point 39 obviously creates a unwanted output oscillation signal on the electrical load. The circuit 10 then operates as a. Oscillator rather than an amplifier. If the electrical load has both the capacitor 42 and the resistor 43, then oscillation can also occur occur when the amplifier input signal passes the amplifier causes the load current to change, where f ^ - the PNP Darlington transistors in turn changes. this leads to the result that the impedance with which the base 39 of the PNP substrate element 38 is applied, which of the from ohmic and capacitive components combined load is reflected, begins to appear as inductive reactance. the Capacity at connection point 39 »which is due to the collector capacity of the transistor 26 and other capacitive effects produced, obviously combines with the inductance, so that a resonance circuit 'arises. The loop, which contains transistors 26, 30, 32, 34 and Darlington arrangement 36, oscillates obviously due to the feedback through the resonant circuit.

A well known technique for eliminating this vibration problem contains in it, a large capacity between the connection point

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and to arrange the alternating current earth which cover the impedance or would affect the impedance reflected by the Darlington assembly 36 such that it is no longer able to generate an oscillation. The capacity required for this can be in the order of magnitude of 300 picofarads, which in today's monolithic processes is a large range on the order of about 3,000 square mils (1.8 mm) if appropriate Arrangement on the same integrated circuit construction would be provided as the amplifier 10.

Circuit 10 does not require that a large capacitor be connected to terminal 39. More specifically, the capacitor 44 has a terminal 4-6 which is connected to the base of the NPN transistor 30, and has another terminal 48 which is connected to a point of low alternating current impedance, which may be the negative power supply conductor 18 · Die Terminal 48 could also be connected to the positive power supply conductor 14. In fact, the transistor 30 multiplies the actual capacitance of the capacitor 44 in such a way that there is an increased effective capacitance at the terminal 39, which is equal to the value beta of the transistor 30 multiplied by the capacitance of the capacitor 44 Capacity of 30 picofarads at terminal 39 is required to stabilize circuit 1o, then a capacitor is suitable which is connected to the base of transistor 3O and has a capacity of 300 picofarads, divided by the value beta of transistor 30 Since, according to standard procedures, transistor 30 has a value beta of about 100, a capacitor with three picofarads between the base of transistor 30 and the power supply conductor 18 delivers 300 picofarads between the terminal and conductor 18. Thus, the capacitor 44 requires instead of a plane of about 1 _t 8 mm (3OOO square mils) only an area of about 0.018 s® <3O square mils).

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The structure of the capacitor is explained below. As can be seen from the cross section of FIG. 2, the structure a P substrate 50 having a layer of N-type epitaxial semiconductor material 52 thereon. On the after the outside-facing surface of the epitaxial material 52 is a Layer of silicon dioxide 62 grown. A photolithographic one Technique is used to selectively open windows in the silicon dioxide layer through which diffusion P + isolation regions 54a, 54b and 54c, which differ from the Surface of the epitaxial material 52 into the substrate material 50 extend. The N-type epitaxial islands 56 and 57 are from Isolation diffusion area 54 of the P + type and from a substrate 50 surrounded by P-type. Then there is silicon dioxide in the openings grown through which the insulation diffusion regions 54a, 54b and 54c were generated. The silicon oxide layer is again selectively masked by photolithographic processes and etched to create openings through which base diffusion creates the region 58a which is the base electrode of the NPN transistor 30, furthermore the region 58b, which represents an integral part of the isolation region 54b, and finally the region 58c, which is the emitter region for the PNP substrate transistor 38. Another Diffusion forms the region 60a, which is the emitter of the NPN transistor 30 forms, furthermore the area 60b and the collector contacts within the (not shown) semiconductor material

Thereafter, an oxide layer 62 grows over the surface of the itself in this way resulting semiconductor structure, and be in it in turn, selectively openings are provided. Then there is a metallization layer applied and selectively formed to a box to the collector contact 64, the emitter contacts 66 and 72, the base contacts 68 and 74 and the short-circuit contact 70 to generate. The base contact 68 also extends over the silicon dioxide layer 62 and overlaps the area 60b of type N + to form the plate of capacitor 44, which

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is connected to the base of transistor 30. The metallization 70 shorts the N + type region 60b to the P type region 58b in such a way that the rectifying action which would otherwise be present therebetween is eliminated and the series resistance of the capacitor 44 is reduced. The metallization 72 provides an electrical connection to the emitter of the PNP transistor 38, and the metallization 74 provides a contact to the base of the transistor 38.

Insulation diffusion layers 54-a, 54b and 54-c can pass through the diffuse windows are formed in the silicon dioxide layer which are on the order of about 0.01 mm (four-tenths of a mil) wide. According to Pig. 2 exists for the isolation diffusion P +, the tendency to diffuse in a lateral direction at about the same rate as diffusion takes place in the vertical direction. Thus, if the epitaxial layer 52 has a depth on the order of 16 microns, then the outward diffusion of the isolation region P + is on the order of 16 microns. So take the insulation diffusions occupy a large part of the surface area of the semiconductor mold. The structure of the capacitor 44, which covers the insulation diffusion 54-b increases the required The surface is negligible because it takes up a surface area that would otherwise be due to the diffusion of insulation 54-b would be taken, which separates two active devices from one another, for example the transistor 30 and the Transistor 38. The isolation diffusion generally forms the anode of the reverse-biased diode array, which isolates the devices of the integrated circuit from one another.

An arrangement has thus been described above which is an improved one Figure 3 illustrates a monolithic amplifier integrated circuit comprising a PNP Darlington pair. The integrated circuit

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furthermore has a capacitor arrangement which has a minimum Occupies space and has a capacity which is equal to the value beta, multiplied in such a way that a effective value is reached, which is able to a. Stabilize pair of PNP substrate Darlington transistors Since the capacitor arrangement covers an insulation diffusion of the P + type that would otherwise be required, the capacitor arrangement decreases effectively does not take up any additional surface area on the integrated circuit wafer. Therefore, pro Disc or plate more integrated circuits are accommodated than if other capacitor arrangements were used. Thus, the described capacitor arrangement according to the invention serves to increase the yield and the costs of the integrated Lower circuits. Thus, the improved capacitor design and the technique of multiplying the value beta show the Trend towards using PNP substrate Darlington arrangements in circuits where this was heretofore practically impracticable because of the considerable size which of the required Frequency stabilization capacitor was taken.

Although the arrangement of the capacitor according to the invention is illustrated in relation to a particular monolithic amplifier configuration it can also be used in other monolithic arrangements. Although the beta multiplication of the effective capacitance value of the capacitor has been described on the basis of a special capacitor structure, the effect of the multiplication the effective capacity value also for other applications are used, in which the above-described Capacitor arrangement not available

- patent claims -

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Claims (10)

Claims 1.) Circuit arrangement with a capacitor arranged in a monolithic integrated circuit for use in an integrated circuit which has a conductive substrate with a layer of semiconductor material arranged thereon, one plate of the capacitor being connected to the substrate, characterized in that a metallization layer (68) is provided which forms a first plate of the capacitor and has a first and a second surface, that furthermore a layer of a dielectric material is present which has a first surface which is arranged adjacent to the second surface of the metallization layer, and further having a second surface, further comprising a first region (60B) of the layer of semiconductor material of a first conductivity type having a first surface which is disposed adjacent to the second surface of the dielectric material and a second surface, wherein the first region forms a second plate of the capacitor, further a second region (58B) of the layer of semiconductor material having a second conductivity type and a first surface adjacent to the second surface of the first region of semiconductor material, the second region of semiconductor material extending therefrom the first region of the semiconductor material extends to the substrate, and in that a second metallization layer (70) is provided which conductively connects the first region of the semiconductor material to the second region of the semiconductor material. 2. Arrangement according to claim 1, characterized in that the layer of dielectric material contains silicon dioxide. 509827/0730 3. Arrangement according to claim 1, characterized in that that the first area of semiconductor material with. a first conductivity type through an emitter diffusion is formed. 4. Arrangement according to claim 1, characterized in that that the second region of semiconductor material has a first part (54B), which by an insulating diffusion and further has a second portion (58B) that is associated with the first portion and with the first region forms an integral part, the second part being formed by a base diffusion 5. Monolithic integrated circuit arrangement which has a circuit part which at a circuit connection point has an impedance which tends to oscillate, a frequency stabilization circuit being present, characterized in that a capacitive device (44) is provided which has a first (6OB) and a second plate (68) and a predetermined capacitance, and which is conductively connected to an AC grounding point (50), and that a first electronic control device (28) is present which has a control terminal (46) which is connected to the second Plate (68) of the capacitive ELnrich- ^; device (44) is connected, which further has a first terminal, which is connected to the SohalteVerbindungspunkt (27), and which further has a second terminal, which is coupled to a power supply terminal (14), and that the first electronic control device is the default - The capacitance value of the capacitive device is multiplied in such a way that an effective capacitance is formed at the circuit connection point (27) which is greater than the specified capacitance value, so that the effective capacitance stabilizes the integrated circuit · ' 509827/0730 6. Arrangement according to claim 5 »wherein the capacitive element is an integral part of a monolithic integrated Forms a circuit comprising a substrate, characterized in that the capacitive element a metallization layer (68) forming the second plate of the capacitor, and a first and a second surface has that the capacitive element further comprises a layer of dielectric material which has a first surface adjacent the second surface of the metallization layer, and further a second Has surface that the capacitive element further comprises a first region (60B) made of semiconductor material having the first conductivity type, which has a first Surface located adjacent to the second surface of the dielectric material, the first area forms the first plate of the capacitor, and that the capacitive element also has a second Having region (58B) of semiconductor material having a second conductivity type and having a first surface, which is adjacent to the second surface of the first area of semiconductor material is arranged, wherein the second region of semiconductor material is arranged from the first region of semiconductor material extending to the substrate. 7. Arrangement according to claim 6, characterized in that that a second metallization layer (70) a connection between the first region of semiconductor material and forms the second region of semiconductor material. 8. Arrangement according to claim 7 »characterized in that that the second region of semiconductor material has a first part (54-B) which is formed by an insulating diffusion is formed, and that the second region of semiconductor material further comprises a second part (58B) which is an integral Forms part of the first part and the first region, the second part being formed by a base diffusion is formed. 509827/0730 9. Arrangement according to claim 5 »characterized in that the first circuit (28) has a transistor (30) having a base which is connected to the control terminal (46) is connected, which has an emitter which is connected to the first terminal is connected, and has a collector which is connected to the second terminal that the first Circuit (28) furthermore a first resistance element (33) has, which is arranged between the base and the collector of the transistor, and that the first circuit (28) further comprising a second resistance element (35) which is arranged between the base and the emitter of the transistor. 10. The arrangement according to claim 5 »characterized in that a second circuit (22, 24, 26) is provided which has a first electrode (12) which is connected to a voltage supply conductor, furthermore a control electrode (20) which is designed such that it biases with a constant amplitude receives, and further has a second electrode which is connected to the circuit connection point (27). 5 0 9827/0730 Blank page