DE2450921A1 - MOS-INTEGRATED CIRCUIT ARRANGEMENT FOR A PULSE GENERATOR - Google Patents

Description

MOS integrated circuit arrangement for a pulse generator

The invention relates to a MOS integrated circuit arrangement for a pulse generator using a flip-flop circuit with two mutually fed back switching transistors, with two control transistors each connected in parallel, and with two load transistors connected in series for this purpose.

If mechanical processes are to be controlled electronically, problems arise in particular in cases where impulses are involved low frequencies must be supplied and where the power loss must remain small. Low frequency pulses and steep edges are difficult to produce in terms of circuitry. This problem occurs in particular with electronic camera control where the available space is very small. The object on which the present invention is based exists in realizing a pulse generator in MOS technology, which generates pulses with low power dissipation Can deliver frequencies. The impulses should have steep edges. The pulse duty factor and the frequency should be variable within wide limits be.

To solve this problem it is proposed according to the invention in a circuit arrangement of the type mentioned that the The drain electrode of the first switching transistor is connected as the output of the flip-flop to the gate electrode of a fifth switching transistor is whose drain-source path is a connection point of the

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Circuit arrangement sit a reference potential connects and thereby parallel to a capacitor and in series with a current source through which the capacitor is blocked when the fifth Switching transistor is charged that further the gate electrode of a third Schalttraiisistor connected to the connection point is, wherein the source electrode is at reference potential and the drain electrode with the gate electrode of the first control transistor is connected at the output of the flip-flop and leads to a Yersorgungspotential via a third load transistor, and that the Gate electrode of a fourth switching transistor is connected to the connection point, the drain electrode being at supply potential and the source electrode is connected to the gate electrode of the second control transistor of the flip-flop and via a fourth load transistor leads to the reference potential.

With the aid of a circuit arrangement according to the invention, a pulse generator with a minimal space requirement can be implemented in MOS technology. The power loss is very low and can be kept extremely small by an advantageous embodiment of the invention, which consists in that the load transistors are MOS field effect transistors of the depletion type. In principle, the circuit arrangement according to the invention consists of a flip-flop which is controlled by two amplifiers with widely different response voltages. The switching states of the pulse generator in the intermediate areas are well stabilized by the flip-flop and the pulses emitted are shaped favorably with regard to their edges. A reliable oscillation of the pulse generator is guaranteed. The oscillation pulse has the same length as the following pulses. The current source can be implemented both by an ohmic resistor connected between the connection point and an operating voltage source and by a constant current source. The use of a constant current source has the advantage that the charging of the capacitor is very linear and

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thereby the trigger mechanism for the two amplifiers and the Flip-flop is extremely accurate. By changing the capacity, the feeding current and / or by dimensioning the fifth Switching transistor, the duration of a cycle, including the frequency, can be determined. Very low frequencies can be set will. If the integration of the capacitor with the required capacitance is difficult, the capacitor becomes externally connected to the named connection point.

Further details of a circuit arrangement according to the invention will be explained in more detail using an exemplary embodiment shown in the drawing. The 1 shows a circuit arrangement according to the invention with an ohmic Resistor as a power source and with an external capacitor and the

FIG. 2 shows the potential profile at five different ones shown in FIG Points A to E.

In Figure 1, a flip-flop including a first and second switching transistors 1 and 2. The source electrodes of the two switching transistors 1 and 2 are at a reference potential U _ss · The gate electrode of the switching transistor 1 is connected to the drain electrode of the switching transistor 2, the gate electrode of the switching transistor 2 the drain electrode of the switching transistor 1 is connected. A first load transistor 3 leads from the drain electrode of the switching transistor 1> from the drain electrode of the switching transistor 2 a second load transistor leads to a supply potential U ™ - .. The gate electrodes of the two load transistors 3 and 4 are each connected to the source electrodes. That of a control transistor 5 is parallel to the drain-source path of switching transistor 1 »that of a control transistor 6 is parallel to the drain-source path of switching transistor 2. The potential point at the drain electrode of switching transistor 1 is E, that at the drain electrode of switching transistor 2 with

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D called. The gate electrode of a fifth switching transistor 7 is connected to the potential point E. The source electrode of the switching transistor 7 is on reference potential U ^ g, the drain electrode is connected to an external connection point A. Furthermore, this external connection point A is connected to the gate electrode of a third switching transistor 8, the source electrode of which is at reference potential Ug ₃ and the drain electrode - potential point B · - leads via a third load transistor 9 to the supply potential Uj-jq. The gate electrode of the load transistor 9 is connected to its source electrode. The drain electrode of the switching transistor 8 - the potential point B - is at the gate electrode of the control transistor 5. Furthermore, the outer connection point A is connected to the gate electrode of a fourth switching transistor 10, the drain electrode of which is at supply _{potential U DQ} and its source electrode - identified as potential point C - via a fourth load transistor 11 leads to the reference potential U _ss . The gate electrode of the load transistor 11 is connected to its source electrode. The source electrode of the switching transistor 10 - the potential point C - is connected to the gate electrode of the control transistor 6. The external connection point A leads via an ohnischen resistor 12 to the supply _{potential U DD} and via an external capacitor to the reference potential

All switching transistors and control transistors are of the enhancement type,. all depletion type load transistors. At first it is left open whether it is a MOS field effect transistor with a p-channel or with an η-channel. The representation of the potential curves at points A to E according to FIG. 2 is based on the assumption that these are p-channel transistors and that the supply potential U ^ is negative compared to the reference potential U _ss .

The circuit arrangement according to FIG. 1 is composed of one Flip-flop, from two amplifiers controlling the flip-flop and off

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a controlled timer. The flip-flop comprises the two switching transistors 1 and 2, the two load transistors 3 and 4 and the two control transistors 5 and 6. The first amplifier includes the Switching transistor 8 and the load transistor 9 »the second, the switching transistor 10 and the load transistor 11. The timer includes the Ohmic resistor 12 and the capacitor 13 and is controlled via the switching transistor 7 by the flip-flop. The two amplifiers have a very different response threshold: the first speaks after exceeding the potential at point A. single threshold voltage,

the second after exceeding two threshold voltages, namely the of the two transistors 10 and 6.

These two potential thresholds are indicated by U and O in FIG Identification of a lower and an upper potential point. The potentials of the curve shown in FIG. 2 fluctuate between a zero value and a negative value. The two states are denoted by 0 and 1 in the language of logic.

In the idle state, the switching transistor 7 is blocked. When switching of the supply potential Ujyp. the capacitor 13 via the ohmic resistance t <2 charged. The potential at point A increases with it. When the first threshold voltage is exceeded, the switching transistor 8 is switched on at the lower switching point U. Previously, the potential at point B had the fourth logical 1, after the lower switching point U the value of logic 0. Before the lower switching point U, the control transistor 5 was due to the potential at Point B conducting from logic 1 and kept the potential at point E at logic 0. After the lower switching point U of transistor 8 the control transistor 5 is blocked and thereby releases the output of the flip-flop at point E. As soon as the potential at point A by further charging the capacitor 13 to twice the threshold voltage has risen and exceeds the upper switching point 0,

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the transistor 10 becomes conductive. This creates a potential of logical value 1 at point C. When this value is reached, the control transistor 6 conductive. This switches the flip-flop: the potential at point D receives the value logic 0, that at point E the value logic 1. The potential value at point E. of logic 1 causes the switching transistor 7 to be turned on. This means that the potential at point A cannot increase any further » The charge on the capacitor 13 can be discharged from the switching transistor 7. The potential at point A falls. After falling below after double the threshold voltage, the potential point C receives the value logic 0 by blocking the switching transistor 10 If the voltage falls below the simple threshold voltage - that is to say again at the lower switching point U - the switching transistor 8 is blocked again. The potential at point B changes from the value logical 0 to the value logical 1 and thus switches the control transistor conductive. This again causes the flip-flop to switch and thus an interruption of the discharging process of the capacitor 13, because the switching transistor 7 is blocked again. The cycle then begins all over again. The capacitor 13 is charged again. Switching the potentials at the two points D and E of the flip-flop take place with very steep edges. For example at the potential point Output pulses can be picked up for further use.

The time constant can also be increased by increasing the charge of the capacitor 13 reach. This happens, for example, when between the source electrode of the switching transistor and the potential point C at the drain electrode of the load transistor 11 another load transistor is switched, i.e. when the potential point C is at the divider point of a voltage divider made up of two load transistors lies. The size of the capacitor 13 can then be smaller.

3 claims
2 figures.

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Claims (3)

Claims MOS-integrated circuit arrangement for a pulse generator using a flip-flop circuit with two mutually fed back switching transistors, with two control transistors connected in parallel to them and with two load transistors connected in series, characterized in that the drain electrode of the first switching transistor (1) is used as the output of the flip-flop the gate electrode of a fifth switching transistor (7) is connected, whose drain-source path _{connects a connection point (A) of the circuit arrangement to a reference potential (U ss} ) and thereby parallel to a capacitor (13) and in series with a current source (12) lies, through which the capacitor (13) is charged when the fifth switching transistor (7) is blocked, that further the gate electrode of a third switching transistor (8) is connected to the connection point (A), the source electrode being at reference potential (U ₃₃ ) and the Drain electrode with the gate electrode of the first control ertransistor (5) is connected to the output of the flip-flop and leads via a third load transistor (9) to a supply potential (Uj-jyj), and that the gate electrode of a fourth switching transistor (10) is connected to the connection point (A), the drain electrode to supply potential (ϋ ™ 0 and the source electrode is connected to the gate electrode of the second control transistor (6) of the flip-flop and leads _{to the reference potential (U ss) via a fourth load transistor (11).} 2. Circuit arrangement according to claim 1, characterized in that that the load transistors (3, 4, 9 and 11) are from Verarraungtyp and that their gate electrode each with the Source electrode is connected. VPA 9/110/4080 609818/0593 -8- 3. Circuit arrangement according to claim 1, characterized in that that the current source consists of an ohmic circuit connected between the connection point (A) and the supply potential (UrnO) Resistance (12) exists. 609818/0593 VPA 9/110/4080