DE2365092A1 - Electronic monitoring cct. - monitors frequency and phase of clock pulse and blocks when faulty - Google Patents

Abstract

The circuit is assembled from fault free elements operating with a.c. signals, so that an acknowledgement signal sets a store, after which a clock pulse reaches the circuit output only if it appears during a time interval determined by two delay lines activated by a preceding pulse. The store is provided with a resetting device. It remains set so long as a negated clock pulse or the pulse determining the time interval is applied negated through an OR circuit to the resetting input. The construction plan is simple since both phase and frequency testing is carried out in one channel.

Description

Licentia Patent-Verwaltungs-GmbH Frankfurt / Main, Theodor-Stern-Kai 1

Kühn / ks ·. B 73/112

Electronic circuit for frequency and phase monitoring of a clock signal -

The invention relates to an electronic circuit for frequency and phase monitoring of a clock pulse.

When transmitting information, it is often necessary to have transmitting and receiving devices with a common clock signal to synchronize. For this purpose, the clock signal is often transmitted over large distances, and therefore frequency and Phase errors and thus ultimately errors in the transmission of information can arise.

This results in the need for such a clock signal monitor for frequency and phase errors. The circuit for monitoring the clock signal must in this respect be designed to be fail-safe that the clock signal in the event of a signal error in no case, i.e. also in the event of failure or Errors -von Bruielercenten, to the output of the circuit

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can get. When using components that process direct current signals, the risk of such a transmission of faulty clock signals caused by component defects is particularly great. In contrast, the risk of errors in the case of alternating current signals via modules processing input and output transformers is greatly reduced or even completely eliminated. The invention is therefore based on the object of creating a fail-safe electronic circuit for frequency and phase monitoring, avoiding the disadvantages mentioned, which does not allow the clock signal to be passed on in the event of frequency and phase errors or errors in the components in the circuit.

This object is achieved according to the invention in that the circuit is constructed from fail-safe components working with alternating current signals in such a way that a memory Sp is set by an acknowledgment signal Q, consequently each clock pulse T only reaches the output A of the circuit when it is in one of two time delay elements T, - and T ₀ set by the previous Tak ^v .i ν Is triggered time interval t2 occurs.

An advantageous embodiment of the invention provides that a memory Sp with reset priority is used and the memory Sp remains set as long as the negated clock signal T or o: i ■ ;. Signal'8 determining the time interval t2 is present negated via OR gates CL, O ₂ at the reset input R.

Another advantageous embodiment of the invention is characterized in that a first logical AND element U ^ .-. -, the clock signal T, the output of the memory Sp and that Signal 8 determining the time interval ti is present, accordingly upon fulfillment of the logical UliD-3ediiigung the aa output of the

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AND element. lL · pending clock pulse T a time delay element T ^ and thus a second AND element U ₂ triggers, whereby after completion one of the time delay element Tp generated and'by the previous clock pulse triggered time-delayed signal 6, which is via a third AND element U to the Duration of the clock pulse reduced, on the one hand via an OR element 0 "to the first AND element U" and on the other hand negated to the second AND element Uo, the time delay element T "is triggered again.

The advantages of the circuit, in addition to the fail-safe nature of the circuit, are the particularly simple structure, since phase and Frequency single-channel in contrast to other circuits can be checked and in-fact that the circuit only depending on a renewed acknowledgment signal can be restarted after a clock signal error has been detected. This means that there is no unwanted transmission of individual clock signals without prior elimination of the present error largely excluded.

An example according to the invention is given below of the drawings.

1 shows a block diagram of d ei> 6 rf indüng s according to the solution,

Fig. 2 shows the signal sequence of the clock monitoring with a perfect clock signal,

Fig. 5 shows the. Signal sequence if the pulse sequence of the cycle is too long,

Fig. 4- shows the signal sequence if the pulse sequence of the clock is too short,

Fig. 5 shows a signal sequence of the clock monitoring a clock pulse train with buckets multiples of the normal Working frequency.

To explain the circuit, the Taktübor -. 'Achung "with hornal sequence, with a taki impulse sequence,

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which is too long, with a clock pulse train that is too short and with a clock pulse train with a multiple of the normal ' working frequency.

1. Clock monitoring during normal operation

The normal course of the cycle is to be understood here as if the clock pulse follows the previous clock pulse within a prescribed time tolerance.

According to FIG. 1 and FIG. 2, it is initially due to the clock monitoring an acknowledgment signal Q briefly on. It will provided that the acknowledgment signal is generated in this way by a circuit that is also implemented using safe building block technology that, due to an error, there is never a permanent low signal Q is present. This acknowledgment signal Q is a Storage tank Sp with reset priority · on the one hand, direct and on the other hand supplied via the OR gate Oy, and Op.

, This sets the memory Sp; Signal 2 persists. An applied acknowledgment signal Q leads the AND element Uy. via the OR gate O _x , and via the memory Sp at the same time the L signal. If there is a clock pulse at U _x . The output signal 3 of the AND element Uy represents at the same time the output of the total clock monitoring. The signal 3 is fed to the timer Ty. ", Whereby the signal 4 is set at its output for the time of the time delay ^ t1 by the timer The signal 4- is applied to the -AND element U ₂ , equal to-

• at the same time as the signal 7 »which is at logic zero at this point in time. The condition of the AND element U2 is thus given, and the output signal 5 is applied to the time delay element T _P. At the AND element -U, the signal δ of the output of the delay element T ^ urä is thus the signal 5. That is the condition

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• of the AND element U, as long as the signal 5 which triggers the time delay t2 is still present. With 'the absence of' signal 5 i * the condition of the

'AND gate U, met, whereby the signal 7 on the one hand at the OR element O ^ and on the other hand at the .UND element Ug. The presence of the signal 7 at the AND element Ug is ensures that there is no further via the AND element Ug Signal can be forwarded. As a result, signal 5 remains at logic zero in each case, and the output of the

"Time delay ^{element Tg, ^ as} signal 6, is passed on via AND element U, as signal 7. Thus, the length of signal 7 is determined exclusively from the length of signal 6 reduced by signal 5 at the output of time delay element-Tg. Via the OR element O ^, the signal 8 is now again at the AND element U ^, identical to the signal 7. If another clock pulse T arrives for the duration of the set signal 8, the condition of the AND element U is , again fulfilled, since the memory Sp is set before \ Jle . The memory position of the memory Sp is alternately given by the negated clock signal (T) or the signal 8, both of which are fed to the input R of the memory via the OR gate Og This process is repeated

• as long as the clock signal T exactly in the signal 6 illustrated time interval t2 falls. This means that during the normal cycle at output A of the circuit, this is the case monitored clock signal T.

2. Clock pulse train too long

According to FIGS. 3 and 1, if the clock pulse sequence is too long, the clock pulse following a first clock pulse follows outside the time t2 described in point 1. The absence of the L signal β at the output of the time delay 3gliod.es T ₀ results in signal 7 at the output

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■ of the AND element TJ, also to'logic zero. As a result - the signal 8 at the output of the "OR gate CL" is set to logic zero, and every subsequent clock pulse

■ no longer finds the condition of the AND element U ,, Fulfills.

'Due to the absence of the L signal 8 at the output of the OR gate 0 ,. will 'the memory Sp at the next ■ Clock pulse reset. (Output logic zero). As a result, there is also no clock signal at output A of the circuit T more; the clock monitoring must be restarted via the Q acknowledgment signal.

^. Clock pulse train too short

If the clock pulse sequence is too short, according to FIG. 1 and FIG. 1 the following clock pulse to the previous one already in the time interval ti after signal 4. However, since at this point in time the memory Sp is only held by the negated clock signal, it is unconditionally reset as a result of a clock signal T now occurring. This is the condition of the AND element U _x for each subsequent clock pulse. no longer fulfilled. This means that no more clock pulse arrives at output A of the clock monitoring. As a result, the clock monitoring can only be started again via an acknowledgment signal Q-.

4. Clock pulse train with a multiple of the normal Working frequency

According to FIG. 5 and FIG. 1, the first clock pulse also arrives the acknowledgment signal Q to the AND gate U., and the clock, The process according to FIG. 2 is initiated as in Nc times. The next clock pulse, on the other hand, lags behind according to FIG. 4 in the time interval ti. signal

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However, this means that signal 7 at the output of AND element U, and also signal 8 at the output of OR element O ^, are set to logic zero with certainty. This means that the condition of the AND element U _x , is not given, and the clock cannot be passed on to the time delay element T ₇ . On the other hand, if the L signal is absent and the signal is present. T, the memory Sp will be reset with certainty via the ^ OR gate Op, since its R input is set. This is the condition of AND for all subsequent clock pulses -Level U ^ no longer fulfilled. Thus, the clock monitoring can only be started with a new acknowledgment signal Q.

Technical design

In the technical implementation, the clock monitoring circuit must be created from fail-safe Batx elements.

It processes dynamic signals. · The outputs of the components When errors occur, "always go to logical zero (error preferred position). The logical parallel but electrical inputs connected in series and driven by an output signal · obtained by the demolition of a Connection at any point at the same time zero signal. Fail-safe components required in the circuit Item were already in the applications P-1 953 715; P 1,950,330; Γ 1950 331; P 2 014 135 and P 2 014 110.

described.

It goes without saying that static signals can also be fed to the circuit, 'only it is necessary in this In the case of a conversion of the static signals into dynamic signals and vice versa at the output, the conversion of dynamic signals in static sis- nals. ·

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To display an error in the clock signal T, a control lamp was added to the circuit at signal 6 at the output of the time delay element T ₂ . According to signal 6, this lamp lights up as long as the clock signal is in normal operation. Only when the signal drops, the control lamp, which works according to the closed-circuit principle, is also switched off. A failure of the control lamp thus indicates an error in the monitored clock signal T or an error in the modules used.

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Claims (2)

-y- Li c ent ia Pat ent-Ve rwaltungs-GmbH Frankfurt / Main, Theodor-Ster-Kai 1 Kühn / ks' B 73/112 Claims π. / Electronic circuit for frequency and phase monitoring a clock pulse it, - characterized in that the circuit is made up of fail-safe components working with alternating current signals in such a way that a memory (Sp) is set by an acknowledgment signal (Q), and consequently only each clock pulse (T) sends the output (A) of the circuit achieved when it occurs in a time interval (t2) specified by two time delay elements (T ₁ and T _{2) triggered by the previous clock pulse.} ' 2. Electronic circuit according to claim 1, characterized in that a memory (Sp) with reset priority "is" used and the memory (Sp) remains set as long as the negated clock signal (T) or the time interval (t2) The determining signal (8 _{) is negated via OR gates (0 ^, O 2} ) at the Jerkset input (R). 509827 / 0A58 B 75/112 J. Electronic circuit according to claims 1 and 2, ' characterized in that the clock signal (T), the output of the memory (Sp) and the signal determining the time interval (ti) at a first logical AND element (U ,,) (8) is applied, so when the logical AND condition is met, the clock pulse (T) pending _{at the output of the AND element (U x .) Triggers a time delay element (T x} ,) and thus a second AND element (Uo) , whereby after the end of a delay element (To) generated by the Zeitvex ^ and triggered by the previous clock pulse time-delayed signal (6), das.über a third AND element (U ^) to the. Duration of the clock pulse ■ reduced, on the one hand via an OR element (O _x ,) to the first AND "element (U _x .) And on the other hand negated to the second AND element (U ₂ ), the time delay _{element (T x} ,) is triggered again. ' ^L \ -. Electronic circuit according to claims 1, 2 or 3,. ' characterized in that a control lamp (L) is connected to the output of the time delay element (Tp). 509827/0458 Blank page