DE2260389A1 - SAMPLE AMPLIFIER - Google Patents

Description

Advanced Memory Systems, Inc.

Sunnyvale, Santa Clara Ward, California (V.St.A.)

Sense amplifier

The invention relates to a sense amplifier with transistors of the same conductivity type and an output stage. The sense amplifier responds Differential input signal and has a single ended output.

Various logic circuits with conventional logic elements in each of these circuits are known which are used in digital systems. Such logic circuits include a diode logic, a resistor-transistor logic, a diode-transistor logic and a French-stor-transistor logic * There is also already a logic group _; which is usually referred to as the emitter-coupled locfik (ECL) wlid ·; Sometimes this logic v / t "; μ? η of the type _y : n..t ler ale 3üha 1. tEnnkt ions obeyed, also as Strocnmociealoylk. Lt-. to reject.,. The ECL-liOijik can generally aL ^ - Transistor lotj LJc "will be marked.

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PATENTANWÄLTE ZENZ & HELBER ESSEN 1, ALFREDSTRASSE 383 TEL .: (02141) 472087

whose transistors are not driven into the range of saturation, so that the problem of reverse inertia that typically occurs due to saturation in some other logic circuits is avoided. In addition, the emitter-coupled logic is characterized generally as current scarf t- logic of which are in typical operation "switches a substantially constant current between two paths in response to an applied at input voltage or difference voltage This large transitions are avoided on the supply lines, and also very fast logic elements can be implemented, since the current switching generally takes place with relatively small voltage differences. This means that the impedance associated with such circuits is very small in its characteristic design and leads to low RC time constants in the presence of element and lead capacitances.

The invention provides a high speed sense amplifier, which enables a monolithic "integration and consequently can form part of a memory circuit. This sense amplifier is because of its characteristically high Switching speed is particularly useful for ECL logic circuits, because the switching speed of each element is of considerable importance in such circuits Has. Therefore, the invention and also the known prior art are described below in particular with regard to the ECL logic described, this application is of course only given as an example, since the inventive Sense amplifier circuit can also be used with similar advantages in other types of logic.

Known sampling amplifiers have a differential or Differential input, whose two input connections e dLrect are connected to the base of an associated transistor, so that an initial differential gain is caused. Since the base impedance of a transistor is usually high, the input connections are also in t / pL design

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Resistance-coupled to a reference voltage, so that the RC time constant is primarily dependent on the value of the last-mentioned resistors and less on the base impedance of the transistors, _etc.

The above circuit can be operated at sufficient speed by changing the resistance values of the resistors be chosen relatively low for those applications in which the input differential current is sufficient to'einen satisfactory base voltage at the two input transistors to evoke. However, as the input current decreases, the resistance of the two resistors must increase be to a minimum value of the read differential voltage (typically approx. 200 mV) to be maintained ο Accordingly, in such an application, the input impedance must be increased considerably, resulting in much larger Response time leads. In order to obtain the high speed of such an amplifier that is possible in principle, it is necessary to the other parts of the memory circuit can be designed to develop an adequate input current to enable the the resistances lying on the base electrodes of the input transistors can be kept relatively small note that with integrated circuits there is a upper limit for the power that can be absorbed by the circuit. Therefore, in a memory circuit, the values of the Currents carried in the circuit itself decrease when the number of components (bits per module) increases. As a result the bit line currents must decrease with increasing capacity , whereby the response time of known sense amplifiers is increased. Also need more transistors for that Scan / write coupling electronics can be provided, though the storage capacity increases due to an increase in the number of storage columns, thereby increasing the total capacity at the input port of the sampling amplifier grows ο From this it follows that in known sampling amplifiers the storage capacity = did and / or the speed, due to a memory circuit of the aforementioned restrictions are limited or *, is.

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These known sampling amplifiers are a hit of the invention remaining problems largely resolved. Starting from a sampling amplifier of the type specified at the outset, suggests the invention for this purpose proposes that first and second Transistors with interconnected base electrodes are connected to a first terminal and have their collectors above first and second resistors in the output stage with a second terminal are connected that the collector of the first • transistor also with the collector of a third transistor and the collector of the second transistor with the Collector of a fourth transistor is coupled that the emitter of the first transistor to the base of the fourth Transistor, a third terminal and a first current source is connected, that also the emitter of the second Transistor is coupled to the base of the third transistor, a fourth terminal and a second current source, and that the emitters of the third and fourth transistor are interconnected and connected to a third current source with the output stage connected to the collectors of the first and second transistors and to their output terminal a compatible logic signal as a function of the difference signal between the first and second resistors developed.

The invention thus provides a high speed sense amplifier available for use with ECL-compatible, integrated memory components is particularly suitable. The sense amplifier is basically a two-stage amplifier with an input stage absorbing differential input currents and an output stage with ECL-compatible single-ended output ο The input stage is a low input impedance differential current amplifier and the output stage is differential controlled Current switch, which is typically coupled to a conventional single-ended ECL output follower is. The differential current amplifier that forms the input stage det, ensures a low input impedance even within

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PATENTANWÄLTE ZENZ 4 HELlER ESSEN 1, ALFREDSTRASSE 383 TEL .: (02U1) 472 (587

half of such circuits; which only supply a small input current «The response time is correspondingly short of the amplifier even in the presence of a relatively high Capacity at the input terminals due to a circuit connected to them ^

According to a further development of the invention, there is a blocking circuit provided, which is the output signal of the sense amplifier blocks regardless of the state of the input signals, without driving any of the active components of the amplifier into the saturation range, which results in a quick reset the lock state becomes possible. The sense amplifier circuit constructed according to the invention can be connected to either used with active or passive power sources and operated with a conventional 5 volt ECL supply voltage.

In the drawing shows;

Fig. 1 is a block diagram of a typical memory array; on the basis of which the use of the sense amplifier is described j and

Pig, 2 is a circuit diagram of a preferred embodiment of the new sampling amplifier.

In .Fig. 1 is a block diagram of one commonly used at a memory matrix used sense amplifier and coupling electronics «In the illustrated embodiment the memory matrix 20 is a 128 bit memory matrix consisting of 16 rows and 8 columns. By selection a row and a column over a not shown Circuit can each of the 128 bit memory spaces or «bursts for writing in or reading out by the scan / write coupling electronics 22 can be selected. The read / write coupling electronics is made by a buffer circuit and logic 24 controls which one is either a read or write operation controlling signal developed and in the event of a

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Write operation introduces data into the coupling electronics · If a read signal is present, a differential current output signal appears (the word output signal is understood in the general sense, whereby the positive current "outputs" are defined by the elements 126 and 128 in FIGS. 1 and 2) on lines 26 and 28 according to the logic state des via a row control line and a column control line selected memory location. The differential current is sampled and amplified by a sense amplifier, the sense amplifier generally having an output signal on line 32 that is compatible or compatible with the particular logic circuit used. As previously mentioned, the new sense amplifier shows an unusually high operating speed, which makes it particularly useful for the ECL logic becomes suitable. This is therefore the case with the exemplary embodiment described output signal appearing on line 32 is an output signal compatible with the ECL-Loglk.

A sense amplifier, such as amplifier 30, has an inhibit input and a blocking line 34, which is the output signal of the sampling amplifier blocks independently of the difference signal present on lines 26 and 28. In Fig. 1 is also shown in phantom is a capacitor on each of the input lines 26 and 28. These capacitors are not used as components in the circuit, but represent unavoidable capacitances between the conduction paths in the integrated circuit and in the substrate darο There is of course a certain capacitance between the two Lines 26 and 28, which, however, can be achieved by suitably arranging these lines in relation to one another and in relation to the substrate in FIG reasonable limits can be kept »

It should be noted that currents 126 and 128 in the lines 26 and 28, respectively, are shown as emerging from the sense amplifier 30. This direction of current is characteristic of the

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emitter-coupled logic, and the blocking inertia or response time of the sampling amplifier to the application of differential currents on lines 126 and 128 is determined primarily by the input impedance of the amplifier and the size of the capacitive load on the input line, internal or external, determined · In the particular application, for one Embodiment of the new amplifier was used is the operation of the scan / write coupling electronics 22 so provided that the output signal is during the reading process is in the true or correct state when a current 126 is present (e.g. when the voltage is on of line 26 is smaller than that on line 28) | it should be in the wrong state when a stream 128 is present, with streams X26 and 128 generally do not occur at the same time. When a lock signal is sent to the Line 34 is applied (typically during a write operation of the memory) becomes the output of the sense amplifier regardless of smaller currents on lines 26 and 28 (e.g. lower or signal level compared to Power source 152) set to the wrong state. Of course is the blocking inertia or «. Recovery time of the amplifier when the lock signal is disconnected essential parameter for such a sampling amplifier.

In Pig. Referring now to Fig. 2, a schematic diagram of the preferred embodiment of the new sense amplifier is shown is connected to a first supply voltage, referred to herein as VCC, and terminal 42 is connected to one second supply or reference voltage Vl, which is something never driger as VCC, and current sources 44, 46, 48, 50, 52 and 54 are each with an even lower supply · =. voltage connected, which is not designated »The current sources 44 to 54 can be either passive or active sources, i.e. each can be designed simply as a high resistance, or they can be constructed as a transistorized current source

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its to be an obviously higher impedance for the current and voltage drop than to be achieved by means of a resistor. Such active power sources are known and are therefore not described below. (In this context it should be noted that the term "current source" or "current sources" in the following in general Sense is used and denotes both current sources and sinks, depending on the type of line used for the construction of the amplifier used transistors. Albeit the preferred embodiment npn transistors and current sinks used, pnp transistors and current sources can be used to build a direct equivalent amplifier.)

The input lines 26 and 28 are the differential current input lines shown in FIG. The line 26 is with the Current source 50, the emitter of a transistor Q6 and the base of a transistor Q8. Similarly, the Line 28 to current source 54, the base of a transistor Q9 and the emitter of a transistor Q7 are turned on. The base electrodes of the transistors Q6 and Q7 are connected together and connected to terminal 42. The collector of the transistor Q6 is connected to the terminal via a resistor R1 40 and turned on to the collector of transistor Q9. Similarly, the collector of the transit port Q7 is coupled to terminal 40 through a resistor R2 and connected to the collector of transistor Q8. The collector of transistor Q8 is also connected to the collector of a transistor QlO connected, wherein the base electrodes of the transistors Q8, Q9 and QlO are connected and at the Power source 52 lie. The base of the transistor Q10 is connected to the dsm terminal 34, which is the output signal of the sampling · » The amplifier locks when a lock signal appears.

Furthermore, the base electrodes of the transistors are Q1 and Q2, respectively connected to the collectors of transistors Q6 and Q7,

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and the collectors of transistors Ql and Q2 are common at terminal 40. The emitters of transistors Q1 and Q2 are connected to current sources 44 and 48 and the base electrodes of transistors Q3 and ". Q4 connected the issuance, The transistors Q3 and Q4 are connected together and are connected to the current source 46. The collector of the transistor Q4 is connected to terminal 40 and the collector of transistor Q3 is through resistor R3 coupled to terminal 40 and connected to the base of a transistor Q5. The collector of the transistor Q5 is connected to terminal 40 and its emitter is connected to terminal 32 which is the single ended output of the amplifier represents.

The emitter-base junctions of transistors Q6 and Q7 serve as non-linear loads on the input current on lines 26 and 28. The mean input impedance of the amplifier is determined by the value or size of the Input current sources 50 and 54 and the mean value of the sample current applied to the input is determined. More precisely, because the impedance, i.e. the dynamic resistance of the emitter-base diode is inversely related to the emitter current the effective input impedance of the amplifier can be reduced by increasing the values of the current sources 50 and 54 will.

The transistors Q8 and Q9 and the current source 52 form a differential amplifier. Also in the preferred embodiment, the circuit is made in monolithic form, with all the transistors being diffused into the substrate at the same time. Therefore, the transistors Q6, Q7, QS and Q9 are essentially identical, so that the non-linear current ~ voltage - *> characteristics of their emitter-base junctions also match. Also, as can be seen, the bases of transistors Q6 and Q7 are connected together as are the emitters of transistors Q8 and Q9. In

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Similarly, the bases of transistors Q8 and Q9 are coupled to the emitters of transistors Q6 and Q7, respectively. Accordingly, the base-emitter voltage difference between transistors Q8 and Q9 must be equal to the base-emitter voltage difference between transistors Q7 and Q6. If the base currents are neglected, the non-linear characteristics of the emitter-base diodes increase one another resulting in the simple proportional relationship that the current in transistor Q6 divided by the current in transistor Q7 is equal to the current in transistor Q9 divided by the current in transistor Q8. The input stage current gain, expressed as (160-162), divided by the input current difference on lines 26 and 28 is approximately 1 + 152/2 150, where 152 is the current in the power source 52, and 150 is the current in the current source 50 (the current in the current source 54 becomes equal to that in the Current source 52 assumed).

In many applications, the new sense amplifier is not used with a true differential input * but a current in line 26 represents a true or correct state with a current of approximately zero in line 28, while a current in line 28 with a current of about zero on line 26 represents the wrong condition. In such a case, the gain of the input stage approximates 1 + 152 / (2 150 + I _in ) »where I _{in is} the current in input line 26 and 28, respectively.

The amplified currents 160 and 162 flow through resistors R1 or R2 and call a differential voltage between the bases the transistors Ql and Q2 emerge. These two transistors are connected to current sources 44 and 48 and act as emitter followers to control the base electrodes of the transistors Q3 and Q4. The emitters of the transistors Q3 and Q4 are connected together and are at the current source 46, whereby a differential current switching amplifier is formed, which the current

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the current source 46 either downward sends through the transistor Q3 or the transistor Q4, according to the present at the sense amplifier input signal * Therefore, when the current for the current source 146 flows through the transistor Q4, the resistor R3 is substantially de-energized ₉ and the base of Transistor Q5 is essentially at the positive supply voltage present at terminal 40. The transistor Q5 acts as an emitter follower, and when its base is at the positive supply voltage, e.g. the true or correct state, the output signal at terminal 32 is in the true or correct state (the output signal is then VCC - the voltage drop across the Base-emitter diode of transistor Q5). When the amplifier input transitions to the false state, transistor Q3 will be turned on and carry substantially all of the current from current source 146. Therefore, the voltage drop across resistor R3 will cause the base of Q5 to drop to the false state. The output voltage at terminal 32 is then VCC minus the voltage drop across R3 and minus the voltage drop across the base-emitter diode of Q5.

Transistor Q5 gives BZL compatibility, though different Output circuits apparently for use with the new sense amplifier and for making compatibility with other logic circuits are suitable. In a similar way Way can generally consist of the transistors Ql, Q2, Q3, Q4 and Q5 constructed entire output stage can be modified within the scope of the present invention.

The conventional ECL feed or supply voltage is approximately 5 volts * In the preferred embodiment the voltage Vl at the terminal 42 is set to a value to prevent the saturation of the transistors Q6 and Q7, which is approximately 1/2 volt lower than VCC. The resulting voltage levels on input lines 26 and .28 are reduced by a base-emitter voltage drop below Vl

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set, whereby saturation of the coupling electronics 22 (Fig. 1) is prevented. The most negative circuit voltage occurs at the emitters of transistors Q8 and Q9 and is two diode voltage drops below Vl or approximated to VCC - 2.1 volts. The remaining 2.9 volts voltage drop across the power source is large enough to sustain the Realization of the current sources 144 to 154 either as high resistance To enable resistors or transistorized current sources, as previously stated.

The amplifier described here enables high-speed current amplification of differential current signals on input lines that are heavily loaded with capacitance. In addition, the amplifier has excellent common mode rejection properties, it is quick and easy to disable, and highly emitter-coupled circuitry compatible. In this connection it can be seen that the transistor Q10 is essentially parallel to the transistor Q8 is so that a pending blocking signal at the terminal 34 switches the transistor Q10 through. Therefore, the mooring ensures The inhibit signal indicates that the current from current source 52 is not through transistor Q9, but through one or both of them of transistors Q8 and Q10 flows. This ensures that the output of the sense amplifier is in the wrong State is retained, regardless of the state of the input signals on lines 26 and 28 (provided that that both input signals are zero or small). It should also be noted that the maximum current through the resistance Q10 is equal to the current in the current source 152, so that a modulation of the transistor Q10 in the Saturation area is prevented. Therefore, there is only a minimal reset time or blocking inertia after removal of a blocking signal necessary to trace the output of the sense amplifier back exactly to the state of the input signal. Are there all current sources 44 to 54 selected so that they saturate one of the transistors in the circuit and thus long blocking delay times of the transistors in the saturation area

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impede. Of course, other blocking circuits can also be used For example, the transistor Q10 can be used instead of the circuit shown in FIG be connected with its emitter to the connection 26 and with its collector to the connection 40. In this circuit variant, the amplifier is quickly blocked, even if the Locking delay is significantly greater than that in the case of the one in FIG. 2 Locking circuit shown is. Similarly, you can other circuit variants, e.g. a replacement of the transistor QS by other circuits to improve the output compatibility with other logic circuits in the new sense amplifier.

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Claims (7)

PATENTANWÄLTE ZENZ & HELBER · ESSEN 1, ALFREDSTRASSE 383 · TEL.! (02141) 472487 Claims Sampling amplifier with transistors of the same conductivity type and an output stage, characterized that first (Q6) and second (Q7) transistors with common base electrodes on a first Connection (42) lie and their collectors via first (Rl) and second (R2) resistors in the output stage are connected to a second terminal so that the collector of the first transistor is also connected to the collector «ines third transistor (Q9) and the collector of the second transistor coupled to the collector of a fourth transistor (Q8) is that the emitter of the first transistor (Q6) is connected to the base of the fourth transistor (Q8), a third terminal (26) and a first current source (50), that the emitter of the second transistor (Q7) is connected to the base of the third transistor (Q9), a fourth terminal (28) and a second current source (54) is coupled, and that the emitters of the third and fourth transistor are connected together and are connected to a third current source (52), wherein the output stage (Ql, Q2, Q3, Q4, Q5) to the Collectors of the first and second transistors (Q6, Q7) is turned on and at their output terminal in dependence a logic-compatible output signal is developed from the difference signal between the first (Rl) and second (R2) resistors. 2. Sampling amplifier according to claim 1, characterized in that the first (50), second (54) and third (52) current sources are each designed as resistors, which with are connected to a fifth supply voltage terminal. 3. Sense amplifier according to claim 1, characterized in that the first (50), second (54) and third (52) current sources Each as an essentially constant current 309832 / 10SA PATENTANWÄLTE ZENZ & HELBER ESSiN 1, ALFREDSTRASSE 383 TEL.s (02141) 472687 supplying transistorized current sources are formed, which are coupled to a fifth supply voltage terminal are. 4. Sampling amplifier according to one of claims 1 to 3, characterized characterized in that a blocking circuit iait a sixth Terminal (34) is coupled and the output signal as a function of a pending blocking signal regardless of the state of the input signals at the third (26) and fourth (28) Holds connections in a predetermined logical state. 5. Sampling amplifier according to claim 4, characterized in that the blocking circuit is formed by a fifth transistor (Q10) of the same conductivity type as the first ^ second / third and fourth transistors (Q6, Q7 ₉ 08, Q9), the base of which is connected to the sixth terminal (34) whose collector is coupled to the collector of the fourth transistor (Q8) and whose emitter is coupled to the third current source (52). 6. Sampling amplifier according to one of claims 1 to 5, characterized in that the collectors of a sixth (QDj, · seventh (Q4) and eighth (Q2) transistor are connected to the second terminal (40), that the collector of a ninth Transistor (Q3) is connected to the second terminal (40) via a third resistor (R5) that the base electrodes of the sixth and eighth transistors (Ql, Q2) are coupled to the collectors of the first (Q6) and second (Q7) transistors are _t, that furthermore the emitter of the sixth (Ql) and eighth (Q2) transistors having fourth (44) and fifth (48) current sources and the base electrodes of the ninth (Q3) or "of the seventh <Q4) transistor are coupled, and that the emitters of the ninth and seventh transistors are connected together and are connected to a sixth current source (46), a tenth transistor (Q5) having its base connected to the collector of the ninth transistor (Q3) and its collector connected to the second terminal (40 ) turned on and its emitter is connected to a fifth terminal (32) * 3 0 9 8 3 2/1064 PATENTANWÄLTE ZENZ * HELBER ■ ESSEN 1, ALFREDSTRASSE 383 · TEL.ι (02141) 472687 7. sampling amplifier according to one of claims 1 to 6, characterized in that all transistors (Ql to QlO) npn translators are. 309832/1014