DE2134529A1 - PROCEDURE FOR ERROR DETECTION AND CORRECTION IN INFORMATION WORDS READ OUT FROM THE MEMORY OF A PROGRAM-CONTROLLED DATA PROCESSING SYSTEM - Google Patents

Description

Boeblingen, June 29, 1971 ne-sz

Official file number: New registration

Applicant's file number: Docket GE 970 007; GE 869 163

Method for error detection and correction in read out from the memory of a program-controlled data processing system Information words

The invention relates to a method for error detection and correction in the memory of a program-controlled data processing system read out information words from η bits, of which k are check bits that correct the correction of t errors and enable the detection of t + 1 errors.

The semiconductor memories used in modern program-controlled data processing systems have the necessary short access times, but they are not as reliable as the slower working magnetic core memory. That's why it must be ensured that errors are automatically corrected by an error detection and correction circuit. For this purpose, the information words to be stored are converted into an error-correcting code. The implementation takes place in the way that check bits are derived from the data bits to be stored according to certain rules, which together with the data bits get saved. When reading out a word secured against errors in this way, the test bits are again extracted from the data bits

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derived and compared with the read out check bits. The at Signals obtained from the comparison, called syndromes, are used to locate the erroneous bit of a Decoding circuit evaluated, which corrects the erroneous bit by inverting it (in a data bit modifying circuit) causes.

The more data bits an information word contains and the more errors should be automatically correctable, the more check bits must be added to the word for error correction purposes. The amount of memory required to store the check bits represents a noticeable additional effort with which the automatic error correction has to be bought. For cost reasons one tries to keep it as low as possible. It is therefore advisable to convert the information words into a code, which allows the automatic correction of a single error and the detection of a double error. Put that into one Code, which also allows double errors to be corrected, differs in practice because of the additional check bits required for this usually off.

There are two types of monolithic semiconductor memories Errors on. The first are permanent errors; H. Errors caused by constantly defective storage elements are. These errors can therefore be reproduced. The second type of error form the so-called sporadic errors. This is the term used to describe errors whose cause only lasts for a short time, e.g. B. in the form of a glitch , is present during a write or read process and then disappears again. Therefore, sporadic errors are in which a distinction is made between sporadic write and read errors, not reproducible.

Due to the possibility of sporadic failure grows with monolithic Save the likelihood of double faults occurring. Becomes one when reading out a word If double errors are displayed, the data processing system must

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Docket GE 970 007; GE 869 163

■ " 3 ^mm

being stopped. The maintenance technician must be called with the help of test programs the double fault, its presence yes only indicated, it is localized and has to be eliminated by exchanging any components.

The disadvantage here is that the data processing system up to The arrival of the maintenance technician stands still.

Studies have shown that double faults are very often the result of a combination of a permanent fault with a sporadic one exist. If a memory is organized in such a way that each bit of a word is on its own semiconductor chip, the probability that a double error was caused by two sporadic writing errors is negligibly small.

The invention is based on the object of preventing a data processing system from coming to a standstill when a due to the code properties to avoid recognizable, but no longer correctable multiple errors. The said task will by a method for error detection and correction in from the memory of a program-controlled data processing system read information words from η bits, of which k check bits which enable the correction of t errors and the detection of t + 1 errors, solved, which is characterized by is that to correct t + 1 errors, at least one of which is a so-called permanent error, i. H. one, whose The cause is a permanently defective storage element, first of all the permanent error or errors in a special test procedure of the memory location, when reading it out, the multiple errors that were uncorrectable due to the code properties were found was localized and corrected and the information word thus obtained after passing through a known error correction circuit is transmitted to the processing unit.

209884/1119

Docket GE 970 007; GE 869 163

According to a further feature of the invention, after t + 1 has been indicated by the error correction circuit, due to the code properties no longer correctable errors the selected storage space to eliminate so-called sporadic read errors, d. H. of errors, the cause of which is only briefly present during a reading process and which are therefore not reproducible are read out again.

The special test procedure for the localization and correction of the permanent under the t + 1 errors consists of the following steps:

a) a data pattern consisting of n-k bits is fed to the check bit generator of the error correction circuit, at in which the first bit has the binary value "1" and the remaining bits have the binary value "0";

b) In this data pattern, the check bits are calculated in a known manner, with the data pattern in the faulty one Storage space is stored, read out again and fed to the error correction circuit, which consists of derives test bits from the read out data pattern, compares them with the stored ones and delivers a signal, that indicates either correctable or uncorrectable errors or freedom from errors;

c) the signal indicating the correctable error is sent to a counter and the series input of an n-k stage shift register supplied, the content of which is shifted by one level after each supplied signal;

d) the check bit generator now receives a further data pattern supplied, in which the binary value "1" is shifted by one place compared to the previous data pattern is;

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Docket GE 970 007; GE 869 163

e) steps b to d are repeated until each data bit memory element of the selected memory location once the binary value "1" was offered;

f) according to the n-k output signal of the error correction circuit the counter reading of the counter and / or the content of the shift register is used to localize the error and correction evaluated.

In the following, the method according to the invention is explained together with the description of an exemplary embodiment Circuit for carrying out the method explained in more detail in conjunction with the drawings. Of these shows:

Fig. 1 is a block diagram of a circuit for performing _v out the method according to the invention,

Fig. 2 shows a more detailed representation of the additional

Correction circuit and the circuits for querying the counter readings and the content of the Shift register according to FIG. 1,

Fig. 3 is a code table for an automatic

Correction of single errors and the recognition of uncorrectable double errors modified 22/16 bit Hamming code,

Figs. 4 to 8 tables of the error correction circuit

when carrying out the method according to the invention generated signals about the presence of single and double defects as well as freedom from defects for different types of double defects.

For the description of the invention it is assumed, for example, that a memory location comprises 22 bit positions. the Bit positions D 1 to D 16 are used to receive data bits and

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Docket GE 9 70 007; GE 869 16 3

the remaining six bit positions P 1 to P 6 store check bits, correct individual errors and identify them of double faults.

In Fig. 1 is the block diagram of an arrangement for implementation of the method according to the invention. The outputs of a semiconductor memory 1 are identical to that of the error correction circuit FKS 3 associated 22-stage register FKS and on the other hand with an also 22-stage auxiliary register HR 4 connected. The outputs of the auxiliary register 4 lead to one Correction circuit KS 5 consisting of 22 EXCLUSIVE OR gates,

™ whose second inputs are described in more detail later Control lines 6 are connected. The outputs of the correction circuit KS 5 are via a multiple switch U 7 with two Switch positions B and C in its switch position B can be connected to the 'error correction circuit FKS 3'. In the switch position B of the multiple switch U 7, the outputs of the register FKS 2 are connected to the error correction circuit FKS 3. In addition to the_ outputs for the corrected data, the error correction circuit 3 also has an output EF at which a signal EF occurs in the event of a single error. The exit EF of the error correction circuit FKS 3 is equipped with a counter Z 9 and the series input of a 16-stage shift register SR 10 connected. The eight output lines of those Bit positions which, according to the code table according to FIG. 3, are assigned to a check bit P lead to those which are not shown in detail Addressing circuits of a read-only memory FWS 11 to FWS 17 assigned to the relevant test bit. The output of each Read-only memory FWS is connected to the second input of the EXCLUSIVE OR element of the in Correction circuit KS 5, shown in greater detail, is connected to FIG. Also, as this figure shows, the two outputs are each Stage of the shift register SR 10 via an AND circuit 18 or 19, the outputs of which lead to an OR gate 20, the outputs with the second inputs of the EXCLUSIVE OR gates of the correction circuit KS 5 assigned to the data bits D 1 to D 16

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Docket GE 970 007; GE 869 163

2134528

are connected. The second inputs are the ones with the regular outputs the AND elements 19 connected to the shift register stages D 1 to D 16 are connected to the output of an OR element 21, which then emits an output pulse when the number of individual errors counting counter Z 9 either the counter reading 1 or 2 has reached.

The second inputs of the AND elements 18 connected to the complementary outputs of the shift register stages D 1 to D 16 are all connected to an OR gate 24, the first input of which is connected to an AND gate 25, which then has a Emits an output pulse when the counter Z 9 has the count 14. The second input of the OR gate 24 is with one AND gate 26 connected, which emits an output pulse when the counter Z 9 reaches the count 15.

The meaning of the counter readings will be explained later. They are determined with the help of the connected to the outputs of the counter Z 9 AND elements 22 (counter reading 1), 23 (counter reading 2) as well as 25 (counter reading 14) and 26 (counter reading 15).

If, when reading out an address A, the error correction circuit indicates the presence of a double fault, the following causes for the double fault are conceivable:

1) The storage space A has te learn two permanent defective Save au f j

2) the memory location A has a permanently defective memory element, which causes the first error of the double error because it can only store one, but not the desired binary value, the second error is a sporadic write error;

3) The memory location A has, as under 2), a permanently defective one Storage element showing the first failure of the double failure

209884/1119

Docket GE 970 OO7; GE 869 163

- 8 caused, the second error is a sporadic read error;

4) 1 the display of a double fault is caused by a sporadic typing errors present during the writing of the word and one sporadic typing error occurring during reading Read error ;.

5) the display of the double error is caused by two sporadic read errors;

6) the display of the double error is caused by two sporadic writing errors.

In order to eliminate the influence of sporadic reading errors on the display of a double error, after such a display the selected memory location is read out again. This means that in the aforementioned cases 3, 4 and 5, the double error and do not apply the still existing individual error is automatically corrected in a known manner by the error correction circuit.

In cases 1, 2 and 6 it is also after reading out again of storage location A still has a double error display. It was mentioned earlier that the probability of the simultaneous occurrence of two sporadic typographical errors in one word is negligible. Thus, the case can 6 remain out of consideration. Practically only cases 1 and 2 remain as those that also exist after the renewed Reading of the memory location A still show a double error display. What these cases have in common is that at least a double fault fault is a permanent one.

According to the invention, the one or more permanent faults with the aid of a special test method in which one Sequence of special data patterns is used, localized and corrected and the then still existing individual errors in known

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Docket GE 970 007; GE 869 163

ter way automatically corrected by the error correction circuit.

If a double error display is still present after the second readout of a memory location A, the central unit performs the data processing system to locate the faulty bits, the test method described below with the memory location by: In the example chosen, in which the word read out contains 16 data bits, the test procedure consists of 16 steps. In step 1, that in the error correction circuit a first data pattern consisting of 16 bits D 1 to D 16 is supplied by the central unit, in which the bit D 1 has the binary value "I" and the remaining bits D 2 to D 15 have the binary value "0". Together with the six check bits P 1 to P 6 generated by the check bit generator, the Data bits D 1 to D 16 are stored in the address of the memory 1 in which the word containing a double error was stored. The stored word is then read out again and fed to the error correction circuit FKS 3. In it become out The check bits P 1. to P 6 are derived from the read out data bits D 1 to D 16 and with the stored check bits P 1 to P 6 compared. Depending on the comparison result, the error correction circuit supplies an output signal "No error (KF)", "Single fault (EF)" or "Double fault (DF)". The output signal "individual error" is fed to the counter Z 9. aside from that the signal "single error" is sent to the serial input of the shift register SR 10 supplied, the content of which is shifted by one level after each test step has been carried out.

In step 2 the check bit generator is the error correction circuit FKS 3 is supplied with a second data pattern consisting of bits D 1 to D 16. While with the first data pattern only that Bit D 1 had the binary value "1", it now only has bit D 2. All other bits have the binary value "0". The check bit generator the error correction circuit FKS 3 calculates again in accordance with the selected code (Fig. 2) the for the second data

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Docket GE 970 007; GE 869 163

Pattern D belonging test bits P 1 to P 6, which are stored again in address A of memory 1 together with the data bits from which the word containing the double error was read. The stored word is then read out again and the error correction circuit FKS 3 supplied. This again forwards the check bits from the read out data bits D 1 to D 16 P 1 to P 6, compares them with the stored test bits and again delivers an output signal that either does not have an error, indicates a single fault or a double fault.

In step 3, bit D 3 indicates that of the error correction circuit ^ supplied data pattern has the binary value "1", while the remaining 15 bit positions all have the binary value "0". The data pattern is processed in the same way as it is in the steps 1 and 2 was the case. A result "individual error" is fed back to the counter Z 9 and the shift register SR IO, whose Content was moved back one level before.

In each of the 16 steps for localizing the error, the binary one is in that of the error correction circuit FKS 3 supplied data pattern at a different bit position. This is always the bit position that follows the one in which the binary "One" was on the previous data pattern.

After the 16 steps, each bit position is the faulty memory location with the address A the binary value "one" has been offered once and in the shift register there is a certain binary value Ones (single errors) and zeros of existing patterns are saved.

In the earlier mentioned case 1, in which the double fault occurs through is caused by two permanently defective storage elements, a distinction must be made between the following options:

a) two data bits are incorrect;

Docket'GE 970 007; GE ff69 T.5 J ''' ³

OHiQiHAl INSPECTED

b) a check bit and a data bit assigned to it are incorrect;

c) a check bit and a data bit not assigned to it are faulty;

d) two check bits are incorrect.

In case 2, in which one of the two errors is a permanent and the other is a sporadic typo, a distinction must also be made between the following possibilities:

a) of two data bit errors, one is a sporadic one Spelling mistake;

b) a double error consisting of a data bit error and a check bit error is the data bit error a permanent one;

c) a double error consisting of a data bit error and a check bit error is the check bit error a permanent one;

d) of two check bit errors, one is permanent.

In the table of Fig. 4 are those from the error correction circuit signals delivered during the individual test steps 1 to 16 compiled, which are generated for the case that the memory elements for storing the data bits D 5 and D 10 are permanently faulty.

In the top line of Table 1, the two faulty ones are on the left Storage elements indicated, in this case the storage elements D 5 and D 10. To the right of this are the numbers of the test steps listed. In the second line of Table 1, it is indicated on the left that the two faulty memory elements can only save the binary value "0". To the right of it are the signals delivered in this case by the error correction circuit after the individual test steps are listed. the

Docket GE 970 007; GE 869 16

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The next lines of the table indicate the signals supplied by the error correction circuit after the individual test steps for the case that the memory element D 5 can only store the binary value ¹¹ O "and the memory element D 10 can only store the binary value" 1. The next line applies to the opposite case, while the last line specifies the signals of the error correction circuit, which delivers them after the individual test steps when the faulty memory elements can only store the binary value "1".

The table according to FIG. 4 shows that when two data bit errors are present, the counter Z 9 after the 16 test steps have elapsed has one of the following counter positions, depending on which binary value the two defective storage elements D 5 and D 10 are still can save:

D 5 D 10 Z 9

0 0 2 0 1 , 14 1 0 14th 1 1 2

These counter settings are used to locate and correct the incorrect bits. For example, saves that Storage element D 5 only has the binary value "0" and the storage element D 10 only has the binary value "1", so, as can be seen from the table according to FIG. 4, after the 16 test steps the counter Z 9 shows the counter reading 14. The steps 5 and 10 of the shift register SR 10 corresponding to the erroneous bits, the yes only the signals indicating a single error are fed, have the content "0", while the remaining stages all the Have content "1". When the counter reading is 14, those are connected to the complementary outputs of the shift register stages AND elements 19 prepared. Since only the complementary outputs

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of the shift register stages 5 and 10 have high potential (storage of the binary value "0"), only those connected to them will be AND gates 19 switched through. Therefore, in the correction circuit KS 5, which consists of EXCLUSIVE OR gates, only the bits D 5 and D 10 are inverted and thus corrected.

Then the multiple switch U 7 switches to the switch position C um, the word stored in the auxiliary register HR 4 and corrected by the correction circuit KS 5 runs through the error correction circuit FKS 3 and becomes a processing unit from there transfer. The multiple switch U 7 then switches back to switch position B.

Table 5 summarizes the signals supplied by the error correction circuit during the individual test steps 1 to 16 for the event that the storage elements D 1 and P 1 cause the double error. In this case it should be noted that the erroneous data bit D 1 is assigned to the check bit C 1 according to the code table according to FIG. Can e.g. B. the memory element D 1 only store the binary value "1" and the memory element P 1 only ^{store the binary value 11} O ", as can be seen from the third line of the table in FIG 16 test steps have the following content:

Step of the shift register SR 10: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Contents: 1000011101 1 0 1 1 0 1

Since, as already mentioned, the read-only memory FWS 11 is only addressed by the content of levels 1, 2, 3, 4, 5, 9, 12 and 15, In this case, the address 10000000 is assigned to it. When this address is supplied, the read-only memory generates its Output P 1 a signal that corresponds to the binary value "1". The output P 1 is EXCLUSIVE with the check bit P 1 assigned OR element of the correction circuit KS 5 connected, in which the test bit P 1 is corrected.

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Then the multiple switch ü 7 switches to the switch position C around. The word stored in the auxiliary register HR 4 and partially corrected by the correction circuit KS 5 runs through the error correction circuit FKS 3, in which the remaining data bit error is corrected.

The switch U 7 then switches back to its normal position C around.

The table in FIG. 6 applies to the case Ic. Can for example the storage elements D 7 and P 1 only store the binary value "0", so the content of the shift register SR 10 is after completing the 16 test steps, how to follow the table Fig. 6 takes:

Number of shift register stages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Contents: 11 111010. lOOlOOlO

In this case, the address is assigned to the read-only memory FWS 11 11111111 offered. It generates a "1" signal at output P again.

Whenever the faulty memory element stores a data bit that is not assigned to the check bit P, the Read-only memory for the test bit is addressed with the address 11111111 or 00000000, depending on whether the two defective memory elements can only store the same or different binary values.

The read-only memories FWS are connected in such a way that of the 2 = addresses, which can be formed from eight bits, only 2 χ 9 = 18 Addresses at output P of the read-only memory generate a signal that corresponds to the binary value "1", and the rest

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Docket GE 970 007; GE 869 163

- 15 addresses all have a signal that corresponds to the binary value "O".

One of the eight named addresses is obtained after the 16 test steps have been carried out if the faulty data bit is one of the eight of the data bits assigned to a check bit. The ninth address is the one that is obtained when the faulty data bit is not assigned to the check bit. Nine addresses result in the event that the memory elements can only store the same binary values. Nine other addresses, their bits opposite the bits of the first nine addresses are inverted, result in the event that the memory elements are only unequal Can store binary values.

Table 7 applies in the event that the memory elements P 2 and P 5 are defective. For example, can they only do the Store the binary value "1", so the shift register SR 10 after the 16 test steps have the following content:

Level of

Shift register: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Contents: 010101 lOOlOlOl

In this case, the FWS 12 to which the stages 4, 5, 6, 7, 8, 10, 13 and 16 of the shift register IO are connected, the Address 10110100 is supplied and the read-only memory FWS 5 assigned to check bit P 5 is supplied with the address with which levels 2, 5, 7, 12, 13, 14, 15 and 16 are connected to the address 10110110.

Both read-only memories generate the output signal "1" at these addresses at their outputs P 2 and P 5. Both output signals become EXCLUSIVE to those corresponding to check bits P 2 and P 5 OR elements of the correction circuit KS 5 supplied,

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at the outputs of which the corrected word appears, which then passes through the error correction circuit FKS 3 and goes to the processing unit is transmitted.

Since a "double error" caused by two check bit errors each check bit together with one of the remaining check bits in the underlying code with one of the five remaining check bits, the Can form double errors, 2 χ 5 = 10 additional addresses are added to the 18 addresses for each read-only memory, if they are relevant the read-only memory must also supply an output signal "1". Five of these ten additional addresses apply to the case ^ That the two storage elements can only store the same binary value, the rest in the event that they only can store different binary values. In total, each read-only memory therefore supplies an output signal for 28 addresses "1", with the others always an output signal "0".

In the following, the correction of double errors carried out according to the invention will be considered in more detail for the cases 2 a to 2 d mentioned earlier, in which one error is a sporadic writing error and the other is a permanent error. Since the test method according to the invention, which consists of 16 steps, only allows the localization of permanently defective memory elements, the permanent W error is first localized and corrected in cases 2 a to 2 d and the individual error then still present is then corrected in a known manner by the error correction circuit.

The table in FIG. 8 applies to case 2 a. Stores for example the faulty storage element D 2 only has the binary value "1", the counter Z 9 indicates after the 16 test steps have been carried out counts 15. In the shift register SR 10, as can be seen from the table according to FIG. 8, only stage 2 contains the binary value "0", all others the binary value "1". When the count is 15, those with the complementary outputs of the shift register stages connected AND gates switched through. In the present case,

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in which only the complementary output of stage 2 has high potential, only the AND gate connected downstream of this stage generates 18 an output pulse through which the bit read out from the faulty memory element D 2 in the correction circuit KS is corrected.

The individual error still present, which is caused by a sporadic writing error, is then cleared by the error correction circuit corrected.

The table in FIG. 8 also applies to case 2b). It then assumes that the storage element D 2 only stores the binary value "0" can, after the 16 test steps only stage 2 of the shift register has the value "1", all others have the value "0". In this case, the count of counter Z 9 is 1, as can be seen in line 1 of table 8. So it just becomes that AND gate 19 connected to the regular output of stage 2 is switched through and the data bit D 2 is passed through the correction circuit KS 5 corrected. Their outputs are then switched via the multiple switch U 7, which is again in switch position C switches, fed to the error correction circuit FKS 3, in which the still existing sporadic write error is corrected will.

Cases 2c) and 2d) correspond to case Ic, which was dealt with earlier, since in them too the faulty memory element P is first localized and the check bit is corrected. In these cases too, the address for the read-only memory is 11111111 or 00O00000. The sporadic error is then localized by the error correction circuit.

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Docket GE 970 007; GE 869 163

Claims (7)

2 f34b29 PATENT CLAIMS Method for error detection and correction in from the memory of a program-controlled data processing system read out information words from η bits, from where k are check bits that correct the correction of t errors and enable the detection of t + 1 errors, characterized in that for correcting t + 1 errors, from at least one of which is a so-called permanent error, d. H. one whose cause is a permanently faulty one Storage element is, first of all, the permanent error or errors in a special test procedure for the storage space, When reading it out, the multiple errors that were uncorrectable due to the code properties were found was localized and corrected and the information word thus obtained afterwards after passing through a known error correction circuit is transmitted to the processing unit. 2. The method according to claim 1, characterized in that after displaying t + 1 by the error correction circuit no longer due to the properties of the code ψ correctable errors of the selected space to eliminate so-called sporadic read errors, d. H. of errors, the cause of which only occurs briefly during a Reading process is present and which are therefore not reproducible, is read out again. 3. The method according to claims 1 and 2, characterized in that the special test method for localization and correcting the permanent under the t + 1 errors consists of the following steps: 20988 4/1119 Docket GE 970 007; GE 869 163 OBQ iNSPECTSD a) a data pattern consisting of n-k bits is fed to the check bit generator of the error correction circuit, in which the first bit has the binary value "1" and the remaining bits have the binary value "0"; b) the check bits for this data pattern are calculated in a known manner, with the data pattern in the faulty one Storage space is stored, read out again and fed to the error correction circuit, which consists of derives test bits from the read out data pattern, compares them with the stored ones and delivers a signal, that indicates either correctable or uncorrectable errors or freedom from errors; c) the correctable error indicating signal is a counter and the series input of an n-k stage Shift register supplied, the content of which is shifted by one level after each supplied signal; d) the check bit generator now receives a further data pattern supplied, in which the binary value "1" is shifted by one place compared to the previous data pattern is; e) steps b to d are repeated until each data bit memory element of the selected memory location once the binary value "1" was offered; f) according to the n-kj output signal of the error correction circuit the counter reading of the counter and / or the content of the shift register for error localization and correction evaluated. 4. The method according to claims 1 to 3, characterized in that permanent data bit errors by evaluation of the achieved at the end of the special test procedure 209884/1119 Docket GE 970 007; GE 869 163 Counter reading of the counter (Z 9) and the contents of the shift register are corrected in such a way that the counter reading for this purpose, the regular or complementary content of the corresponding to the faulty data bits is used Shift register stages to a correction circuit consisting of η EXCLUSIVE OR gates (KS 5) through which the second inputs are connected to an auxiliary register (HR 4) in which the t + 1 Information word containing errors is stored, the erroneous bits of which are thus corrected by inverting will. 5. The method according to claims 1 to 3, characterized in that permanent check bit errors by evaluation of the shift register contents are corrected in such a way that the contents of those register stages which are in accordance with the selected code are assigned to a test bit, for addressing a read-only memory assigned to this test bit (FWS) can be used, which generates an output signal that is fed to the correction circuit (KS 5) so that the faulty check bit or bits > The information word stored in the auxiliary register (HR 4) can be corrected by inverting. 6. The method according to claims 1 to 5, characterized. records that after correcting the permanent error the sporadic typographical errors still present, the cause of which is only briefly during a write process was present by the error correction circuit in 'can be corrected in a known manner. 7. Circuit arrangement for performing the method according to claims 1 to 6, characterized by the following Characteristics: 20988.4 / 1119 Docket GE 970 007; GE 869 163 a) rait the storage outputs is an n-stage auxiliary register (HR 4) connected, the one containing a t + 1 error Stores information word and its outputs is connected to a correction circuit (KS 5) consisting of η EXCLUSIVE OR gates, whose η Outputs via a multifunction switch U 7 with a known error correction circuit (FKS 3) for correction errors are connectable by t; b) to the. indicate the presence of correctable errors The output of the error correction circuit (FKS. 3) is on Z-äfeler (line 9) · and the series input of an n-k stage. Shift register (SR 10) connected, of its regular outputs are those that, according to the selected code are assigned to a check bit (P) the AdEesse inputs of a read-only memory assigned to this check bit (FWS), its output (P) to the second input of the check bit assigned to this EXCLUSIVE OR gate of the correction circuit leads; c) the regular and the complementary outcome of each Shift register stage is in each case via an AND element (15 or 18), the outputs of which to an OR gate (20) connected to one input of the one Dmfcenbit corresponding EXCLUSIVE OR gate of the Correction circuit '(KS 5) connected; d £ the second inputs of the to the regular outputs of the Scitie register stages connected AND elements (19) ' are via an OR gate (21) to two AND gates (22; 23) - connected to selected outputs of the Counters (2 9 /) are connected, while those to the complementary Outputs connected AND elements (18) via a further OR element (24) with two more AND elements (25; 2 €) are connected. / titt ι ** · ♦ Blank page