DE2122475B2 - Multi-layer printed circuit board using thick film technology for wiring integrated semiconductor components - Google Patents

Description

The invention relates to a multi-layer in such a thick film technology printed circuit board executed according to the preamble of claim 1. Such a circuit board is assumed to be known ( "The electronics", no. 2, 1970, pages 57 to 71).

Semiconductor memories consist of a large number of monolithic semiconductor components that have to be connected to one another and to control circuits. For this purpose, the semiconductor modules or chips are arranged on circuit boards to which conductor track arrangements are applied. The conductor tracks usually run outside of the semiconductor components. To wire the semiconductor components, however, a relatively large number of conductor tracks is necessary, so the space requirement for the conductor tracks is very large. However, this means that the number of ⁶ S semiconductor components to be contacted on the circuit board will be small.

From US patent specification 34 47 038 a conductor track arrangement is known in which the conductor tracks to run at least partially below the semiconductor modules. This is made possible by the fact that on dei Raised conductor tracks are provided which use as contact areas for the semiconductor modules will. The conductor tracks can cross on the circuit board, but they are at the crossing plate isolated from each other A disadvantage of this conductor track arrangement is that the conductor tracks finally verlau fen on the surface of the circuit board. This means that the number of mil the semiconductor components usable conductor tracks limited.

It is also known to arrange conductor tracks in different line levels (e.g. English Pa tentschrift 11 37 907, French patent specification 15 64 787). For this purpose, conductor tracks, which can also cross, can be arranged in the semiconductor material. The conductor tracks are diffused into the semiconductor material. The manufacture of a multilayer circuit board is very expensive. It is also possible for those on the Provide bridging links for the uppermost line level of the printed circuit board crossing conductor tracks. These Bridging links can also be made of semiconductor material. In this case too, the Conductor tracks diffused into the semiconductor material, so that the above-mentioned disadvantages also occur here.

The object on which the invention is based, on the other hand, is to provide a multilayer, using thick film technology specified printed circuit board according to the preamble of claim 1, in which the contact surfaces and their connections to the partially internal conductor tracks can be easily established can and with which it is possible to arrange the semiconductor components in very narrow pitch grids. These The object is achieved by the combination of the features specified in the characterizing part of claim 1.

With the help of the circuit board according to the invention, in which part of the conductor track arrangement is known per se Way below the semiconductor components, the packing density of the semiconductor components can can be increased significantly. Another advantage is that the contact surfaces for the semiconductor modules are mechanical can be edited. This is e.g. B. important if there are residues on the contact surfaces when replacing must be removed from semiconductor components. The connecting lines of conductor tracks the internal line levels to the contact surfaces, which are located on the outermost management level can be arranged outside of the module area and used for electrical measurements.

Further developments of the invention emerge from the subclaims.

An embodiment of the invention shown in various stages of its manufacture in the figures is illustrated is explained below. It shows on an enlarged scale

F i g. 1 the first line level applied to a substrate,

F i g. 2 a section through the line level and the substrate,

F i g. 3 the first level of isolation,

4 shows a section through the arrangement of the F i g. 3,

F i g. 5 a second management level,

6 shows a section through the arrangement of the

15th

F i g. 7 is a perspective view of part of the circuit board.

On a substrate SLZ (Fig. 1), the z. B. can consist of aluminum oxide, the first line level is applied by known methods of thick film technology, which consists of conductor tracks L1. Simultaneously with the application of the conductor tracks L1, the substructure for the contact surfaces is also created, which in the exemplary embodiment consists of patches FL of conductive material. Since the contact areas in the exemplary embodiment are not arranged above conductor tracks L1 of the first line level, as many spots FL must be provided as there are contact areas in the outermost line level

FIG. 2 shows a section through the arrangement of FIG. 1. SLZ is again the substrate, Li are the conductor tracks and FL are the spots for the contact substructure.

Insulation material is then applied to the first line level. The insulation layer is - as shown in ^Fig. 3 ζε '8 ^ι "~ ^mlt ^ . The first line level is followed by a first insulation level Insulation material of the first insulation level left free The vias through the first insulation level are denoted by D.

F i g. 4 shows a section through the arrangement of FIG. 3. It can be seen from it that the circuit board consists of a substrate SLZ, the first line level and the first insulation level.

As shown in FIG. 5 and 6 represent - the second line level applied. The conductor tracks of the second line level run perpendicular to the conductor tracks of the first line level. They are named L 2. Since the second line level should also be the outermost line level, the contact areas for contacting the semiconductor components are also arranged in or on it, areas KF are shown in a drawing for easier recognition. When realizing a printed circuit board, of course, these different possibilities cannot be used at the same time.

SU is again the name of the substrate on which a line level and an isolation level are arranged alternately. In the following, the various options for the substructure of the ACF contact surfaces will now be described:

The contact area ACF4 lies directly over a conductor track of the first line level. For this reason, the conductor track L 1 can be used for the contact substructure. Of course, the conductor track L 1 is followed by an insulation level IS, then a connection of the contact area ACF4 in the outermost line level. This consists in this case of a connection line VL to a connection point VS, through which the connection line VL is connected to a conductor track L 1 of the first line level. The contact surface KF4 is placed on the connecting line VL as an additional spot, ie the contact surface KF4 is higher than the conductor tracks L 2 of the second line level.

The contact surfaces KF5, KFb are also attached above the conductor track L 1 of the first line level. In the case of the contact surface KF5 , however, a patch FL made of conductive material is applied directly to the conductor track L 1 of the first line level as a substructure. An insulating layer lies between the patch FL and the contact surface KF5. In the case of the contact area ACF6, a patch is placed directly on the connection line to the conductor track L 2 of the second line level.

The contact areas KF4, / CF5, KF6 are all next to the conductor tracks L 2 of the second line level. The contact area ACF7, on the other hand, is arranged above the conductor track L 2 of the second line level. The rest of the structure of the substructure, which lies under the contact surface ACF, corresponds to that under the contact surface ACF6.

The contact surfaces ACF4, ACF5, ACF6, ACF7 all have at least one patch of conductive material,

40

Execution of the circuit board the conductor tracks L 1 and KF 1. Da below the contact surface

^AUSf to a bucket part below the semiconductor building 50 ba ^ r, a Lemings level - ^, ^ - ^ rer

agile.

from F i

and 6 that the contact surfaces are also provided on the 55 contact substructure. The same is true

In the embodiment of FIG. 1 to 6 consists the circuit board consists of a substrate, two line levels and an insulation level. The circuit board can Of course, it can also be made up of more management levels and correspondingly more insulation levels. The production of such a printed circuit board using thick film technology is generally known and can be found in the literature can be removed.

In Fig. Fig. 7 is a part of the circuit board in perspective View shown. There are different 1 of the contact substructure for the contact

KF ensures that the contact surfaces are all at the same height and that the contact surfaces have at least the same height as the conductor tracks of the outermost line level. Thus, the semiconductor modules HBS can be placed on the contact surfaces and contacted and still run underneath the semiconductor modules conductor tracks.

The remaining contact areas ACF8, ACF12 are only indicated in principle, just as part of the conductor tracks of the line levels are shown schematically by dashed lines. With M is part of the ladder

tracks of the outermost line level, which can be used as a measuring point for test purposes. This measuring point M lies outside the block geometry. KFT, KFS ', KF9' are contact areas for an adjacent semiconductor component.

For this purpose 4 sheets of drawings

Claims (5)

Patent claims: 1. Multi-layer, thick-film printed circuit board for wiring integrated Semiconductor components in which layers with conductor tracks and layers alternate on a substrate with insulating material are arranged one above the other, and in which the contact surfaces for contacting are at the same level as the semiconductor modules in / on the outermost line level, characterized by the combination of the following Characteristics: a) on the line levels running inside the circuit board, next to the lower conductor tracks (Ll), spots (FL) made of conductor track material that are not electrically connected to these are arranged, b) the contact surfaces (KF) are above the stretchers (FL) in such a way that they are raised into the contact plane by the flecks and the insulating layer (IS) above, c) the conductor tracks run (L 2) in the top line level in part under the semiconductor components (HBS). * 5 2. Circuit board according to claim 1, characterized in that the spots (FL) are provided in each line level except the outermost below the contact surfaces (KF) . 3. A printed circuit board according to claim 1, characterized in that patches (FL) are provided in each line level, the patch being used as a contact surface on the outermost line level. 4. Printed circuit board according to claim 1, characterized in that below the contact surfaces (KF) run conductor tracks in at least one line level and that only in the line levels patches (FL) are arranged below the contact surfaces in which no conductor tracks are below the contact surfaces (KF) . 5. Circuit board according to one of the preceding claims, characterized in that the number of spots (FL) or conductor tracks (L) provided as a substructure on top of one another is 1 or 2 greater than the number of line levels.