DE2038217B2 - CIRCUIT ARRANGEMENT FOR THE SIMULTANEOUS MONITORING OF SEVERAL VOLTAGES FOR BELOW AND / OR EXCEEDED A SPECIFIED SET LEVEL - Google Patents

Description

, Normal operation are permeable, that according to the number of voltages to be monitored there are diodes for decoupling which are unconnected with opposing electrodes and with voltage monitoring s e4m polder fu and in which the output side of the one decoupling diode of a Dio ^ npaa-S is connected to the Connection point of the reference-Sode and the ohmic resistance for the posi-Se reference potential and at which the Ausgangsidtige pole of the respective other decoupling diode deTDiodenpaa.es are led to the connection point of the reference diode and the ohmic resistance for the SSrc reference potential in such a way that you use diode pairs for decoupling are locked in the normal case, that furthermore is parallel to the ohmic Wigrstand for the reference diode for fas more negative reference potential, a voltage divider, the comparator is at desfen center tap of the one input of the! oeführt, while the other input of the grain ⁸ comparator is the Vubindungspunkt the reference diode for the more positive reference potential and the associated ohmic resistance is connected. ^ZU8 M e ner multiple monitoring the invention may for example all monitored together for a carrier frequency system produce carrier pilots and control level and switched on failure to compensation who-Sen without a disproportionate effort _s jnd.

kind of trained _; that those of w_

Assemblies * ^ * ^ JJS DC monitoring voltage under

The arrangement according to the invention is designed so that the comparator also built m circuit technology knew

its special ^^ ikausj ^^

On the basis of the ^^ F ^ gf grams according to Fig. 1 and 3 te 5 as well as J ^s gg ic Fig. 2, the invention is explained in more detail - _

The principle current flow of such a thing ^^ ^^

Limit value _{monitoring shows e} / _s ¹ _{arrangement of} the important potentials m ° f ^r bcüarrrag ^ ^

ir. Dependence on an input voltage shown in FIG
The'

over ^ swell from ^ * o D 6 through to
Decoupling

about the ^ ψζ

, 5 such that -F <2 ^ or

the potential V3

nal po enti al 2

_{are vl to Un} ? The response deviations _{D t un} d - and V + ng Vl so are the

locked while g P ' _{d h wi} .

\ ^ * Lon flows. A certain ^ ^

j «« _{s annungst} part R 3, en ^ ^ _R

by the amount U pos. %

_DS

THE ALERT SWEET 30 SSTALS

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5t ^ S? Sl "Si vern§n ^g changed. Due to the low offset voltages and currents S that occur, a high level of accuracy of the response points is achieved with greater reliability and low space requirements. For the plus-minus monitoring of a Pe _g S, only one monitoring ggle.chspan - "" ng is required, and there is no special inversion level for the sign reversal.

To compensate for the threshold voltage of the DiodTn for decoupling and to compensate for its temperature response, it is advantageous to connect a compensation diode, which is supplied with an impressed current via an ohmic resistor, in series in the opposite pole direction. ⁸ Instead of the compensation diodes

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^ Lj _n values down, then that takes

we.se »™ f ^tt ^ J ™ g ^ from ü« on, as soon as the Potojüd V3 »d as the potential V-. Voltage ΙΛ ^ne negative accordingly

It ^ .st then the E ^ oJ ^ ¹ / _uch ^P _{the potential} l Vl; ^ ^^^ ^, tant At the top An, the ™ em ar 1 _{id the} potentials

talk threshold / 12 ubeßcM ^^^. ^^ ^ _

^^^^ 5 ^ ,,,?. An analogous overarching Gjenzwwi ^ _{Anrechschwelle A} 1 laying | 1 JJ _{der Entk} o _PP lungsd.oden

° «^ S ^ Siang can be _{compensated with two diodes and their 1_em p} erai _h j . A corresponding DI ^ and D8 honor ge _p P _{3 D; ese} Moder and

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points of reference diode and ohmic resistor F ^ stand is connected. Instead of a diode, 55 Diode Aug g P can be used
at _A ^ h

of the comparator ge

ssÄp

be connectable with a button with earth potential.

For the purpose of short-circuiting sturgeon pulses, between the two inputs of the grain

themselves

^6S restore normal state. If there are _{or more} e of the input voltages J, then after

IS

Ko _m pa ™ "new, a" _S p _re c _te ".

A resistor R 7 enables the capacitor C1 to be discharged after the button Tl has been opened. Another capacitor C1 has the task of short-circuiting the input of the comparator to interference pulses and thus increases the immunity to interference.

The one-time checking avoids the in FIG. 4, in which the output voltage is fed back via a transistor Tr 2. By pressing a cancel key T 2 , the feedback is interrupted, and the circuit only returns to the normal state if all input voltages are within the response limits. In Fig. 4 it is also shown how the temperature compensation can take place with the emitter-base path of a transistor TrI. This circuit variant enables the voltage divider R 3, R 4 to be designed with low resistance and thus to keep the influence of the offset current on the response wave even lower.

In Fig. 5 shows how all the voltages of the components required in a carrier frequency system can be monitored simultaneously with the aid of the arrangement according to the invention. The first five assemblies represent the pilot amplifier PV, the following seven assemblies control frequency amplifier StV, the following assembly the carrier amplifier TV, the subsequent two assemblies the auxiliary frequency amplifier HV and the last assembly the frequency control FK . The response limits for Ul to J75 are from - 0.2 to - 0.5 db on the lower side, from + 0.2 to +1.0 db on the upper side. At U 6 to

ίο t / 8 and UlO to Ϊ / 15, only the lower response limits are monitored, which are - 2.0 to - 4.0 db, and the response limit of C / 9 is - 1.0 to - 3.0 db . Here, too, only the lower response limit is monitored.

The different lower thresholds for carrier, pilot and control levels are, as in the F i g. 5 specified, achieved by different setpoints of the monitoring DC voltages output by the amplifiers. One therefore needs in the Multiple monitoring no additional voltage dividers for different response thresholds and can conduct the monitoring voltages to the control lines with an optimally low internal resistance.

1 sheet of drawings

Claims (5)

is bound and that the base of the transistor claims: (7> 2) via an ohmic resistor (R 8) and a cancel button (T 2) can be connected to ground 1. Circuit arrangement for simultaneous 6. Circuit arrangement according to one of the pre-monitoring of several voltages on lower 5 claims, characterized gekennzeich- and / or exceeding a predetermined net that each input of the comparator setpoint level using a comparator, (K) via a parallel connection from a capacitor to which the voltages to be monitored are fed via di- (C2) and ohmic resistance (R 7) and a dull one, which means that the key (T1) can be connected to earth potential
Characterized that the two reference potentials io 7. Circuit arrangement according to one of the pre- (F +, F-) for the undervoltage and overvoltage-related claims, characterized in each case border on one pole of each reference that between the two inputs of the comparing diode (Dl; D 6) lie which reference rators a capacitor (C 1) lies diodes (Dl, D 6) each via an ohmic 8th circuit arrangement according to one of the Resistor (Rl; R2) such a bias 15 claims, characterized thereby is that it runs through the modules to be monitored in normal operation it is permissible that the monitoring equilibrium corresponds to the number of setpoints to be monitored voltages (Ul to Un) di- voltage are of different sizes, odcnpaarc for decoupling (D 2, D 4; D 3rd DS)
are present, which on the input side with opposite 20
set electrodes and each with one pole the voltages to be monitored (Ul to Un) are connected and where the output side
Pole of a decoupling diode (D 4; D 5) one
Pair of diodes (D 2, D 4; D 3, D 5) on the 25th Connection point of the reference diode (D 6) and The invention relates to a circuit of the ohmic resistance (R 1) for the positive arrangement for the simultaneous monitoring of several tivere reference potentials (F +) and for those of the voltages for undershooting and / or overshooting of the output-side pole of the respective other decoupling of a given setpoint level using development diode (D 2 ; D 3) of the diode pair (D 2, D 4; 30 of a comparator to which the D 3, D 5 to be monitored) are fed to the connection point of the reference voltages via diodes,
reference diode (D 1) and the ohmic resistance Known circuit arrangements for plus-minus (R 2) for the more negative reference potential (F-) monitoring of a voltage have the disadvantage of being guided in such a way that the diode pairs for the voltage deviations at the same time via decoupling (D 2, D 4; D 3, D 5) in the normal case 35 one inverting and a non-inverting are blocked that are also led parallel to the ohmic path to a limit value stage. Resistance (R 2) for the reference diode (D 1) for example in the German patent the more negative reference potential (F-) is a voltage described, in which each input to tap the one input of the comparator (K) ge 40 leads a differential amplifier with an inverting, while the other input of the grain and a non-inverting output is performed. parators (K) with the connection point of the Re- The outputs are via a z. B. from diodes gebilferenzdiode (D 6) linked for the more positive reference potential OR circuit and led to a Grenztial (F +) and the associated ohmic countervalue circuit. The setting of the response level (R 1) is connected. 45 points is made by reference voltages and the 2. Circuit arrangement according to claim 1, selected gain. characterized in that each of the same- From the German patent specification 1 289 557 a polarized diode for decoupling (D2, D3; D4, circuit arrangement is known in which the one for the D 5) each have a compensation diode (D 7; D 8), the implementation of a positive and negative limit value each with an ohmic resistance (RS; R 6) 50 th necessary reversal of sign in which the applied current is supplied to the opposing assembly takes place. There, the set pole direction must then be connected in series. however, two DC monitoring voltages are present 3. Circuit arrangement according to claim 2, that the limit value detector is guided. characterized in that instead of the compen- the object of the present invention is to provide a sationsdioden (D7, D 8) transistors (TrI) in front of 55 circuit arrangement for simultaneous monitoring are seen. multiple voltages to under- and / or over- 4. A circuit arrangement according to claim 1 to create a predetermined target level, or 2, characterized in that the output is not required at the corresponding inversion stages of the comparator (K) via a feedback and at the same time simple in their structure diode (D 9) with one of the connection points 60 and is reliable in the monitoring of the corresponding reference diode (D 1; D 6) and ohmic important voltage. derstand (R 2; Rl) is connected. According to the invention, this object is in a 5. Circuit arrangement according to claim 1 Circuit arrangement of the type mentioned or 2, characterized in that the trigger is achieved in that the two reference potentials output of the comparator (K) via the emitter collector 65 for the undervoltage and overvoltage limit in each case to lektor -Distance of a transistor (TrI) with one pole of a reference diode each, which of the connection points of the reference diode (Dl; reference diodes each via an ohmic resistor D 6) and an ohmic resistor (R 2; Rl) understood such a bias fed is that she