DE2015815B2 - PROTECTIVE CIRCUIT FOR AN INTEGRATED CIRCUIT - Google Patents

Description

«Was enough. Another advantage is toS, as a result of the additional protective diode in the for

whose diode parallel gate-substrate capacitance * Γ§ί fceine throw such a high static charge stored can as before, but the charge with the appropriate polarity essentially depends on the junction capacitance of the PN junction between the substrates, which is much larger, so that the stresses occurring are correspondingly small are. This reliably prevents the voltage from becoming dangerous due to static charging Can assume values.

The invention is hereinafter referred to as a preferred one Embodiment explained in detail with reference to the drawing. It shows

pig. 1 the circuit diagram of a complementary Inverter stage with a protective circuit according to FIG

Invention,.

pig. 2 a cross-sectional view of a monolithic circuit module with the protective

tune and
3 shows an equivalent circuit diagram of the protective circuit

according to FIGS. 1 and 2.

The circuit according to FIG. 1 contains an energy supply source in the form of a battery 10 with the voltage V ₀₀ . The battery 10 is connected with its positive pole to a terminal 12 and with its negative pole to a terminal 14. A P-conductive IGFET 16 is connected with its source electrode 16s and with its substrate 30 to the terminal 12 and with its drain electrode 16d to the connection point 18. An N-leitenoer IGFET 20 is connected to the junction 18 and with its substrate 40, and its source electrode 20 s connected by its drain electrode to terminal 2oD fourteenth The gate electrodes 16g and 20g of the IGFET 16 and 20 are connected in common to the connection point 22. A diode D 1 with its anode and a diode D1 with its cathode are also connected to the connection point 22. The cathode of the diode D 1 is connected to the terminal 12 and the anode of the diode D 2 is connected to the terminal 14. A resistor R serving to limit the current, which can be designed either as an integrated (semiconductor) or as a discrete component, is connected between the connection point 22 and the signal input 24 in order to prevent the diodes or the insulating layer from being excessively high and sudden Input voltage will be destroyed.

The operation of the circuit nacr. F i g. 1 can be explained more easily if one assumes, for example, that + V _{00 is} equal to 10 volts, terminal 14 has zero or ground potential and the input signal fed to signal input 24 has negative and positive amplitudes that can be greater than 45 to 65 Volts, which are to be used as the breakdown voltage of the insulating layer.

The mode of operation of the circuit is now to be examined on the basis of the three cases that the supplied voltage firstly fluctuates between 0 volts and V ₀₀ , secondly becomes more positive than V ₀₀ and thirdly becomes more negative than 0 volts.

Case 1: If the voltage (V ₀ ) applied to the gate electrodes at junction 22 is greater than 0 volts and less than V ₀₀ [0 volts <V ₀ <V _DD ], diodes D 1 and D 2 are reverse biased , so high resistance. Thus, when the voltage applied to the gate electrodes is within the operating voltage range, the circuit operates as if the diodes were absent.

Case 2: When V ₀ exceeds + V _DD , diode D1 is forward biased so that a current (in the conventional sense) flows from junction 22 to terminal 12. When diode D 1 conducts, the voltage drop across the diode is equal to the forward voltage drop (V _F ) across the ^{PN junction formed by P + region} 37 and substrate 30 in FIG. The value of V _F rises somewhat with increasing current consumption due to the transition; however, it can be assumed that this value remains in the range of 0.6 to 1.0 volts for the current range considered here. The voltage at connection point 22 can not exceed the value I V ₀₀ + Vf I, since a possible voltage increase, be it signal input 24 or at connection point 22, causes diode D 1 to conduct more strongly, so that the gate voltage at j V ₀₀ 4 - V _F J remains in brackets. As a result, the gate-to-substrate voltage of the IGFET 16 is reverse biased by an amount equal to the pass voltage drop V ₁ , the diode D 1, which is obviously a safe value.

When V _{0 is} positive, diode D 2 is reverse biased so that it will not conduct unless the reverse voltage across its anode and cathode exceeds its reverse breakdown voltage (V _R ). Since V _{R is} typically 40 volts and more and j V ₀₀ + V _F \ is considerably less than 40 volts, the diode D 2 cannot break down, so that it maintains its high-resistance state.

In the case of the IGFET 20, the maximum voltage between the gate electrode 20 g and the substrate 40 is when V _{0 is} positive, since the substrate 40 is at ground or zero potential. Since the maximum value of V _{0 is} equal to j V ₀₀ + V _F | and since the substrate 40 of the IGFET 20 is at 0 volts, the gate electrode 20 of the IGFET 20 is by the amount '. V ₀₁ , + V _F , forward biased with respect to the substrate. Since V _{F is of} the order of magnitude of 1 volt and the voltage V ₀₀ (10 volts) is always dimensioned so that it is well below the breakdown voltage of the insulating layer, the IGFET 20 is also well protected.

Case 3: If V ₀ goes negative (V ₀ < 0 volts), the diode D 2 is forward-biased and a current flows (in the conventional sense) from the terminal 14 to the connection point 22. When the diode Dl conducts, is the voltage drop across this diode is equal to the forward voltage drop (V _F ) of the through the N + region 47 and the P-type substrate 40 in FIG. 2 formed PN junction. The value V _{F of} the diode D 2 is approximately equal to the value V _{F of} the diode Dl. To the extent that the voltage at the signal input 24 or at the connection point 22 rises in the negative direction, the diode D conducts correspondingly more strongly, so that the gate -Electrodes 16 g, 20 g are clamped to a voltage of V _F below zero potential (V ₀ = - V _F ). Thus, regardless of the amplitude of the negative signal, the gate electrode of IGFET 20 will be reverse biased with respect to the substrate by an amount equal to V _F , which is a safe value since Vf is on the order of 1 volt.

When V _{0 is} negative, diode D1 is blocked so that it does not conduct. Since the maximum negative voltage at the gate electrode 16g of the IGFET 16 and

at the anode of the diode D 1 is equal to - V, .- volts, and since the substrate of the IGFET 16 and the cathode of the diode D1 are connected to + V _0n volts, the diode Dl and the gate-substrate path of the IGFET are 16 biased with a voltage in the forward direction, the amplitude of which is equal to j V _0. , + V ₁ j. Since, as before, V ₁ - is on the order of 1 volt and V _0n (10 volts) is well below the reverse breakdown voltage of diode D 1 and the gate-substrate breakdown voltage of IGFET 16 , the transistor is well protected.

As is apparent from the foregoing, the forward conduction of two diodes D 1 and Dl can be limited by utilizing the voltage between the gate electrode and the substrate to a safe value.

The simplicity and effectiveness of the present circuit can be seen by referring to FIG. 2 considered, which shows in cross section an integrated circuit according to the invention. The circuit component is made in monolithic form by conventional methods and includes a substrate 30 from a semiconductor material such as silicon, which in this case is N-conductive. On, the surface 34 of the substrate 30, the elements of the circuit module can be formed with the aid of conventional diffusion processes will.

A diffused-in is located on the surface 34 P-type region which forms the active substrate 40 for the N-type IGFET 20 of the circuit. Within this diffused area on the surface 34 are located at a distance from one another the source zone 45 and the drain zone 46 of the IGFET 20. There is also an indiffused region 47 is provided, which with the remaining part of the substrate 40 forms a diode D 2 PN junction forms.

The P-type IGFET 16 formed in the substrate 30 outside the substrate 40 is spaced from each other a source region 35 and a drain region 36. A P-conductive region 37, which at the Surface 34 is provided at a point spaced apart from IGFET 16, forms one with substrate 30 the PN junction forming the diode D1.

The N + -conductive region 47 of the diode D 2, the gate electrode of the N-conductive IGFET 20, the gate electrode of the P-conductive IGFET 16 and the P-region of the diode D1 are all through a common conductor 21, which in turn is connected to the connection point 22 , interconnected. A contact SO connects the substrate 40 of the N-conductive IGFET 20, designed as a P-well, to the terminal 14, which, as mentioned above, can be connected to ground. A contact 52 connected to the N-conductive substrate 30 is connected to the terminal 12, which can be connected to + V _0n , as also already mentioned.

The use of a P ^{+ region} 37 in connection with the substrate 30 for the formation of a protection diode and the use of an N-conducting region 47 in connection with the substrate 40 for the formation of a second protection diode provide a simple solution to the difficult problem of the protection of the Insulating layer.

The diodes D1 and D 2 form a conduction path between the PN junction formed by the substrate 40 and the substrate JO and the gate electrical Jen. The benefit of this conduction path, although not further apparent, results in part from the fact that the PN junction has a barrier layer capacitance which, because of the relatively large extension of the junction, is one to two orders of magnitude larger than the gate-substrate Capacitance of a typical IGFET can be.

There is therefore, as shown in FIG. 3 (diode D ₁ ) shows a reverse biased PN junction, dei with its cathode (substrate 30) on terminal II and with its anode (substrate 40) on terminal 14

ίο is connected, and to which a junction capacitance (C;) is parallel.

Let us now consider the case that a static charge is stored while the circuit component is electrically "floating"; H. without mass connection is (z. B. when carrying or handling), and that then only one of the terminals 12 and 14 first connected to ground either directly or through the low source impedance of battery 10 is, for example, when installing the circuit module in a circuit arrangement.

In order to adjust how the diodes, in conjunction with various capacitances, help to prevent a build-up of voltage due to static charges, consider FIG. 3, which shows a simplified equivalent circuit diagram of the circuits according to FIGS. In the equivalent circuit diagram, the gate-substrate capacitance (C ₁ ) of the IGFET 20 closed by the diode D 2 is _{in series with the gate-substrate capacitance (C 1) of the closed by the diode D 1}

_{IGFET 16 in series with the junction capacitance (C;} ) of the substrates shunted by the PN junction diode (Dy) of the substrates. To simplify the explanation, assume that the static charge on the gate electrodes at junction 22 is positive and only terminal 14 is grounded. If the diode D1 were not present, the total capacitance would be very small, since C _{2 would} effectively lie in parallel with the series connection of C _{1 and C 1.} As a consequence of this, the voltage at C ₂ (V = - £), which is applied to the gate-substrate stretch of the IGFET 20, could be so great that the oxide layer is broken through or penetrated. However, since the diode Dl couples the gate electrodes 16g, 20g to the substrate 30, this _{effectively makes C 2 in} parallel with C _; switched. Since the amount of charge (Q) is constant, increasing the capacitance by one order of magnitude lowers the voltage by one order of magnitude. Even if the terminal 12 is not at a low-resistance point, the fact that the diode D 1 conducts as soon as the voltage at the gate electrode exceeds the voltage at the substrate 30 prevents the build-up of a high voltage. It is now assumed that the stored

Guaranteed charge negative and only the terminal 12 is connected to the positive pole of the battery 10. The diode D 2 now puts C, parallel to C ₁ . The voltage between the gate electrode and the substrate of the IGFET16 is therefore suppressed considerably, since the La tion is constant as before and the diode D 2 is now used to distribute the charge to a much larger capacitance and to charge it.

The diodes D 1 and D 2 thus connect a larger capacitance in parallel with the various gate- substrate capacitances and protect the insulating layers in that they prevent the build-up of a high voltage as a result of static charging.
If the stored charge is positive and the

Terminal 12 is connected to the positive pole of battery 10, or if the stored charge is negative and terminal 14 is connected to ground, there is no risk of high voltages being built up, since the diodes are then connected to K ₀ ( V _n ,, ! V ₁ ) or cling to (- V ₁ ) , as in connection with FIG. 1 described.

Note that different Liehe PN junctions are present is also, (see. That can help I also that ei failure of the insulating layer is prevented. However, I have DEND the diode Dl and Dl, two critical supply lines between Su and the gate -Form electrodes.

1 sheet of drawings

Claims (3)

The substrate of a (discrete) field effect transistor is patent claims: also known from BE-PS 6 96 173. Up until now it was believed that this protective measure was 1. Protection circuit for an integrated circuit, since a single diode contains the insulating layer circuit, the two insulating layer field effect transistor voltage theoretically, depending on the polarity of the conductivity type opposite to that of the (IGFET) large input voltage either on its length, which on two with each other Rectifying voltage or breaking voltage (e.g. 25 V) is limited on semiconductor substrates which almost pass through their blocking junction, that is to say normally from mutually opposite conductivities to harmless values. In practice it can be arranged, with one between the two, however, the reverse breakdown of an interconnected gate electrode of the two such diodes only occurs at an abnormally high value IGFET and the first, N-conducting substrate is or If the diode does not break down sufficiently quickly, the first semiconductor diode switched, which in such cases can break through the insulating layer of the transistor protecting its anode on the two gate electrodes, i.e. is destroyed, before the diode becomes effective can be,
net that the protective circuit has a second half To avoid these disadvantages, one can contain a conductor diode (D 2), the two gate electrodes (16 g, 20 g) and with its cathode at the forward biased PN junction combine to cling signals of one polarity of their anode to the second, P-type substrate with a first transistor, which is connected as an on (40). 20 input impedance element between the input point 2. Protective circuit according to claim 1, characterized in that the circuit and a second transistor is located, characterized in that the protective circuit is connected as a diode via the input of a third between the interconnected gate-electrode transistor, the insulating layer of which is troden (16g, 20g) and a signal input (24) is to be protected. The channel of the second transi-connected, the input current limiting 25 stors (diode), whose gate and drain electrodes contain resistance (R). are interconnected is between the gate and 3. Protection circuit according to claim 1 or 2, source electrodes of the transistor to be protected characterized in that the two half-switched. This becomes the third transistor Conductor diodes (Dl, D 2) each from a semi-protected, but now the entire load is the Conductor area (37, 47) are formed, which is buried in the first 3 ° and the second transistor. Absten or in the second substrate (30, 40) is seen from the fact that the circuit is very complex, and from material from the substrate in question, the problem will thus only consist of a conductivity type opposite to the shell. part of the management relocated to another. Especially in the Case of an integrated circuit is of course with 35 Failure of an element, regardless of whether it is the first the second or the third transistor is lost, the entire circuit. There is another possibility The invention relates to a protective scarf therein for the protective transistors on the one hand device for an integrated circuit, the two iso- and the transistors to be protected on the other hand lierschicht - field effect transistors opposite 40 different insulation layer thicknesses (oxide thicknesses) to Conductivity type (complementary IGFET). use in such a way that the protective circles guide, according to the generic term of claim 1. if the input voltage has a certain critical IGFET have reached an intermediate value due to the over the channel (US-PS 33 95 290). This iso-method, which is arranged between the gate electrode and the substrate, has the obvious disadvantage that it forms a layer with an extremely high input resistance. 45 Special care in the manufacture of the under-So that the transistor requires oxide layers of different thicknesses with practicable voltage, since these values can be operated, the insulating layer must be precisely controlled so that the thicknesses are relatively thin. However, if this position becomes correspondingly expensive,
A large voltage is applied to the thin insulating layer. Accordingly, the object of the invention is to be destroyed, so that the transistor 50 breaks down a protective circuit which is as simple as possible. Add a high voltage to the gate electrode, at which the protective effect cannot depend on the electrode, either by applying an input breakdown voltage of a high amplitude operating signal in the reverse direction or by storing a protective diode. static charge. Because of the high input The invention solves this problem by the im input impedance of the transistor (typically a protective circuit,
carry the input resistance more than 10 ¹⁴ ohms The invention has the advantage that the protective and the input capacitance in the order of magnitude of the circuit no longer ^{depends on the voltage breakdown 10 ~ 12} Farad) even a small static charge (Zener effect) is dependent on a protective diode and it is converted into a high voltage at the gate electrode - the relative gate Voltage of the transistors of the insetzt. 60 integrated circuit is therefore essentially reliable There are already different protection circuits for siger than before on low values (in the size IGFET known, a protective circuit of the initial order of 1 volt, based on the supply mentioned Type (for a NOR element of the CMOS type voltages of the circuit) limited. It was with three inputs) e.g. B. from "Electronics Review", namely found that so far in particular with one Vol. 40, No. 8, pages 48-49. The activation of a rapid sequence of glitches at the circuit unit according to the polarity of the unwanted signals in gear the reverse breakdown voltage of the only one Forward direction or in breakdown operation diode could become increasingly larger, so that protective diode between gate electrode and finally a dangerous value for the transistors