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DE19983687T1 - Verarbeitung geordneter Datenanforderungen an einen Speicher - Google Patents

Verarbeitung geordneter Datenanforderungen an einen Speicher

Info

Publication number
DE19983687T1
DE19983687T1 DE19983687T DE19983687T DE19983687T1 DE 19983687 T1 DE19983687 T1 DE 19983687T1 DE 19983687 T DE19983687 T DE 19983687T DE 19983687 T DE19983687 T DE 19983687T DE 19983687 T1 DE19983687 T1 DE 19983687T1
Authority
DE
Germany
Prior art keywords
memory
data requests
ordered data
processing ordered
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19983687T
Other languages
English (en)
Other versions
DE19983687B4 (de
Inventor
John Fu
Dean Mulla
Gregory S Mathews
Stuart E Sailer
Jeng-Jye Shaw
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE19983687T1 publication Critical patent/DE19983687T1/de
Application granted granted Critical
Publication of DE19983687B4 publication Critical patent/DE19983687B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
DE19983687T 1998-10-30 1999-10-18 Verarbeitung geordneter Datenanforderungen an einen Speicher Expired - Fee Related DE19983687B4 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/183,519 US6381678B2 (en) 1998-10-30 1998-10-30 Processing ordered data requests to a memory
US09/183,519 1998-10-30
PCT/US1999/024362 WO2000026742A2 (en) 1998-10-30 1999-10-18 Processing ordered data requests to a memory

Publications (2)

Publication Number Publication Date
DE19983687T1 true DE19983687T1 (de) 2001-11-22
DE19983687B4 DE19983687B4 (de) 2008-09-11

Family

ID=22673147

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19983687T Expired - Fee Related DE19983687B4 (de) 1998-10-30 1999-10-18 Verarbeitung geordneter Datenanforderungen an einen Speicher

Country Status (7)

Country Link
US (2) US6381678B2 (de)
CN (1) CN1208723C (de)
AU (1) AU1122400A (de)
DE (1) DE19983687B4 (de)
GB (1) GB2358941B (de)
TW (1) TW486628B (de)
WO (1) WO2000026742A2 (de)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6381678B2 (en) 1998-10-30 2002-04-30 Intel Corporation Processing ordered data requests to a memory
TW449695B (en) * 1999-11-26 2001-08-11 Via Tech Inc PCI data reading system for using reading requirement pipe and its method
US6826573B1 (en) 2000-02-15 2004-11-30 Intel Corporation Method and apparatus for queue issue pointer
US6832308B1 (en) 2000-02-15 2004-12-14 Intel Corporation Apparatus and method for instruction fetch unit
US6665776B2 (en) * 2001-01-04 2003-12-16 Hewlett-Packard Development Company L.P. Apparatus and method for speculative prefetching after data cache misses
US7487330B2 (en) * 2001-05-02 2009-02-03 International Business Machines Corporations Method and apparatus for transferring control in a computer system with dynamic compilation capability
US20030137519A1 (en) * 2002-01-22 2003-07-24 Nazanda Rima M. Method and apparatus to handle multiple requests to different memory agents
US7334086B2 (en) * 2002-10-08 2008-02-19 Rmi Corporation Advanced processor with system on a chip interconnect technology
US8601606B2 (en) 2002-11-25 2013-12-03 Carolyn W. Hafeman Computer recovery or return
US7139879B2 (en) * 2003-07-24 2006-11-21 International Business Machinces Corporation System and method of improving fault-based multi-page pre-fetches
US7870342B2 (en) * 2003-07-24 2011-01-11 Marvell International Ltd. Line cache controller with lookahead
US20050039016A1 (en) * 2003-08-12 2005-02-17 Selim Aissi Method for using trusted, hardware-based identity credentials in runtime package signature to secure mobile communications and high-value transaction execution
US8117392B2 (en) * 2003-10-22 2012-02-14 Intel Corporation Method and apparatus for efficient ordered stores over an interconnection network
US7281120B2 (en) * 2004-03-26 2007-10-09 International Business Machines Corporation Apparatus and method for decreasing the latency between an instruction cache and a pipeline processor
US7284092B2 (en) * 2004-06-24 2007-10-16 International Business Machines Corporation Digital data processing apparatus having multi-level register file
US7181575B2 (en) * 2004-09-29 2007-02-20 Hewlett-Packard Development Company, L.P. Instruction cache using single-ported memories
US7917731B2 (en) * 2006-08-02 2011-03-29 Qualcomm Incorporated Method and apparatus for prefetching non-sequential instruction addresses
JP2011028736A (ja) * 2009-07-02 2011-02-10 Fujitsu Ltd キャッシュメモリ装置、演算処理装置及びキャッシュメモリ装置の制御方法
US20110022802A1 (en) * 2009-07-27 2011-01-27 Arm Limited Controlling data accesses to hierarchical data stores to retain access order
US8700646B2 (en) * 2009-08-12 2014-04-15 Apple Inc. Reference file for formatted views
US8775700B2 (en) * 2011-09-29 2014-07-08 Intel Corporation Issuing requests to a fabric
US9098418B2 (en) 2012-03-20 2015-08-04 Apple Inc. Coordinated prefetching based on training in hierarchically cached processors
US9971694B1 (en) 2015-06-24 2018-05-15 Apple Inc. Prefetch circuit for a processor with pointer optimization
US9904624B1 (en) 2016-04-07 2018-02-27 Apple Inc. Prefetch throttling in a multi-core system
US10180905B1 (en) 2016-04-07 2019-01-15 Apple Inc. Unified prefetch circuit for multi-level caches
US10331567B1 (en) 2017-02-17 2019-06-25 Apple Inc. Prefetch circuit with global quality factor to reduce aggressiveness in low power modes
US10380034B2 (en) 2017-07-14 2019-08-13 International Business Machines Corporation Cache return order optimization
US20250077435A1 (en) * 2023-08-30 2025-03-06 Samsung Electronics Co., Ltd. System and method for adaptive prefetch for memory device

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5247649A (en) * 1988-05-06 1993-09-21 Hitachi, Ltd. Multi-processor system having a multi-port cache memory
EP0348628A3 (de) * 1988-06-28 1991-01-02 International Business Machines Corporation Cache-Speicheranordnung
US5307477A (en) * 1989-12-01 1994-04-26 Mips Computer Systems, Inc. Two-level cache memory system
JP2549256B2 (ja) * 1992-12-01 1996-10-30 インターナショナル・ビジネス・マシーンズ・コーポレイション 浮動小数点プロセッサへデータを転送する方法及び装置
US5544342A (en) * 1993-06-30 1996-08-06 International Business Machines Corporation System and method for prefetching information in a processing system
US5553276A (en) * 1993-06-30 1996-09-03 International Business Machines Corporation Self-time processor with dynamic clock generator having plurality of tracking elements for outputting sequencing signals to functional units
US5826052A (en) * 1994-04-29 1998-10-20 Advanced Micro Devices, Inc. Method and apparatus for concurrent access to multiple physical caches
US5724533A (en) * 1995-11-17 1998-03-03 Unisys Corporation High performance instruction data path
US6012134A (en) * 1998-04-09 2000-01-04 Institute For The Development Of Emerging Architectures, L.L.C. High-performance processor with streaming buffer that facilitates prefetching of instructions
US6381678B2 (en) 1998-10-30 2002-04-30 Intel Corporation Processing ordered data requests to a memory

Also Published As

Publication number Publication date
GB2358941B (en) 2003-07-23
CN1411575A (zh) 2003-04-16
WO2000026742A3 (en) 2000-08-10
US20010044881A1 (en) 2001-11-22
DE19983687B4 (de) 2008-09-11
AU1122400A (en) 2000-05-22
GB0109917D0 (en) 2001-06-13
US6381678B2 (en) 2002-04-30
US6725339B2 (en) 2004-04-20
TW486628B (en) 2002-05-11
CN1208723C (zh) 2005-06-29
GB2358941A (en) 2001-08-08
US20020073284A1 (en) 2002-06-13
WO2000026742A2 (en) 2000-05-11

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8125 Change of the main classification

Ipc: G06F 12/12

8607 Notification of search results after publication
8364 No opposition during term of opposition
R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee

Effective date: 20110502