DE19950563A1 - Process for cleaning a monocrystalline silicon semiconductor wafer - Google Patents

Abstract

The invention relates to a method for cleaning platinum impurities or other metal and/or rare earth metal substances from a monocrystalline silicium semi-conductor disk (1). A getter layer (15) is produced on a main surface by application of predefined ions. Non-desired substances, together with inserted ions, are gettered to crystal dislocations in a temperature treatment step to form complexes. Said getter layer (15) is removed from the main surface in a final wet chemical etching step.

Description

The invention relates to a method for cleaning a monocrystalline silicon semiconductor wafer from metal and / or rare earth metal substances according to the preamble of Claim 1.

Conventional microelectronic memory elements (DRAMs) mostly use oxide or nitride layers as the storage dielectric, which have a dielectric constant of at most about 8. To reduce the size of the storage capacitor and to manufacture non-volatile memories (FRAMs), "new" capacitor materials (dielectrics or ferroelectrics) with significantly higher dielectric constants are required. For this, from the generic publication "New Dielectrics for Gbit Memory Chips" by W. Hönlein, Phys. Bl. 55 (1999), pages 51-53 the capacitor materials Pb (Zr, Ti) O ₃ [PZT], SrBi ₂ Ta2O ₉ [SBT], SrTiO ₃ [ST] and (Ba, Sr) TiO ₃ [BST] are known .

The use of these new high-epsilon dielectrics / ferroelectrics presents problems for various reasons. First of all, these new materials can no longer be combined with the traditional electrode material (poly) silicon. Therefore, inert electrode materials such as Pt or conductive oxides (e.g. RuO ₂ ) must be used. Furthermore, a diffusion barrier (eg made of TiN, TaN, Ir, IrO ₂ and Mo Si ₂ ) must be inserted between the electrode material and the conductive connection structure (plug) to the transistor.

After all, building such structures requires the Ab the new high-epsilon dielectrics / ferroelek trika in an oxygen atmosphere and that - usually  multiple - annealing of the already partially processed Si semiconductor wafer at temperatures above 550 ° C.

The use of these new substances (metals and sel earth metals) for the high-epsilon dielectric / ferroelek trikum, the electrodes and the barrier layer in connection with the need to favor high diffusion processes Having to use process temperatures means in the Practice a significantly increased contamination or contact minimization risk of the Si semiconductor wafer during production.

A major problem in this context is the contamination of the silicon crystal with platinum. Even relatively small amounts of platinum in silicon can lead to a reduction in the charge carrier lifespan by orders of magnitude. With certain components, such as SIPMOS components, this fact is exploited by specifically induced platinum impurities to reduce the service life of minority charge carriers in a targeted manner. In the case of other components, however, undesirable higher platinum impurities, ie <10 ¹² atoms / cm ^{2, can} already lead to total failures of the components. In addition to process-related contamination, cross-contamination by the devices (vacuum tweezers, storage plates, chucks) itself can occur and also contaminate the back of the wafer.

Since platinum diffuses relatively quickly through interstitial spaces in the silicon at temperatures from 550 ° C, temperature treatment steps in component manufacturing processes that use higher temperatures can lead to platinum impurities present in the vicinity of the wafer penetrating into the crystal or already in the Diffusing crystal present platinum impurities into the component regions and thus making them unusable. Extensive cleaning tests on specifically contaminated silicon wafers (spin-on solutions) have shown that platinum in particular can no longer be completely removed from the silicon surface. A kind of re-accumulation occurs, in which the same contamination of 3 × 10 ¹² atoms / cm ² platinum is still measured on selectively contaminated silicon wafers after removal of up to 5 µm silicon. Even complexing agents such as TEFO, which are added to the etching solutions, have so far not achieved the desired result.

It has long been known undesirable substances getter in semiconductor crystals, d. H. to generate targeted interferences, such as implanted foreign atoms or ions, from among themselves and / or with the atoms of the host lattice formed complexes, crystal dislocations or son crystal defects or the like far from the building element region.

A getter process is known from U.S.-A-5,223,734 which after the component manufacture on a front a protective layer made of BPSG or PSG to apply and using the back of the wafer chemical-mechanical planarization and to apply a getter substance such as phosphorus and in insert the back of the wafer. Then the Wafers are subjected to a thermal treatment in order to Drive substance deeper into the wafer and build up mobile contaminants, such as platinum, on the phosphor getter To initiate centers. Because of this procedure two things Getter centers, namely the chemical one mechanical planarization generated dislocations and to of which the phosphor sturgeon introduced by the diffusion places can be generated unwanted substances effizi ent beetter.

A getter technique is also known from U.S.-A-5,840,590 knows, in which helium ions implan in a silicon wafer animals that have the property of being in the crystal larger complexes together. A subsequent tempe  temperature treatment step causes outgassing of the helium Inclusions from the crystal, so that relatively large empty space len or inclusions remain in the crystal, at their inner surfaces free silicon bonds ("dangling bonds ") remain, which act as efficient getter centers.

Both of the methods mentioned have the property that at ih rer application in component manufacturing processes a region the semiconductor wafer, usually the back, specifically is sacrificed in order to allow undesirable foreign substances into it gladly, while in a region remote from it functional hige components are manufactured. However, from ver be desirable for various reasons, the undesirable Remove all substances from the semiconductor crystal. On the one hand, those captured by getter technology can Foreign atoms under certain external influences, such as pressure or temperature, released from the getter centers again and diffuse into the device region so that they subsequently affect the functionality of the components can be pregnant. On the other hand, you get the possibility all regions of the wafer and thus also the wafer Reverse side for the production of components usable to ma chen.

It is accordingly an object of the present invention to provide a ver drive to cleaning a monocrystalline silicon half conductor disc of metal and / or rare earth substances specify which of the undesirable substances entirely be removed from the semiconductor crystal.

This task is characterized by the characteristics of the Claim 1 solved.

Accordingly, such a cleaning process is characterized in that

• A near-surface getter layer is generated, that ions of at least one specific element by mind least one main surface of the semiconductor wafer into one near-surface zone,
• - The metal and / or rare earth substances and the introduced ions in a temperature treatment step Crystal dislocations gettered to form complexes become,
• - The getter layer of in a wet chemical etching step the at least one main surface is removed.

This method is particularly efficient in the case of platinum as an impurity and phosphorus and / or boron as the element of the ions introduced. This is based on the knowledge that the introduction of P ⁺ or B ⁺ ions in the silicon crystal generates dislocations and the introduced P ⁺ ions or the B ⁺ ions form complexes with the platinum atoms, preferably at the dislocations which can be removed from the main surface of the semiconductor wafer in the subsequent etching step, for example using an HF / HNO ₃ mixture and, if appropriate, an aftertreatment with HNO ₃ .

The ions can be introduced by plasma doping (plasma doping) or by ion implantation. Plas madoping can generally achieve a higher surface concentration. An ion implantation is carried out, for example, with a dose of 20 ¹⁸ -10 ²⁰ atoms / cm ² .

After the ions have been introduced, a temperature treatment is carried out step in which the present in the semiconductor crystal Diffuse platinum atoms and diffuse with the ones brought ions to the dislocations more or less larger complexes together.  

The method according to the invention can be used as an isolated one Cleaning process applied to a semiconductor wafer the. However, it can also be used in a processing process Nes semiconductor device can be integrated, with one The main surface of a silicon semiconductor wafer is a semi-lead terbauelement is processed and in the course of the process tion on the other main surface according to the invention Cleaning process is carried out. Advantageously can the temperature treatment step to a suitable ten point in time, so that he at the same time Getters of foreign substances and one in the process tion of the semiconductor device provided function fills.

The invention is illustrated below with the aid of an embodiment game of processing a DRAM memory cell explained. The single figure is a schematic of the layer follow a DRAM formed in a Si semiconductor wafer Memory cell with switching transistor and high epsilon or ferroelectric stack capacitor shown.

An N-channel MOS transistor is built up on a p-doped Si semiconductor substrate 1 by means of conventional planar technology (layer deposition, layer structuring using lithography and etching techniques, layer doping).

An n ⁺ -doped drain region 2 is separated from an n ⁺ -doped source region 3 via an intermediate channel 4 made of substrate material. A thin gate oxide layer 5 lies above the channel 4 . A polysilicon gate electrode 6 is attached to the gate oxide layer 5 .

Above the described MOS transistor 2 , 3 , 4 , 5 , 6 , a cover oxide layer 7 is deposited, which comprises a contact hole 8 . The contact hole 8 is filled with an electrical connection structure 9 (so-called "plug") consisting of polysilicon.

Structure and method of manufacture of the structure shown are known. Instead of the MOS transistor 2 , 3 , 4 , 5 , 6 shown here , a bipolar transistor or another monolithic semiconductor functional element can also be provided.

A capacitor 10 is realized above the cover oxide layer 7 .

The capacitor 10 has an inner electrode 11 (so-called “bot tom electrode”), an upper electrode 12 and, in between, a high-epsilon dielectric / ferroelectric 13 .

The high-epsilon dielectric / ferroelectric 13 , for example PZT, SBT, ST or BST, is deposited by a MOD (metal organic deposition), a MOCVD (metal organic chemical vapor deposition) process or a sputtering process.

After the deposition of the high-epsilon dielectric / ferroelectric material 13 , this must be repeatedly annealed in an oxygen-containing atmosphere at temperatures of approximately 550-800 ° C. (“conditioned”). To avoid an undesired chemical reaction of the high-epsilon dielectric / ferroelectric 13 with the electrodes 11 , 12 , these are made of Pt (or another sufficiently temperature-stable and inert material).

To produce the electrodes 11 , 12 , further deposition processes are required before and after the deposition of the high-epsilon dielectric / ferroelectric 13 .

In the above-mentioned tempering step z. B. Bi, Ba, Sr from the high-epsilon dielectric / ferroelectric 13 diffuse through the lower Pt electrode 11 . Furthermore, Pt has a high diffusibility in Si at temperatures above about 550 ° C. To protect the connection structure 9 , a continuous and highly conductive barrier layer 14 made of TiN, TaN, Ir, IrO ₂ , Mo Si ₂ or another suitable material is therefore provided below the lower Pt electrode 11 . The barrier layer 14 is generated by a deposition process (and possibly a subsequent tempering step), which is carried out according to the layer sequence shown before the deposition of the Pt electrodes 11 , 12 and the high-epsilon dielectric / ferroelectric material 13 .

All of the "new" substances (metals and rare earth metals) required for the capacitor and barrier layer structure could have come into direct contact with the above-mentioned deposition processes with the - usually exposed - back of the Si semiconductor wafer and have penetrated into the semiconductor substrate. In order to prevent these substances from diffusing in a subsequent temperature treatment step in the direction of the component regions and thus impairing them, a getter layer 15 is produced before such a temperature treatment step on the back of the Si semiconductor wafer. This getter layer 15 is produced, for example, by implanting phosphorus or boron ions to a depth close to the surface of the rear side of the semiconductor wafer. Typical implantation doses are in the range 10 ¹⁸ -10 ²⁰ atoms / cm ² , whereby the surface concentration should be an order of magnitude higher. Instead of an implantation, plasma doping can also be carried out.

The implantation of phosphorus and boron induces internal stress in the silicon crystal, through which dislocations are generated. These dislocations are the nucleus for Pt-P or Pt-B complexes. These complexes can be removed relatively easily in wet chemical solutions without platinum re-attaching to silicon. In this wet chemical etching step, for example, an HF / HNO ₃ mixture can be used. However, other acid mixtures, such as aqua regia, are also conceivable. Aftertreatment with HNO _{3 may} be desirable or necessary.

As already explained above, the high-epsilon dielectric / ferroelectric 13 must be repeatedly annealed in an oxygen-containing atmosphere at temperatures of approximately 550-800 ° C. These temperature treatment steps can be used in such a way that they simultaneously serve to ensure that the foreign substances diffuse to the getter centers in the cleaning process according to the invention. It is thus possible to carry out an ion implantation on the back of the wafer to produce a getter layer 15 before each temperature treatment provided for the component production, and after the temperature treatment step the getter layer 15 , or mainly the Pt-P complexes in the getter layer 15 can be removed by a wet chemical etching step. As a result, the temperature treatment steps required anyway in the processing of the semiconductor component can additionally be used in the getter process. In addition, of course, if desired and necessary, further cleaning steps according to the invention can be carried out. The getter layer 15 can accordingly be generated before, during or after the production of the MOS transistor 2 , 3 , 4 , 5 , 6 by ion implantation and removed by a wet chemical etching step, a temperature treatment step being always interposed.

Claims (10)

1. A method for cleaning a monocrystalline silicon semiconductor wafer ( 1 ) from metal and / or rare earth metal substances, characterized in that

• a near-surface getter layer ( 15 ) is produced by introducing ions of at least one specific element through at least one main surface of the semiconductor wafer ( 1 ) into a near-surface zone,
• the metal and / or rare earth metal substances and the ions introduced are gettered in a temperature treatment step at crystal dislocations within the getter layer ( 15 ) to form complexes,
• - In a wet chemical etching step, the getter layer ( 15 ) is removed from the at least one main surface.

2. The method according to claim 1, characterized in that

• - The substance to be removed is platinum and the element of the implanted ions is phosphorus and / or boron.

3. The method according to claim 1 or 2, characterized in that

• - The ions are introduced by implantation.

4. The method according to claim 3, characterized in that

• - The dose of the implantation is 10 ¹⁸ -10 ²⁰ atoms / cm ² .

5. The method according to claim 1 or 2, characterized in that

• - The ions are introduced by plasma doping.

6. The method according to any one of the preceding claims, characterized in that

• - In the wet chemical etching step, an HF / HNO ₃ mixture is used and, if appropriate, an aftertreatment with HNO _{3 is} carried out.

7. The method according to any one of the preceding claims, characterized in that

• - The process steps are carried out several times in succession.

8. A method for processing a semiconductor component on a main surface of a silicon semiconductor wafer ( 1 ), characterized in that

• - In the course of processing, a method according to one of claims 1 to 7 on the other main surface of the semiconductor plate ( 1 ) is carried out one or more times.

9. The method according to claim 8, characterized in that

• - At least one of the temperature treatment steps simultaneously fulfills a function in the processing of the semiconductor device.

10. The method according to claim 9, characterized in that

• - The semiconductor component is a memory component with ferroelectric dielectric and the at least one temperature treatment step serves simultaneously to condition the ferroelectric dielectric.