DE19935497A1 - Method and circuit arrangement for correcting memory errors - Google Patents

Abstract

Disclosed is a method in which information saved in the course of writing to a memory (9) is compared with the write information used in the writing procedure. If a discrepancy is detected, the previously used write information is inverted, the inversion is registered and the inverted information is rewritten to the memory unit (9) for the purpose of correcting memory errors which can occur in the course of programming or writing to a memory (1).

Description

The present invention relates to a method according to the Preamble of claim 1 and a circuit arrangement according to the preamble of claim 8 for correcting Memory errors that occur when writing or programming memory.

Today, they are predominantly used as program or data storage non-volatile FLASH memory used in the form of a external chips or with an integrated logic due to ih er erasability and programmability for maximum flexibility with retentive storage of the information without electrical Provide resources. Associated with this is the demand for the highest possible stability (endurance) with regard to the Number of possible write and delete operations and one data storage as long as possible (<10 years).

In order to be able to check the requirements described above, are used to ensure the quality and specification of the Memory appropriate test systems or test programs turned on sets, with the help of such defects can be checked which are reproducible. With various memory types, especially with FLASH memories but it comes to the stochastic occurrence of certain defects men. Such defects are based in particular on memory cells len, on an equal electrical load (stress) un react differently, causing it to store incorrectly can come from unwanted information. Such mistakes are called 'Erratic Bits' and can be identified by the in 'Test' not built into conventional test programs or can only be recorded by chance. In addition, the technological Possibilities are usually limited or not sufficient to reduce such errors to an acceptable error rate  ken, so that basically the need for an intelli procedures for recognizing and correcting 'Erratic Bits' exists.

The occurrence of 'erratic bits' will be briefly explained below with reference to FIG. 4, wherein a memory 1 with four matrix-like interconnected memory cells 5 is shown. Each de memory cell 5 is realized by a field effect transistor, the individual memory cells 5 being able to be addressed via word lines 6 and bit lines 7 . For programming or writing to a memory cell 5 , the gate connection of the desired memory cell 5 is driven by applying a control voltage to one of the word lines 6 , while the source or drain connection of the desired memory cell 5 is driven by applying a control voltage to one of the bit lines 7 . In the following, it is assumed that the memory cell 5 (a) shown in FIG. 4 is to be selected by applying corresponding control voltages. The memory cells which are connected to the word line 6 selected in this case (see FIG. 4, the memory cell 5 (b)), therefore necessarily also see the control or programming voltage with which the gate connection of the desired memory cell 5 ( a) is addressed. This programming voltage leads to such programming cells 6 , which are supposed to maintain their erased state, to a programming stress and, in the worst case, to an undesired programming. This stress is known as word line or gate disturb. The same applies to those memory cells which are located on the selected bit line (see FIG. 4, the memory cell 5 (c)) and are subjected to the appropriate programming voltage from the drain connection. In this case one speaks of a bit line or drain disturb. When selecting or addressing the memory cell 5 (a) in FIG. 4, erratic bits can thus be caused by the memory cells 5 (b) and 5 (c). In this case, only memory cell 5 (d) is safe from such an error.

'Erratic bits' show non-reproducible, massive fluctuations in the sensitivity to this stress, which is unavoidable, for example, in FLASH memories. The individual memory cells 5 of the memory 1 must therefore be monitored for the occurrence of 'erratic bits'. This can be done, for example, by comparing the write information with the information actually stored in the individual memory cells 5 . As is known, when an 'erratic bit' is detected, this or the corresponding memory cell 5 is deleted and again written or programmed with the desired write information. In this case, the deletion is sensibly limited to a minimal memory area around the 'eratic bit' in order to keep the effort of reprogramming as low as possible.

As a rule, however, such 'erratic bits' disappear not already after a deletion with subsequent he new programming, but it can be very many (even several hundred or a thousand) such deletions operations with subsequent reprogramming required his. This procedure of deleting and reprogramming is on the one hand very time consuming and on the other hand hides also the risk that due to the permanent load through the repeated deletion and programming processes too unprogrammed cells on the selected word and bit line device that is not affected by the individual deletion and programming instructions gears are detected, possibly a very high accumulation tive Disturb exposed in the worst case to egg ner reprogramming of these memory cells can result.

The present invention is therefore based on the object a method and a corresponding circuit arrangement for Correct memory errors, suggesting what to do before problems described can be eliminated and esp special 'erratic bits' reliably without influencing others Memory cells can be eliminated.  

This object is achieved according to the present invention by a Method with the features of claim 1 or a scarf solved with the features of claim 8. The Sub-claims each define preferred and advantageous Embodiments of the present invention.

The basic idea of the present invention is based on A memory error occurs, particularly an erratic Bits', in a specific storage unit or be the original write information matched memory field invert this storage unit and the storage unit to write again with the inverted write information ben. In this case, the fact of inversion is ignored notices what in particular in a corresponding bit of each memory field can take place.

Advantageously, even after the new description memory unit with the inverted write information tion the In actually stored in the storage unit formation verified again. Will continue after the renewed Programming an 'Erratic Bit' in the corresponding memory cher unit recognized, possibly several such Use erase / programming cycles to eliminate the error det. However, this case is very unlikely to be caused by empirically determined 'Erratic Bit' error rates confirm who that can.

It is particularly advantageous if before the first Programming process the programming or writing information is monitored for the occurrence of ones or zeros, especially for the occurrence of 'erratic bits' are critical to memory cells into which a binary '0' should be written, as this may be incorrect can be reprogrammed into a binary '1'. It should be there be started with a write information that a has a minimum number of zeros, i.e. H. owns the  desired write information more zeros than ones, the writer should start before the first write formation inverted and the previously described method be taken as a basis.

The present invention can in principle in all ways of programmable memories can be applied, whereby each but especially a use in the programming of non-volatile FLASH memory is advantageous. Likewise, So-called stucco-at errors well concealed or suppressed become. Furthermore, the invention can by a simple Algorithm and a reasonable amount of space in the Spei and in the corresponding control logic. In addition, the present invention ensures a reduction to acceptable error rates, furthermore with the Cor Correction of memory errors Effects on other memories cells can be minimized.

The invention is described below with the aid of a preferred embodiment Example with reference to the accompanying drawings explained in more detail.

Fig. 1 shows a diagram illustrating the underlying principle of the invention vorlie constricting,

A flow chart of Fig. 2 shows a method according to a preferred embodiment of the present invention,

Fig. 3 shows a simplified block diagram of a circuit arrangement according to a preferred embodiment of the present invention, and

FIG. 4 shows an illustration to explain the occurrence of so-called 'erratic bits'.

In Fig. 1 of the sequence of the method is exemplified for the correction of memory errors according to the present OF INVENTION dung reference to a preferred embodiment provides Darge, wherein the sections shown are also associated with steps S100-S106, which in more detail below un ter reference to FIG. 2 are explained.

First of all, it is assumed that the memory unit 9 to be written to has been erased, ie all memory cells of this memory unit 9 store the binary value '0'. Then, a desired write information or a desired code, in the present case the code '10110100', is written into the memory unit 9 . The subsequent verification of the values actually stored in the storage unit 9 shows that, for example, the penultimate stored bit corresponds to an 'erratic bit' (EB), ie the value '1' is erroneously stored instead of the value '0'. Such memory errors can be detected relatively easily by comparing the original write information with the information actually stored, errors z. B. by a logical XOR combination of the write information and the stored information, he can be averaged. It is not necessary to locate the 'er ratic bit', rather an integral determination of a memory error is sufficient. If an error was found in this way, the corresponding memory unit 9 is deleted again, the original write code is inverted and written again to the memory unit 9 . Then it is followed by a new verification of the written inverted write code. As shown in Fig. 1, the inversion of the write code is noted so that it is always known whether the original write code or the inverted version thereof is stored in the storage unit 9 . It is particularly advisable to use an additional bit 8 of the memory unit or of the memory field 9 for this purpose, which has the binary value '0' in the original state and is also inverted during the inversion.

The additional space required in the store is based on this after the smallest memory unit to be programmed. Each the larger this storage unit is, the smaller it is adding up area. For program memory applications are the units in general bursts (whole / half word lines), while for data storage the pro programming process to program memory units or blocks each are smaller on request and for example one byte or include a word.

In Fig. 2, the inventive method is shown again in accordance with a preferred embodiment in the form of a detailed flow chart.

With the start of the method or program, two variables i and INV are set to the value 0 (step S100). The variable i corresponds to a run variable which specifies the number of the memory block of the memory 1 to be written and can take values between 1 and N. The variable INV, on the other hand, can only assume the values 1 and 0 and denotes the fact whether the write code is inverted or not. The desired screaming information is then written into the memory block i (S101) and this is verified by reading out the information stored in the block i (S102). If it has been determined that there is at least one 'erratic bit', ie a discrepancy between the write information and the information actually stored (S103), the corresponding memory block i is deleted (S104), the write code or the write information is inverted (S105) , The inversion in the form of the bit 8 shown in FIG. 1 noted, ie INV = 1 set (S106), and the memory block i again described with the inverted write information (S101). This is followed by a repetition of steps S102 and S103 and, if appropriate, steps S104-S106 and S101. If no 'erratic bit' was found in the memory block to be written in step S103, it is checked whether all the memory blocks of the memory have already been processed (S107) and, if appropriate, the method is ended (S109). If this is not the case, the variable i is set to the next memory block and the variable INV to the value '0' (S108), and the next memory block is written with corresponding write information (S101) and subjected to the previously described method steps .

If an 'erratic bit' is recognized after the inversion of write information and the reprogramming of the corresponding memory block, further programming and erasing cycles must be carried out to eliminate or correct the corresponding memory error. However, this case is very unlikely. With a 1 megabit FLASH program memory, the 'Erratic Bit' error rate per programming cycle is approx. 0.1%. Since, according to the physical model, basically all memory cells of the memory can have an 'eratic bit', this results in a bit failure rate of 0.1% and assuming only one 'erratic bit' per chip failure. Failure rate of 10 ^-9 . 512 memory cells are written per programming process, so that an error rate of 0.512 × 10 ^-6 results for the probability of an erratic bit occurring in this cluster (or after an inversion of the recurrence).

As a rule, in step S101 with the writing one non-inverted write information started. However, in order to It is recommended to be able to lower the error rate from the outset itself, the writing information to be used at the beginning (non-inverted or inverted) depending on which of the two versions of the writing information is a mini times the number of zeros. The zeros are the ones for that Occurrence of 'Erratic Bits' critical values since the ent speaking memory cells easily by creating Write voltages for storing the value '1' to neighboring ones Memory cells can be reprogrammed. Inver  version of the write to be used in step S101 codes have a smaller number of zeros than the noninver version, should therefore already be in the first Write the corresponding memory block the inv version used to program the memory block become. In this case too, the inversion is in the ent the relevant bit of the respective memory block.

In Fig. 3, a simplified block diagram of a circuit arrangement for realizing the method described above Ver is shown.

A memory 1 to be programmed, for example a non-volatile FLASH memory, is controlled via a write or an input buffer 2 and a read or output buffer 3 by a control logic 4 , which in particular comprises a state machine for controlling the process sequence described above. In the write buffer 2 , the immediately previously used write code is temporarily stored, so that the control logic 4 memory errors can be determined by an AND comparison of the memory contents read out via the read buffer 3 of the previously described memory block with the write code stored in the write buffer 2 . If a deviation is found, the control logic 4 inverts the previously used write code, notes the inversion in the inversion bit (cf. bit 8 in FIG. 1), deletes the previously described memory block and writes this memory block with the inverted write code via the write buffer 2 . The inverted write code is in turn stored in the write buffer 2 for the subsequent verification. In general, the readout of the memory content of the memory block to be programmed should be carried out with a corresponding reserve for deleted memory cells.

Reference list

1

Storage

2nd

Write buffer

3rd

Read buffer

4th

Control logic

5

Memory cell

6

Bit line

7

Word line

8th

Identification bit

9

Storage unit
S101-S109 process step

Claims (13)

1. A method for correcting memory errors, comprising the steps

• a) writing to a specific memory unit ( 9 ) of a memory ( 1 ) with a specific binary write information,
• b) checking the information stored in the memory unit ( 9 ) as a result of step a) to determine a memory error, and
• c) correcting the memory error if a memory error has been determined in step b),

characterized by
that the memory error is corrected in step c),
that the write information used in step a) is inverted, the inversion is noted and the storage unit ( 9 ) is again written with the inverted write information. 2. The method according to claim 1, characterized in that in step b) the stored information is checked by reading it out of the memory unit ( 9 ) and comparing it with the write information used in step a). 3. The method according to claim 2, characterized in that in step b) a memory error is determined in that a logical link between the read out and stored binary information from the storage unit ( 9 ) and the binary cry used in step a) is formed and the existence of a memory error is inferred if at least one bit of the link result indicates a discrepancy between the write information and the stored information. 4. The method according to any one of the preceding claims, characterized in that the inversion of the write information in a specific bit in the memory unit ( 9 ) to be written is noted in step c). 5. The method according to any one of the preceding claims, characterized in
that the write information to be used is analyzed with regard to the number of bits contained therein with the binary value '1' or the binary value '0', and
that the write information to be used is inverted before step a), the inversion is noted and the inverted write information is subjected to steps a) to c) if the analysis has shown that the number of bits with the value '0 'is greater than the number of bits with the value' 1 '. 6. The method according to any one of the preceding claims, characterized in that after the inversion of the write information in step c), steps b) and c) are repeated with respect to the inverted write information written in the storage unit ( 9 ). 7. The method according to any one of the preceding claims, characterized in that steps a) to c) are repeated until a desired number of memory units ( 9 ) of the memory ( 1 ) have been written without detecting a memory error in step b). 8. Circuit arrangement for correcting memory errors,
with a writing device ( 2 ) for writing a certain storage unit ( 9 ) be a memory ( 1 ) with a certain binary write information, and
with a control device ( 4 ) for checking the information stored by the write device ( 2 ) in the memory unit ( 9 ) in order to determine a memory error,
characterized,
that the control device ( 4 ) is designed such that it corrects this upon detection of a memory error by inverting the write information used by the writing device ( 2 ), noting the inversion
and the write device ( 2 ) supplies the inverted write information for rewriting the memory unit ( 9 ) with the inverted write information. 9. Circuit arrangement according to claim 8, characterized in that the memory ( 1 ) is a non-volatile FLASH memory. 10. Circuit arrangement according to claim 8 or 9, characterized in
that a readout device ( 3 ) is provided for reading out the information stored in the memory unit ( 9 ), and
that the control device ( 4 ) for determining a memory error compares the information read by the readout device ( 3 ) and stored in the memory unit ( 9 ) with the write information used by the write device ( 2 ). 11. Circuit arrangement according to claim 10, characterized in that the control device ( 4 ) for determining a memory error has logic linking means which read out the binary information read out by the readout device ( 3 ) from the memory unit ( 9 ) and by the write device ( 2nd ) subject the binary write information used to a logic operation, the control device ( 4 ) concluding that there is a memory error if at least one bit of the result of the operation provided by the logic operation means indicates a discrepancy between the write information and the stored information. 12. Circuit arrangement according to one of claims 8-11, characterized in that the writing device ( 2 ) after inverting the cry binformation notes this inversion in a specific bit in the memory unit ( 9 ) to be written. 13. Circuit arrangement according to one of claims 8-12, characterized in
that the control device ( 4 ) is designed such that it analyzes the write information to be used with regard to the number of bits contained therein with the binary value '1' or the binary value '0', and
that the control device ( 4 ) is designed such that it inverts the write information to be used, notes the indentation and supplies the inverted write information to the write device ( 2 ) for writing to the memory unit ( 9 ) of the memory ( 1 ) if the analysis shows has that the number of bits with the value '0' in the write information to be used is greater than the number of bits with the value '1'.