DE19905282A1 - Three level inverter branching system, comprises multi-branch command circuit breaker, diode and capacitor assemblies - Google Patents

Abstract

The branching system connects a three level inverter assembly to command circuit breakers, diode and capacitor assemblies. Circuit breaker assemblies and the diodes are mounted in a non-parallel manner whilst the capacitors are branched in parallel with the diode assemblies. The supply voltage being controlled by a command unit.

Description

The invention relates to an arrangement for switching on Relief of 3-level inverters according to the Preamble of claim 1.

The well-known 3-level inverters (in: EPE Journal, Vol. 4, No 2, June 1994, Y. Tadros, S. Salama, Th. Schütze: "Three Level IGBT Inverters for Industrial Drives and Traction Applications", page 38 ff., Fig. 3) in IGBT technology (Insulated Gate Bipolar Transistor) consist of four IGBTs per branch with four anti-parallel diodes and two clamp diodes.

In high performance applications, the use of well-known 3-level inverter by the occurring Losses and especially the start-up losses as well due to the size of the components to be used (especially the DC capacitors) and  of the inductive connections between the Components without relief and / or clamp Circuits very difficult.

DE 196 36 248 C1 describes a method for Switching relief of an IGBT known with which at 2- Level inverters resulting from resistors Switching losses are avoided.

For high performance applications, however, the 3-level Inverters due to the possible higher converter voltage is more suitable and becomes accordingly used more and more.

So far there are no solutions for 3-level changes become known to judges with whom little effort (without Resistance) the switch-on losses are reduced can.

To reduce the switch-on losses and to limit the steepness of the inrush currents in 3-level inverters with power semiconductors that can be switched off, it is known to use a concentrated inductance (choke coil) and a clamp circuit consisting of a clamp condenser between the intermediate circuit capacitors and the power semiconductors sator and a diode and a discharge resistor to provide. In particular at higher switching frequencies, this results in high losses, in particular due to the discharge resistance (in: ETG technical reports, Bad Nauheim, May 1998, Dr. H. Grüning, "The GCT strengths of GTO and IGBT technology in one unit" , Page 89, Fig. 14).

The object of the invention is a generic Develop an arrangement that ensures that Switch-on losses reduced and the steepness of rise of the inrush currents for 3-level inverters in High performance applications are limited.

The object is achieved with the features of claim 1 solved. The arrangement is then known records that the controlled switch and that anti-parallel connected diode with the one in series switched capacitor the respective intermediate circuit Capacitors at least on the motor side Converter side are connected in parallel, such that in the steady state the in series Capacitor is charged up to a voltage level, which is larger than that on the respective DC link Capacitor applied voltage.

The clamp circuit provided according to the invention can be brought very close to the power semiconductors be so that the inductance of the electrical Connections reduced due to the short cable routing becomes. The clamp capacitors to be used can be chosen much smaller than that DC link capacitors.

The controllable are used to discharge the capacitors Switch shortly before the power is switched off semiconductors in the phase branch of the inverter switched on. To avoid switch-off losses when the controllable switches are switched off, the Currents in these switches by turning off the Power semiconductors in the 3-level inverter commutates. This turns the electricity out of controllable Switches commutated in the diodes, so that one  lossy shutdown of the controllable switches is avoided. The losses in the taxable Switches are even at high switching frequencies negligible small.

Advantageous developments of the invention are in the Subclaims described.

The invention is described below with reference to a drawing in one embodiment of the arrangement for Start-up relief of 3-level inverters closer explained. Show it:

Fig. 1 is a schematic illustration of a circuit arrangement for a 3-level inverter according to the prior art,

Fig. 2 is a schematic illustration of the circuit arrangement of FIG. 1 with the arrangement according to the invention,

Fig. 3 is a schematic representation of a circuit arrangement for several 3-level inverters with the arrangement according to the invention on a 3-level intermediate circuit capacitor and

Fig. 4 is a schematic representation of a further embodiment of the invention for a circuit arrangement according to FIG. 3.

Fig. 1 shows a schematic representation of the circuit diagram of a 3-level inverter according to the prior art. Each inverter branch (phase branch) is formed from four switchable power semiconductors (IGBT) T1 to T4, which are each connected to a control unit via pulse amplifiers, four antiparallel diodes D1 to D4, two zero diodes D _U1 , D _U2 and intermediate circuit capacitors C ₁ , C ₂ , to which a voltage U _d / 2 is applied. The DC voltage U _d / 2 can be applied to the output terminals of the inverter via the positive tap (T1 and T2 are switched on), via the central tap 0 (T2 and T3 are switched on) or via the negative tap (T3 and T4 are switched on) .

The arrangement according to the invention is shown in FIG. 2. The circuitry according to the invention arranged in the intermediate circuit does not require any lossy resistors and thus ensures that switching-on losses are largely avoided in 3-level inverters in high-performance applications such as rail-powered vehicles. By intelligently controlling the switches T _c1 , T _c2 , the losses in these switches can also be reduced considerably.

In FIG. 2, for low-loss switch-on relief according to the invention, the load side is connected in parallel with the intermediate circuit capacitors C ₁ , C ₂ combinations, each consisting of a switch T _c1 , T _c2 and an anti-parallel diode D _c1 , D _c2 and one series connected capacitor C _c1 , C _{c2 are} formed.

In the steady state, the capacitors C _c1 and C _c2 are charged up to the voltage level Uc _c1 and Uc _c2 <U _d / 2, for example to a voltage level of 1.1 U _d / 2. The switches T _c1 and T _c2 are turned on to partially discharge the capacitors C _c1 and C _c2 to limit the direct voltages Uc _c1 and Uc _c2 . The switching losses of the switches T _c1 and T _{c2 can be} considerably reduced by intelligent control of the switches T _c1 and T _c2 . For example, the switch T _c1 or the switch T _{c2 can be} switched on before one of the current-carrying switches T1, T2 or T4 is switched off in the commutation process. The current from the controllable switches T _c1 , T _c2 is commutated when the current-carrying switch is switched off into the diodes D _c1 , D _c2 , so that lossy switching off of the controllable switches T _c1 , T _{c2 is} avoided.

In Fig. 3 a variant of the arrangement according to the invention for a plurality of 3-level inverter in a 3-level Capacitors- intermediate circuit is shown, as they can be used for example for the drive power converter of high speed trains as Transrapid.

Fig. 4 shows a further embodiment of the arrangement according to the invention for several 3-level inverters on a 3-level capacitor intermediate circuit, in the common relief choke coils L _S1 and L _{S2 are used} for the line-side and motor-side converters.

List of reference symbols

C ₁

, C ₂

DC link capacitors
C _c1

to C _c4

Capacitors
D1 to D4 diodes
D _c1

to D _c4

Diodes
D _U1

, D _U2

Zero diodes
L _S1

to L _S4

Inductors
T1 to T4 power semiconductors (IGBT)
T _c1

to M _c4

controllable switches
U _d

/ 2 DC voltage
Uc _c1

to Uc _c4

tension
0 central tap

Claims (3)

1. Arrangement for the switch-on relief of 3-level inverters with power semiconductors that can be switched off and with intermediate circuit capacitors, with a switch-on relief choke coil, using a circuit comprising a controlled switch and a diode connected in antiparallel to it, to which a capacitor is connected in series, thereby characterized in that the respective controlled switch (T _c1 , T _c2 , T _c3 , T _c4 ) and the diode (D _c1 , D _c2 , D _c3 , D _c4 ) connected in antiparallel with the capacitor (C _c1 , C _c2 , C _c3 , C _c4 ) the respective intermediate circuit capacitors (C ₁ , C ₂ ) are connected in parallel at least on the motor-side converter side in such a way that in the steady state the capacitor (C _c1 , C _c2 , C _{c3, c4} C) charged to a voltage level that is greater than that at the respective intermediate circuit capacitor (C _1, C ₂₎ applied voltage (U _d / 2). 2. Arrangement according to claim 1, characterized in that the wiring of the intermediate circuit capacitors (C ₁ , C ₂ ) is arranged on the side of the line-side and the motor-side converter. 3. Arrangement according to claims 1 and 2, characterized in that the controlled switches (T _c1 to T _c4 ) are controlled such that one of the controlled switches (T _c1 to T _c4 ) is turned on just before one of the current-carrying switches ( T1 to T4) is switched off.