DE19851082A1 - Digital remote control signal transmission - Google Patents

Abstract

To limit the task of the reception, a transmission step frequency is limited in a buffer circuit (1) of a receiver by dividing the signals to transmission blocks of a predetermined size. The transmission blocks are transmitted to the buffer circuit with a higher transmission rate than the transmission step frequency, so that the entire calculation power freed up by the limited reception task can be utilized for the signal processing. The method involves transmitting digital remote control signals from a transmitter to a receiver (1, 2) which contains a buffer circuit (1) at its input for the reception of the digital remote control signals and for their transmission to a processor (2), having a predetermined divided computational power for the reception of the transferred signals and their processing. To limit the task of the reception, the transmission step frequency is limited in the buffer circuit by dividing the signals to transmission blocks of a predetermined size. Before sending out the signals, the transmitter codes their logical condition in form of a pulse which has a specific position in a period (T) of predetermined duration. The transmission blocks are transmitted to the buffer circuit with a higher transmission rate than the transmission step frequency, so that the entire calculation power freed up by the limited reception task can be utilized for the signal processing.

Description

The invention relates to a method for transmission of digital remote control signals from a transmitter to a remote control receiver in general, especially for remote control of door locks conditions in vehicles.

As is known, the user of a key or Remote control device at any time to operate a Door lock the transmission of infrared or radio Trigger signals and that at the location of the door lock installed receivers must be able to receive them.

To limit the power consumption of the receiver, z. B. spared the vehicle battery at a standstill there is a microprocessor in the receiver with an RF input circuit normally in energy-saving standby mode and is switched on by a HF circuit activated on the aisle if it after demo dulation of the RF signals a temporary bit sequence on the Detects the output side of the remote control. The HF scarf but can also be designed so that it in the Idle as standby with low power consumption acts by the input of a bit sequence from the Remote control signal sequence is detected, through which it ak is activated and switches to the activated state, in which the other remote control signals this Signal sequence can be received.

The HF circuit, which has a range of about 100 m can address, but also receives others Interference signals, such as. B. telemetry signals relating to the  Pressure of the vehicle's pneumatic systems or Signals for other vehicles, or remote control signals for garage doors, awnings and the like. The RF circuit can be activated and drives the microprocessor, which turns on the following remote control data analyzed and as foreign rejects signals before returning to standby mode returns.

Every reception of interference signals calls unwanted and unnecessary power consumption.

In addition, again using the example of the remote control of door locks, is the response speed of the Microprocessor regarding the execution of the commands problematic. The key or remote control device can namely a constantly transmitting radio transmitter very carry the short range of the door locks only then opens when the key user is in immediate Comes near the doors. It must be avoided here that the user clicks on an unlocked door lock "hits" because the remote control signal only very much received shortly before the actual opening process has been.

There are therefore difficulties with the Power Consumption Problem, Reak Problem speed, which is difficult with the first Is to reconcile, and also a third Problem that of security for addressing the Remote control signals become a long sequence of bits demands what opposes solving the second problem stands.

It also transmits the bits of remote Operation from the input circuit to the microprocessor triggered by the latter by this the input  circuit cyclically scans and there just every received bit reads. This task, in real time, requires an interruption of the running process in the Microprocessor with at least the same frequency as that of the transmission of the bits from the remote control device, so that the paradoxical situation arises that everyone Increase the transmission speed of the Remote control signals a reduction in Processing power of the microprocessor causes and an additional delay.

To remedy this with a solution for one acceptable compromise between the previously shown different difficult demands is a task the invention.

Based on a procedure for the transfer of digital remote control signals, each one logical state among many, of a transmitter to a receiver on the input side a buffer circuit for receiving the Remote control signals and for their transmission a processor with a predetermined split Computing power for the reception of the transmitted signals and their processing, is this task solved that in order to limit the task of receiving the Transmission step frequency from the input side Switching by dividing the incoming signals there limited to blocks of predetermined size and that in the transmitter before sending the signals whose logical state is encoded in the form of a pulse being a specific position in a period takes predetermined duration and the transmission blocks to the input circuit with a higher one Transmission rate as the transmission step frequency be transferred so the whole due to the restricted receiving task remaining free  Computing power essentially for signal processing device can be used.

Further features of the invention result from the Subclaims.

The method according to the invention has a number of Advantages. Since the simultaneous reading of the blocks in the input-side switching only occurs sporadically and the processor in the non-activated state only receives a sufficient signal current to Processing can avoid downtime processes of remote control signals now faster than expire so far.

When transmitting from the transmitter itself to the entrance term circuit receives due to the fact that just the position and not the form of the impulse for the logical state of each received signal specific is, the input circuit is a signal whose mean level is constant over the entire period, because the level is independent of the transmitted bit value. In this way the input circuit has so very simply using a reference level that is different from the Amplitude of the received pulses is dependent and because it represents a fixed part that defines an optimal detection threshold of the impulses allowed. This optimal threshold means a higher one Transmission speed of the remote control signals possible what an almost complete temporal Utilization as stated above, the Processing options of the processor allowed.

Successive signals can be directly and be transferred in the direction of flow, since even one Signal follow none with the same logical state Deviation from the medium level causes and thus the  Reception without activation is released. A Follow encryption before sending the signal and an appropriate decryption on receipt is therefore eliminated, in particular what the receiving side relieves and also simplifies the hardware allowed.

Preferably, if the signals are binary, each of the two logical states is in the form of a Encoded, at the beginning and at the End of the bit period and the duration of the pulse is on regulated half of the bit period.

Because the frequency spectrum that is used for sending and recognizing the waveform is necessary, in this case a Has fundamental frequency, which depends on the transmission frequency of each Signal is limited, so this can be up to about Functional limit of the various circuits increased become.

Since the input side circuit advantageously so is designed to be both active and Standby mode works in a power-saving manner, one after the other a large number of bit sequences from the transmitter for activation of the input circuit, and this will be until The processor receives a signal only periodically activated to receive at least one of the episodes and to recognize, and then the input side Switch to the active state for receiving the switch subsequent remote control signals.

Since both the transfer and the processing of the remote control signals to be executed with higher Speed can happen again, faster returned to standby and so the average electricity consumption can be reduced.  

The invention is based on the description below a preferred embodiment of the method under Explained with reference to the accompanying drawings.

Show it:

Fig. 1 shows schematically a transmitter of a remote hand for performing the method according to the invention,

Fig. 2 shows schematically a receiver in Zugehör aqueous vehicle,

Fig consisting of FIGS. 3A and 3B. 3 shows, as a function of time t, a transmission frame for a remote control signal and a frame for the drive command an input-side circuit of the receiver, and

Fig. 4 shows the coding of the remote control data.

A transmitter 39 of an arrangement for remote control according to FIG. 1 should be in the hand of the owner of a car so that he can lock and unlock the door locks of the car from a distance. A special circuit unit in the vehicle key or on a chip card is used for this.

The transmitter 39 includes a clock 30 , which supplies a sequential circuit 31 , which reads a remote control signal for the locking and unlocking of the car locks containing memory 32 . The memory controls an input of an exclusive OR gate 33 , which receives at its second input from the clock generator 30 a bit clock signal H with the period T, via the output of which a transmission circuit 34 , here an HF circuit, is controlled. The sequence circuit 31 is used in this example for locking and unlocking the locks, so it can always only cyclically give only one piece of information and the user of the transmitter 39 must therefore make his choice here and expressly enter a signal by using one of two Presses buttons 35 and 36 to control the sequential circuit 31 and thus one of the two available commands is selected.

The receiver shown in Fig. 2 is housed on the vehicle side to command the locking and unlocking of the door locks, not shown. The receiver comprises an input-side circuit 1 with an RF receiving circuit 13 , here tuned to 433.92 MHz, which supplies a transmission buffer circuit 14 , here a UART (Universal Asynchronous Receiver / Transmitter), which has a processor, here a microprocessor 2 connected, which analyzes and executes the remote control commands coming from the transmitter 39 . The control line 5 coming from the microprocessor controls an actuating element (adjusting element) for the locks, also not shown.

FIG. 2 shows a purely functional diagram, ie the UART 14 shown there can practically be integrated together with the microprocessor 2 to form a single IC module.

A line 3 , which can also be a bus of the above-mentioned IC module, enables the buffer circuit UART 14 to supply the microprocessor 2 with data signals, here binary data signals, which correspond to the received RF signals and have been detected by demodulation. In the opposite direction, a line 4 enables the microprocessor 2 to control the functional mode of the circuit 1 by means of a subassembly 11 in this circuit. The subassembly 11 can also act on the UART integrated in the microprocessor 2 . The buffer circuit UART 14 has a clock generator, not shown, which specifies the transfer clock to the microprocessor 2 .

The circuits 13 and / or 14 can adopt a mode in which they are fully actively controlled in order to recognize all remote control signals and a power-saving standby mode in which only a fraction of the beginning of the remote control signal is processed, that is to say recognized, in particular for this purpose serves to activate the circuit 1 for the reception of the next signal sequence.

The microprocessor 2 has a predetermined computing power, which is divided between the reception function of the signals transmitted by the buffer circuit 14 and their processing, ie detection and control for executing the incoming remote control signals.

For this purpose, the microprocessor 2 contains a subassembly 12 , which enables it to work either in the fully activated mode, in which it executes the remote control signals, or in standby mode with limited function and low power consumption, in which it detects an incoming remote control signal, the However, commands cannot execute.

In Fig. 3A, the format of a remote control information is shown. This essentially comprises the preamble, that is to say control characters 21 , 22 by which the circuit 1 and also the microprocessor are activated and a message or data field 24 specifying the information, ie here relating to the doors.

Furthermore, a protective distance is provided here in the form of a clock pulse pause 23 for switching the microprocessor 2 to the active state before receiving the data from the message field 24 .

In the preamble, the front part 21 contains a fixed bit sequence 20 , which is sent here eleven times. This repetition is due to the fact that here the standby mode of the RF circuit 13 does not consist, as could be done, of a static mode with limited power for recognizing the sequence 20 , but instead of a cyclical change between a "fully activated""State for receiving all information and a state" completely inactive "in which the incoming signals cannot be recognized at all.

In standby mode, the duration of the above active state is determined by a read window 25 of the outgoing RF signals, which is 4 ms with a repetition period of 40 ms. The transmitted sequence 20 lasts 4 ms, so that the front part 21 with eleven bit sequences 20 lasts exactly 44 ms. For this reason and regardless of the phase shift between the transmitted front part 21 and the repetition period of 40 ms for reading, there is a whole reading window 25 of the circuit 1 briefly within the part 21 , so that the bits of a sequence from the 11 sequences are recognized will. The part 22 of the preamble provided here is intended to enable additional filtering of the bit values of the incoming information.

The functioning of the receiver is described below in individual explained.  

According to the present method, the task of signal reception in the microprocessor 2 is reduced in order to have time in the central unit for the execution task, which receives a signal stream for the remote control in a cycle that is high enough to cover almost the total time in the central unit. More specifically, the transmission clock frequency of the input circuit 1 is limited by combining the signals received in the latter into transmission blocks of a predetermined size, thereby limiting the reception function of the microprocessor 2 and in the transmitter 39 before the signals are successively transmitted, the logic state thereof encoded in the form of a pulse which takes a certain position in the specified period T and which is transmitted to the input circuit 1 at a higher clock frequency than that of the message transmissions, so that essentially all of the computing power by the restriction the reception function has become available for the processing function.

Until a remote control signal arrives, the RF circuit 1 is in standby for blanking out each transmitted part 21 of the preamble. The detected signals, ie demodulated and represented in binary form, are transmitted to the microprocessor 2 for the purpose of detection. The RF circuit 1 is an input-side buffer, which is transparent with regard to the processing of the detection logic (preamble) of the remote control signals, because it shifts the detection of all signals that it detects in the microprocessor 2, including the sequence 20 that are its Functional mode controls. The sequence 20 can be predetermined and stored in the microprocessor 2 or it can be encoded according to a fixed law and recognized by agreement with this law.

If the sequence 20 is not recognized, the microprocessor 2 leaves the circuit 1 in standby mode. If so, the detection of the sequence 20 leads to the activation of the line 4 , so that the circuit 1 is set to the active mode via ( 11 ).

Since here the standby mode consists of a change between the states active 25 and inactive 26 ( FIG. 3B), the switchover to the pure active mode of the circuit 1 takes place in that the readout window 25 for the duration of remote control information the part 21 , amounting to 4 ms, is extended to the region 27 , or, if the recognition of the sequence 20 takes place only after the end of the window 25 of 4 ms, the microprocessor inevitably activates the additional window 27 of the desired duration, ie blocks each Switching circuit 1 into the inactive state.

The identification field 22 for the remote control is also received and processed by the microprocessor 2 . The field 22 is there to activate the microprocessor 2 only fully ( 12 ) if the remote control, after identification by the field 21 , specifies this. The field 22 contains predetermined data stored by the microprocessor, for example vehicle type, year of manufacture, modulation speed and the type of coding of the field 24 and others. Only when the data of the field 22 have been recognized does the microprocessor 2 switch to the fully active state via ( 12 ), in which it receives the data from the data field 24 of the remote control signals.

The receiver in this embodiment is a CMOS device, a technology in which the power consumption increases substantially linearly with the clock frequency (sub-assembly 12 ), not shown in detail here.

The switchover to standby mode takes place here by lowering the clock frequency. Switching between nominal frequency, active state and lower Frequency / standby is controlled by controlling a multi plex circuit with two inputs, the difference Liche clock frequency signals are assigned.

In another example, the consumption can be reduced by reducing the supply voltage or by switching off peripheral modules, ie modules that are not necessary for the detection of the field 21 and here also the field 22 .

After detection of the field 22 , the microprocessor 2 controls itself (transition 12 ) into the active mode and then evaluates the part 24 for activating the line 5 .

In general, one or more sub-assemblies of the remote control receiver, if it is designed for standby mode, can be activated at the same time or progressively. The preamble 21 and / or 22 is preferably worked by the processor 2 in standby mode, so that it can be fully activated after the receiver 1 has been activated or activated at the same time if it includes the standby mode.

In Fig. 4 the principle of coding of the bits sent by the transmitter 34 is shown, the time t on the abscissa and the amplitude A of the transmitted signals and the signal H of the clock generator on the ordinate are abge.

The transfer is asynchronous here, the bits from the memory 32 are transferred in blocks, four bits 1100 are shown here, framed by one START bit and one STOP bit. Eight clock steps are sent between these two control bits, ie in this example the amplitude of the output signal from the gate 33 has eight stages of the same width, the logic states of which occur in pairs. A bit period T with two stages or clock steps of different amplitudes is available for each bit to be sent. The values or states "0" and "1" of a remote control bit are coded with two steps or transmission bits, the levels of successive values namely 0.1 and 1.0. In other words, each period T contains a pulse of predetermined width, the position of which depends on the value or logic state of the bit to be transmitted.

STOP and START, the duration of which is only one cycle step corresponds to. have levels 1 and 0 and are chainable so that it represents the logical state "1" put. From this you can see that you are no longer up the binary logic is limited and every logical zu stood with from a certain number of states different levels (multi-levels) transmitted that can be done by giving everyone a specific position in the Bit period T is assigned. The given impulse width can also be different than T / 2. In this way is the mean of the one for each logical state multiplying signal equal to its peak value adorned with the factor of the shape of the pulse in the Period T, here 0.5.

The choice of the two positions of the pulse at the beginning and at the end of the period T, whether on one side or the other from the middle of the bit period T and with a regulation of the pulse duration to half the bit period T, enables simple coding of the from Memory 32 bits coming in every period T. If the bit to be coded has the value "0", this remains without influence on the exclusive-OR gate and the clock signal from the clock generator 30 passes through the gate 33 unchanged, ie it has a low level during the first half period (first Clock step), after which the signal reaches a high level in the second half period via a rising edge (second clock step). If, on the other hand, the bit value "1" is to be coded, the clock signal in gate 33 is reversed, so that the high level is now in the first half period. In this way, the pulse is positioned in the first or second bit half-period by conditional inversion ( 33 ) of the clock signal with the bit period T, depending on the bit to be transmitted. At the output ( 33 ) there is therefore a phase jump of 180 degrees if two bits to be sent are different.

As shown in Fig. 4, the states "0" and "1" each have rising or falling envelopes in the half-period of T. An envelope occurs between two periods T in the case of two consecutive identical logic states or bits; otherwise, a change in the bit value corresponds to a continuous level of the clock steps, namely the second and the first phase change in the two affected bit periods T, since the phase jump of 180 degrees is added to the natural phase change of 180 of the clock signal H.

Upon reception ( 1 ), the analog signal reconstructed via the HF circuit 13 (standard band) is integrated (classic RC) in order to have a stable reference voltage, as a result of which a detection threshold for the pulses is established, a threshold which corresponds to that received Instantaneous signal is compared. The reference level obtained here by integration is equal to the incoming peak value and therefore adapted to it, multiplied by the form factor, here 0.5. It would be more favorable to set a different detection threshold than the average level, especially in cases where the form factor should deviate from 0.5. It is then sufficient to amplify or attenuate the middle level according to a fixed factor, or in contrast to amplify the single instantaneous signal.

In this way, you have a stable and reliable reference threshold through integration over several periods T. Since the integration constant (RC) can also be limited because the control peak value is present in each period T, the reference level immediately follows the peak value received in each case, for example, if the user of the transmitter ( 39 ) moves quickly.

One can thus avoid logical complications (through each other) of the long bit sequences with identical bit values free "0" or "1", which means that the circuit structure in the Simplified transmitter and receiver. In the analog, because the detection of the incoming bits after an im mer optimal threshold, the duration can also each step cannot be shortened compared to one stable threshold at which the response of the Si gnaldetector would have to integrate sufficiently long to Turn off interference signals that make the decision at the Detection in one state more than in the other short could falsify early. In short, here is the Ampli tude the signal-to-noise ratio against interference signals via the opti male threshold increases, which means faster transfer is possible.

In addition, through the coding used each Sequence excluded the more than two steps has the same level, so that the presence of a Error is determined when the same level  lasts longer than one bit period T, i. H. at least three Steps.

In order to protect against errors even better, it is seen that each step at the output of the receiver 13 is scanned by a clock with a speed higher by a factor of 16 than the frequency of the clock steps, or the baud rate, after a brief deviation from START and select the value more commonly present in three central samples of each step.

The block with 1 byte clock steps is then in Paa ren decoded to the 4 bits of the original remote to receive service signal. The decoding of "0.1" again gives the logic state "0", while "1.0" results in the logical state "1". In an exclusive OR gates are the two steps of each pair checked different levels. Through this redundancy can alternatively add one by three following identical steps represented errors kor be rigged.

If a STOP bit arrives at UART 14 , this triggers an interruption in processor 2 in order to transmit the 4 bits received, which corresponds to a byte of clock steps. The step / bit decoding mentioned above can be carried out in UART 14 or in microprocessor 2 . For example, UART 14 can expose more than 4 remote control bits, for example two or four blocks of 4 bits, which are transmitted in parallel via a bus of the microprocessor. A serial transfer cannot be ruled out, since the time is saved by transferring one bit block and not a single bit, which leads to fewer interruptions in the microprocessor 2 and therefore less time is lost, if not every time the status information of every running process during processing and execution of the remote control must be saved again. Block-by-block transmission enables the average signal rate processed by the microprocessor to be increased.

At a transmission speed of 10 k clock steps per second, or bauds (T = 0.2 ms), there is an interruption at a period of 1 ms after receipt of a block of 10 clock steps (1 START, 8 steps for 4 bits of the remote control, 1 STOP), or a multiple of 1 ms. The microprocessor 2 executes the remote control commands in 50 to 90 ms, taking into account 40 ms of uncertainty which result from the delay in the detection of the start of the remote control information when the input circuit 1 is in the standby mode.

Claims (7)

1. A method for the transmission of digital remote control signals, each of which can assume a logical state among many, from a transmitter ( 39 ) to a receiver ( 1 , 2 ), the input side of a buffer circuit ( 1 ) for reception the remote control signals and for their transmission to a processor ( 2 ) with a predetermined up divided computing power for the reception of the transmitted signals and their processing, characterized in that, in order to limit the task reception, the transmission step frequency from the an input circuit ( 1 ) is limited by dividing the incoming signals into transmission blocks of a certain size, and that in the transmitter ( 39 ), before the signals are sent, their logical state is coded in the form of a pulse which has a specific position in a period (T) before a certain duration takes and the transmission blocks to the input circuit ( 1 ) with a higher Transmission rate as the transmission step frequency are transmitted so that the entire computing power remaining free due to the limited reception task can be used essentially for signal processing. 2. The method according to claim 1, characterized in that that the binary signals, each one of can take two logical states, in form of an impulse at the beginning and at the end of one Bit period (T) can be encoded.   3. The method according to claim 2, characterized in that that the pulse duration to half the bit period (T) is set. 4. The method according to claim 3, characterized in that the pulse in the first or the second half period of the bit (T) by conditional inversion ( 33 ) of a clock signal over a bit period (T), depending on the bit to be transmitted, is positioned . 5. The method according to claim 4, characterized in that errors in the incoming signals by Er know an equal signal level over more than a bit period (T) is sought. 6. The method according to any one of claims 1 to 5, characterized in that the transmitter ( 39 ) data blocks, each containing a byte clock increments, are transmitted asynchronously and that the input-side switching device ( 14 ) an interruption in the processor ( 2 ) Transfer of every received byte causes. 7. The method according to any one of claims 1 to 6, characterized in that taking into account the power-saving alternating in active mode and standby mode input circuit ( 1 ) from the transmitter ( 29 ) in succession a plurality of preamble sequences ( 20 ) Activation of the input-side circuit are sent and this is only periodically activated by the processor ( 2 ) until a remote control signal arrives, so that the latter can receive and know at least one of the sequences ( 20 ) and then switch the input-side circuit ( 1 ) to set active state in which it receives the subsequent remote control signals.