DE19834648A1 - Circuit arrangement for signal delay in PLL - Google Patents

Abstract

When processing digital signals, certain time periods, for example delay times, must be observed as precisely as possible. With the circuit arrangement according to the invention, delay times can be achieved which are not constant but can be adapted to the clock signal which controls the signal processing. Despite the choice of minimum hold times, this enables safe signal processing that is independent of temperature and technology.

Description

The invention relates to a circuit arrangement which relates to Suitable for delaying signals. When processing Si gnalen delay times occur from the finite Transit time of a signal in a transmission medium or through Pass times in a signal processing module Ren. With several processing modules that work together ken, these delay times must be taken into account to synchronize the building blocks with each other to reach. The influence of delay times is all the more critical table, the higher the clock frequency with which a signal processing unit is operated.

Especially when transferring data from a module to an egg The following in the signal flow are certain time conditions to adhere to.

In digital signal processing, the processing data are usually not evaluated continuously, but rather at specific times. A periodic clock signal usually determines the rhythm of the evaluation. Such a clock signal is shown in the upper line of FIG. 1. The data is evaluated, for example, at the time of rising clock edges. These changes from a low signal level to a high signal level are marked in FIG. 1 with an arrow pointing vertically upward. In order for data to be transferred from a block without errors at these times, two conditions must be met. On the one hand, the data that can be taken over by the block must already be available to the block that is to evaluate it for a certain time, the waiting time, before the clock changes. On the other hand, even after these clock changes, the data must still be pending at this block, the hold time. This is the only way to ensure that the block accepts and processes valid data. If these time conditions are not met, data may be available that are not dethermini tical and lead to non-reproducible errors. In the lower line of FIG. 1, the periods in which final data are available are identified by two horizontal parallel lines. The rest of the time, data with random content may be available.

The waiting time (t _W ) and the holding time (t _H ) are characteristic for each digital component and are specified in the manufacturer's data sheets. They are usually in the range of a few nanoseconds.

The shorter the waiting and stopping time, the longer it can be Frequency of the clock signal from which the signal processing unit is controlled, since a new Time change is allowed. The mo keep the mental state of the clock signal (low, high) the. Waiting and stopping time must therefore be long enough for that valid data can be transferred from a block, but also as short as possible, so a high clock rate and thus a high signal processing speed is achieved.

The holding time (t _H ) is the time by which a date that is already on a block before a certain clock change is delayed after this clock change before a new date is made available in the block. It is desirable that the delay time is kept as precise as possible to enable safe and fast signal processing.

The object of the present invention is therefore a scarf to specify signaling arrangement for which the Delay time is observed with high accuracy.  

This object is achieved with the features of claim 1 solved.

The invention is also based on the object, a Ver suit for the circuit arrangement according to the invention ben. This object is achieved with the features of claim ches 7 solved.

The invention has the advantage that the delays achieved time largely independent of temperature and technology is fluctuations.

The invention uses a control loop, for example egg phase locked loop (PLL). Almost in every signal Such a phase locked loop is already a processing unit available. The invention then advantageously allows it se, with only a few additional components a regulated one Get signal delay.

It is also advantageous that the delay in wide Be range can be chosen.

The circuit arrangement according to the invention can with a Seri Circuit with a fixed number of delay elements operate. However, it is advantageous to provide that the number of delay elements through which the Steueri gnal should be delayed, can be set. This can be achieved, for example, that between the individual A tap is provided for each delay element. Then only the delay elements that act before the sem tap are connected in series. The undelayed The control signal is always on at the first delay element placed.

However, it is also conceivable that the delayed Steueri always on the last delay element of the series connection is taken and the undelayed control signal via a  the taps are fed. In this case only show Delay effect between the tap and the Output of the last delay element.

The greatest accuracy in the delay time is obtained if the delay elements of the ring resonant circuit both from the circuit technology as well as the topography the same Chen structure. The delays are advantageous tion elements of both the ring resonant circuit and the series Switching as integrated circuits on a single Semiconductor chip realized.

It is particularly easy if you act as delay elements Inverters, for example CMOS inverters, are used. The delays This occurs due to the passage time of the at the entrance of the inverter pending signal. The inverted output signal from the inverter is present after a short delay.

Further advantageous training and further education are in Un marked claims.

The invention is based on the figures of the drawing tion explained in more detail. Show it:

Fig. 1 is a timing diagram for explaining the terms "waiting time" and "hold time",

Fig. 2 tung arrangement is a block diagram of a formwork according to the invention,

Fig. 3 shows an embodiment of a series circuit of delay elements and

Fig. 4 shows an embodiment of a delay element.

A circuit arrangement according to the invention has a ring resonant circuit 1 , which is located in a control circuit 2 . According to the embodiment of FIG. 2, the ring resonant circuit 1 contains a chain of coupled delay elements 3 , for example from inverters connected in series. The last inverter in the chain is fed back to the first inverter. The frequency f _T , with which the ring resonant circuit oscillates, is dependent on the number of delay elements and their transit time, i.e. the time it takes for a signal at the input of one of the delay elements to arrive (possibly inverted) at the output . The longer the chain of delay elements 3 and the transit time, the lower the frequency f _T.

In the exemplary embodiment according to FIG. 2, the control loop 2 is designed as a phase locked loop (PLL). The basic structure of phase-locked loops is described, for example, in the reference Tietze / Schenk, "semiconductor circuit technology", 10th edition, 1993, chapter 27.4. Phase-locked loops are used to generate an output signal that is coupled to a reference frequency signal with a high phase.

The control circuit 2 includes a phase detector 4 , the input side of a reference signal with the reference frequency f _B and an output signal with the output frequency f _A , which represents the return signal of the control circuit 2 , who the. The phase detector 4 compares the phase of the output signal with that of the reference signal. The determined phase difference is transmitted to a controller 5 connected downstream of the phase detector 4 . This provides a control voltage U _{R on the} output side depending on the level of the phase difference. A converter stage 6 , which is connected on the input side to the output of the controller 5 , provides a control current I _An on the output side. The drive current I _An is a measure of the phase difference between the reference and the output signal determined by the phase detector 4 and is larger the larger this phase difference. From the drive current I _An the ring circuit 1 and a series circuit device are fed from further delay elements 7 . The frequency F _{T of} the ring circuit 1 can be influenced by the control current I _An within certain limits. If the magnitude of the drive current I _{An is} increased, a larger current also flows through the coupled delay elements 3 . The transit time of a signal through the delay elements 3 is thereby reduced and the frequency f _{T of} the ring circuit 1 increases. It is fed back to the phase detector 4 as the output frequency F _A. The output frequency F _A can be used, for example, to generate a clock signal.

If the output frequency f _A does not match the reference frequency f _B , the phase detector 4 detects a phase difference. Via the controller 5 and the converter stage 6, the control current I to _An in the direction and amount so changed that the ring oscillation circuit 1 f its frequency _T conforms to the reference frequency f _B.

The output frequency f _{A is} tracked with high accuracy of the reference frequency f _B largely independent of temperature and technology fluctuations. If the control circuit 2 is steady, the drive current I _An is subject _to only slight fluctuations.

The converter stage 6 leads the series circuit from the further delay elements 7 to the drive current I _An , which corresponds to the amount of the control current I _R. The passage time of the coupled delay elements 3 of the ring circuit 1 and the passage time of the series circuit from the delay elements 7 are in a fixed relationship, since both the ring circuit 1 and the series circuit 7 with a current of the same amount, namely I _R and I _An , be fed. If the output frequency f _{A of} the control circuit 2 is used to generate a clock signal with the clock frequency T _CLK , the delay due to the delay elements of the series circuit 7 is a fixed fraction of the clock period T _CLK . The output signal AS of the series circuit 7 can be used to determine the holding time T _H. A date, which is supplied, for example, to a signal processing module, is kept constant when the clock edge occurs during a clock change until this clock edge also occurs at the output of the series circuit from the delay elements 7 . The date of the signal processing block is therefore no longer changed until after the clock edge at the output of the control circuit RA this also occurs in the output signal of the series circuit 7 . In order to be able to choose various holding times, the delay must be adjustable by means of the series circuit 7 . One possibility for this is shown in FIG. 3. The delay unit 7 contains a series connection of inverters, of which 3 inverters INV1, INV2 and INV3 are shown. Each inverter has an inverting and non-inverting input, as well as an inverting and non-inverting output. The inputs of the first inverter INV1 of the series circuit are fed to the output signal f _A of the series circuit 2 , the non-inverting input directly, the inverting input after a signal inversion. The outputs of the first inverter INV1 are connected to the corresponding inputs of the second inverter INV2. The following inverters are also connected in the same way to the previous inverter. The non-inverting output of the first inverter INV1 is connected via a switch S1, the non-inverting output of the second inverter INV2 via a switch S2 and the non-inverting output of the third inverter INV3 via a switch S3 to an output terminal OUT of the delay unit 7 . Between the other inverters, which are not shown in FIG. 3, further switches can be provided. By closing the first switch S1, the input signal f _T fed to an input terminal IN of the first inverter INV1 is already removed after passing through the first inverter INV1. In this case, the input signal f _{T is} only delayed by this first inverter INV1. The following inverters INV2, INV3 are then ineffective. If switch S1 remains open and switch S2 is closed, only the first two inverters INV1, INV2 are effective with regard to the delay of the input signal f _T. If only switch S3 is closed, all three inverters INV1, INV2 and INV3 contribute to delaying the input signal f _T. Depending on which of the switches S1, S2, S3 is closed, the desired delay can be set in stages. By the propagation time of the inverters INV1, INV2, INV3 via the driving current I _to the running time of the inverter 3 of Ringschwingkrei adjust ses 1 to the supply side injected current in the inverters of the delay unit is per weils adjustable. The greater the current fed in, the faster the invertors INV1, INV2, INV3 are at the outputs of the inverters to the signal applied to the inputs.

According to FIG. 4 contains a possible embodiment of the In verter INV1, INV2, INV3 two field effect transistors T1 and T2. The gate terminal of transistor T1 is the non-verting, the gate terminal of transistor T2 is the inverting input of the inverter. They source terminals of transistors T1 and T2 are each connected to a first supply potential V _SS via a controllable current source SQ1 . The drain of the transistor T1 is connected via a second controllable current source SQ2 to a second supply potential V _DD . It forms the inverting output of the inverter. The drain terminal of the transistor T2 is connected to the second supply potential V _DD via a third controllable current source SQ3. It represents the non-inverting output of the inverter.

The principle according to the invention is also applicable to inverters Only one input and one output can be used at a time.

The output signal f _{A of} the control circuit 2 is a delay unit 7 fed. This may contain only one further delay element or also several further delay elements connected in series. By connecting the further delay elements in series, a longer delay time of the delay unit can be achieved. The drive current I _at the converter stage 6 is supplied to the delay unit 7 in order to adapt the transit time of a signal through one of the further delay elements to the transit time of a signal through one of the coupled delay elements 3 . Fine control of the delay time can be achieved via the control current I _An . By selecting the number of delay elements connected in series to the length of the holding time T _H can be selected.

The frequency f _{A of} the ring resonant circuit 1 is regulated via the control current I _{R of} the converter stage 6 in such a way that it coincides with the reference frequency f _B if possible. The frequency f _{T of} the resonant circuit is determined by the duration of its delay elements 3 . This is influenced by the control current I _R. Arrangements according to FIG. 4 are suitable as circuit-related implementations of the delay elements 3. If the drive current I _{An is} proportional in amount or equal to the control current I _R , the duration of the further delay elements 8 is also equal or proportional to the duration of the delay elements 3 of the ring resonant circuit 1st By coupling the delay unit 7 to the control circuit 2 , the delay time of the delay unit 7 is not set absolutely, but as a function of the actual frequency of the ring circuit 1 . The holding time P _H can therefore be set very precisely with regard to the clock signal.

Claims (9)

1. Circuit arrangement for signal delay with a ring delay circuit ( 1 ) constructed from coupled delay elements ( 3 ), which produces a control signal with a clock frequency (f _A ) and which is arranged in a control circuit ( 2 ), which has a manipulated variable (I _R ) supplies for driving the ring oscillating circuit (1) to the clock frequency (f _a) to a predeterminable nominal frequency (f _B) to control, and with a Verzögerungsein unit (7) comprises a further delay element (INV1) or more series-connected further delay members ( INV1, INV2, INV3), to which the control signal (I _R ) can be fed and removed after a delay time with the same signal profile, the delay time being controlled by a signal (I _An ) derived from the manipulated variable (I _R ). 2. Circuit arrangement according to claim 1, characterized in that the number of delay elements ( 8 ) of the delay unit ( 7 ) is optionally adjustable. 3. Circuit arrangement according to claim 1 or 2, characterized in that between the delay elements ( 8 ) of the delay unit ( 7 ) first means (S1, S2, S3) are provided, with the delayed delayed control signal (f _A ) can be removed. 4. Circuit arrangement according to one of claims 1, 2 or 3, characterized in that between the delay elements ( 8 ) of the delay unit ( 7 ) second means are provided via which the control signal (f _A ) can be supplied. 5. Circuit arrangement according to one of claims 1 to 4, characterized in that the delay element ( 8 ) of the delay unit ( 7 ) have the same structure as the coupled delay elements ( 3 ) of the ring resonant circuit ( 1 ) 6. Circuit arrangement according to one of claims 1 to 5, characterized in that the delay circuit ( 8 ) of the delay unit ( 7 ) contain an inverter (INV1) with a controllable current source. 7. Circuit arrangement according to claim 6, characterized in that the inverter (INV1) is designed as two source-side coupled field effect transistors (T1, T2), each of which has a controllable current source (SQ2, SQ3) with a first supply potential (V _DD ) and the source side are connected via a further controllable current source (SQ1) to a second supply potential (V _SS ) and whose gate connections each have an input (in_p, in_n) and whose drain connections each have an output (out_p, out_n) of the inverter (INV1 ) form. 8. Use of a circuit arrangement for signal delay according to one of the preceding claims for generating hold times (T _H ) for a data signal in circuits with digital blocks. 9. Use of a circuit arrangement according to claim 8, characterized in that with the default time-delayed control signal is used so that a data signal at the beginning of a certain state of the control signal on is valid until the delayed control signal assumes the same particular condition.