DE19821215A1 - Access control of multiple memory semiconductor memory - Google Patents

Abstract

The semiconductor memory is organized as a number of stages (A,B), and which one is active is dependent upon the selection signals ( phi A, phi B) that are provided by a generator circuit via drive circuits (5,6). The circuit receives inputs from an instruction decoder (2) and also memory addresses from an input buffer (1). The generator receives activation acknowledgment signals (ACT A,ACT B) from the drive stages.

Description

The present invention relates to a multi-bank half conductor storage device.

More specifically, it refers to a multi-bank half circuit memory device having a plurality of banks which is independent of each other in an active / inactive Condition can be driven. The invention relates in particular on a structure for bank control in a syn chron semiconductor memory device in synchronization with a clock signal works.

A synchronous semiconductor memory device that a Has data input / output in synchronism with a clock signal known. Determined in the synchronous semiconductor memory device a clock signal the data input / output rate and data can e.g. B. corresponding to a high speed clock signal, which is a system clock, are transmitted. As a result necessary data can be processed by a processor running at high Ge speed works, can be delivered in a short time. The waiting time of the processor can therefore be reduced and the performance of a processing system is improved.  

Such a synchronous semiconductor memory device is a syn Chronic dynamic random access memory (SDRAM). The SDRAM has a dynamic memory cell from the Transistor-on-capacitor type as a memory cell. At the SDRAM are external signals or a control signal and a Address signal as well as write data in the device z. B. on a rising edge of a clock signal, and a read value reaches a defined state on an rising edge of the clock signal. With the SDRAM, a Be failed or an instruction about an operating mode as a com combination of logical states of a plurality of external ones Control signals supplied. The operating mode instruction becomes all commonly referred to as an "order". By giving an instruction regarding an operating mode in the form of a command given an operating mode instruction for each clock cycle the so that a plurality of memory fields are internally independent can be driven or operated from each other. A majority of banks are generally provided internally in the SDRAM. With regard to a 16 Mbit SDRAM, e.g. B. a specification, according to which 2 banks are provided internally, by JEDEC (Joint Electron Device Engineering Council) standardized.

Fig. 25 shows states of external signals at the time of data reading in a conventional SDRAM.

In a clock cycle # 0 there is an external row address Activation signal ZRAS to an L level and are a gap address activation signal ZCAS and a write enable signal ZWE to an H level on a rising edge of an ex extCLK clock signal set. On this condition the Sig nale is considered an activation command that a field ac tivation referred to. "Field activation" is a Operation of driving a row in a memory cell array in a selected state and performing a detection, Amplification and locking of data in a memory cell, which is connected to the selected line by a Le  stronger. When the activation command is issued, a row selection operation for a bank by a Bank address signal BA using an address signal ADD, the is simultaneously applied as a row address signal X, out leads. With the two-bank structure, the bank address signal is BA a 1-bit signal and a bank address signal BA are for designation bank #A is set to H level in clock cycle # 0. De Accordingly, bank #A is brought into an active state ben.

In a clock cycle # 1 are the row address enable signal ZRAS and the write enable signal ZWE to the H level and that Column address activation signal ZCAS set to L level. This state is called a read command that is reading from Data referred to, referred to. If given the read command is a column selection operation for bank #A by the current bank address signal BA is designated, executed, where the address signal ADD, which is simultaneously a column address signal is applied, is used, and a value in a selected memory cell is read.

A clock cycle period that is required from the delivery of the read command to the output of the valid value in the SDRAM is referred to as a CAS latency. A valid value is output when the CAS latency has expired. In Fig. 25, a data read operation with the CAS latency of 2 is is provided. In this case, the value in a memory cell, which is addressed by a column address signal Y in bank #A, reaches a defined state on a rising edge of the clock signal extCLK in a clock cycle # 3 (shown as value a0).

In the SDRAM, a column address signal is internally corresponding a prescribed sequence with an address signal to the Time of delivery of the read command as a leading ad generated and a selection operation for a memory cell  is subsequently according to the internally generated columns address signal (Burstad address signal) executed. Accordingly data a1, a2, and a3 are successively extracted from bank #A read in clock cycles # 4, # 5 and # 6.

In parallel to reading the data from bank #A, an Ak Activation command delivered in clock cycle # 4. At that time point, the bank address signal BA is set to the L level to designate another bank #B. As a result, in Clock cycle # 4 bank #B activates the current address signal ADD is used as a row address signal X and a Row selection operation is carried out.

In clock cycle # 5, bank #B is reset by setting the Bank address signal BA referred to the L level and a read error is output. The read command allows a split selection operation for bank #B is executed, and a value in a memory cell of a selected column is read out.

Since the CAS latency is 2, a value in bank #B is read out in clock cycle # 6 and a memory cell value b0 of bank #B reaches a defined state on a rising edge of the external clock signal extCLK in clock cycle # 7. A burst address signal is also generated internally in bank #B, memory cells are sequentially selected, and a value in a selected memory cell is read. The number of data that are successively read out when a read command is supplied is called a burst length. Fig. 25 shows a data read operation when the burst length is 4.

On the other hand, the row address activation signal ZRAS and the write enable signal ZWE to the L level and the gap ten address activation signal ZCAS to the H level in clock cycle # 6 set to deliver a preload command. The preload a command that is in a bank in an active state is failed  drives an inactive state. The preload command allows that a bank that addresses according to the bank address signal BA is preloaded. That is why the bank address signal BA is on the rising edge of the external clock signal extCLK in the Clock cycle # 6 at H level, bank #A is labeled, and bank #A is deactivated.

In parallel with a read operation for the data b1, b2 and b3 from the bank #B in clock cycle # 8, the bank address signal BA is again set to the H level in order to provide an activation command for the bank #A. Bank #A is reactivated in this way. Next, in clock cycle # 9, a read command for bank #A is provided. Data from bank #A is read after the last value b3 of the burst length data is read from bank #B (shown as (a) in Fig. 25).

If the two banks are provided, as described above the banks are activated / deactivated alternately. Even if moved to different lines (word lines) is used is the RAS precharge time in a standard DRAM unnecessary to achieve high speed data reading.

Fig. 26 is a timing chart showing the states of external signals at the time of data writing. Referring to Fig. 26, data write operation will be described. Fig. 26 shows an operation sequence when two banks are provided and data is alternately written into the banks with a burst length of 4.

In the clock cycle # 0, the bank address signal BA is at the H level set and an activation command is issued. The bank #A is activated in this way and a line selection mode is under Use of a simultaneously applied address signal ADD as Row address signal X executed.  

On a rising edge of the external clock signal extCLK in clock cycle 1 , the row address activation signal ZRAS is set to the H level, the column address activation signal ZCAS and the write enable signal ZWE are set to the L level, and a write command is given. The bank address signal BA supplied at the same time as the write command is set to the H level, and an instruction to write data to the bank #A is given. When the write command is supplied, column selection is performed using the simultaneously applied address signal ADD as a column address signal, and data writing is performed.

When a value is written, a value that is in a Clock cycle has been created in which a write command has been supplied to the SDRAM to execute the write added. In other words, the value c0 in clock cycle # 1 is included in the storage device. Column address signals are internally corresponding to one written sequence with the address signal ADD, which in Taktzyk lus # 1 has been delivered in bank #A as a leader Address generated as if a value is read out. In the tak Cycles # 2, # 3 and # 4 become column selection operations speaking and the data c1, c2 and c3, which are currently delivered, are consecutively selected in Memory cells written in a prescribed sequence.

Parallel to the data writing operation for bank #A, in Clock cycle # 5 set the bank address signal BA to the L level and an activation command is provided. In this case an instruction to activate bank #B, and one Row of memory cells is created using the address signal ADD currently being supplied as row address signal X in selected by bank #B. In the next clock cycle # 5 that is Bank address signal BA is again set to the L level and on Write command is given. Accordingly, the value b0, which is delivered in clock cycle # 5, included in the SDRAM,  and data write operation for bank #B is performed. Burst address signals are then internally one before written sequence generated in bank #B and a columns selection mode is carried out internally. The data d1, d2 and d3, which are delivered accordingly in clock cycles # 6, # 7 and # 8 will be included in the storage device and values are selected according to one in selected memory cells written sequence written.

Parallel to the data writing operation for bank #B, in Clock cycle # 6 set the bank address signal BA to the H level and a preload command is provided. Bank #A becomes like this deactivated and the memory cell array returns to a preload state back.

In clock cycle # 8, the bank address signal BA is again on the H level set to provide an activation command. The bench #A in the deactivated state is reactivated and one Memory cell row is selected. Next in Tak tcycle # 9 set the bank address signal BA to the H level and a write command for bank #A is issued. From the Taktzyk From # 9 onwards, data writing for bank #A is carried out. Then data c4, c5,. . . in the selected memory cells in bank #A according to a prescribed Ab follow written.

When data is written as above, banks #A and #B alternately activated / deactivated and data are written. As a result, the RAS precharge time is affected (a time to return the memory cell array in the precharge state to enable the driver to be driven again same in the active state is needed) to return bring a selected or activated memory cells field in the precharge state at the time of the page (page) - Switching is necessary, does not affect external access rivers. Data can be consecutive in every clock cycle  be written and high speed data writing is achieved.

Fig. 27 shows a structure of a main portion of the conventional SDRAM. Referring to Fig. 27, the conventional SDRAM comprises: a bank address input buffer 1 which receives an externally supplied bank address signal BA on a rising edge of an internal clock signal CLK, which is generated in synchronization with the external clock signal extCLK, and internal bank address signals BAi and / BAi that are complementary to each other; a command decoder 2 which receives externally supplied control signals ZRAS, ZCAS and ZWE on a rising edge of the internal clock signal CLK, determines the states of these signals, and generates an operating mode instruction signal Φ in accordance with the result of the determination; and a bank control circuit 3 which outputs an operation mode designation signal for the bank #A and the bank #B in accordance with the operation mode instruction signal Φ supplied from the instruction decoder 2 as well as the internal bank address signals BAi and / BAi supplied from the bank address input buffer 1 . issues. A signal Φ represents the signals in FIG. 27 as to whether the operation mode instruction signals are generated by the instruction decoder 2 in accordance with the corresponding instructions shown in FIGS. 25 and 26.

The bank control circuit 3 comprises an AND circuit 3 a, which receives the internal bank address BAi and Betriebsmodusanweisungssig nal Φ, and an AND circuit 3 b, which receives the internal bank address / BAi and the operation mode instruction signal Φ on. An operating mode instruction signal ΦA is output from the AND circuit 3 a for the bank #A, and an operating mode instruction signal ΦB is output for the bank #B from the AND circuit 3 b.

One of the internal bank address signals BAi and / BAi generated by the bank address input buffer 1 is at the H level and the other signal is at the L level. As a result, an operation mode designation signal corresponding to an operation mode instruction signal is output from the command decoder 2 for only one bank designated by the bank address signal BA, the operation mode instruction signal for the addressed bank reaches an active state (H level), and the designated operation is running.

As shown in Fig. 27, if a command is supplied to the SDRAM, a bank address signal BA indicating a bank for which an operation is being performed should be supplied. The reason is that a mode of operation for a bank in the active state should be designated without errors because there is a case where two banks are activated at the same time.

However, there is a case where high speed is too resorted to in such a bank nesting manner (bank Interleave) is not required, but access is always un only one bank is activated. In the field of Image processing is e.g. B. if a storage device is so is structured that pixel data on even fields in one of two banks are saved and pixel data of odd Fields stored in the other bank: are, only on one Bank accessed during a field period, so that a Bank is accessed sequentially. In this case, if a bank that ak to a bank address signal tivieren is designated when an activation command is given an operating mode instruction for the activated bank issued, and a bank does not have to use it specifically a bank address signal if the read command, the write command and the preload command are provided. However, in the conventional SDRAM, once a Bank is activated, an operating mode instruction for the bank then issued simultaneously with a bank address signal  the. In this case, the bank address signal becomes unnecessary driven, the electrical power to drive the bank address signals are consumed unnecessarily, and the ver required performance of the overall system cannot be reduced the. Furthermore, even if the banks are not at the same time A bank address signal must be activated with a command to be delivered. Even if a bank in some is running, obviously, should be an external one Control provide a bank address signal, resulting in an increase in External control is stressed.

An object of the invention is to create a multi-bench half Specify conductor storage device to facilitate the Bank control is capable.

This problem is solved by a semiconductor memory device tion according to claim 1 or 8.

Developments of the invention are set out in the dependent claims give.

A synchronous semiconductor memory device is specified, by designating the load of an external controller a bank is reduced.

Furthermore, a multi-bank semiconductor memory device specified for which an operating mode for a bank in an ak tive state is easily referred to if only one bank is out a plurality of banks are in the active state.

A semiconductor memory device corresponding to a first one Aspect includes: a plurality of bank driver circuits, which are provided in accordance with a plurality of banks for Corresponding banks according to a supplied Operating mode designation signal; and a driver signaler generating circuit with the majority of the bank driver scarf  is coupled to determine whether each of the plurality of Banks are in an active state or not, and if that The result of the determination indicates that only one of the majority of the Banks are in the active state to output the operation mode designation signal corresponding to an operating mode instruction signal for a bank in the active state.

A semiconductor memory device corresponding to a second one Aspect features: A plurality of banks that are independent from each other to an active state and a deactivated one Condition can be driven; a bank selection circuit that a bank address signal synchronized with a clock signal is delivered, received, to generate a bank label signals for a bank by the receiving bank address nal is designated; a bank activation circuit that a Bank activation instruction signal that is in synchronism with a Clock signal is supplied, receives, for outputting a field tivierungssignals to a bank by the bank designation is designated by the bank selection circuit; a Circuit which is an operating mode instruction signal which is under is different from the bank activation instruction signal that is delivered simultaneously with a clock signal, receives to Generate an internal instruction signal corresponding to the received Operating mode instruction signal; and a plurality of Control circuits that correspond to the plurality of banks are provided, each of the bank name signal from the Bank selection circuit as well as the field activation signals for a corresponding bank and other banks from Bankak Activation circuit received to deliver an operating mod Activation signal according to the internal instruction sig nals to the relevant bank while giving the bank name neglect the signal from the bank selection circuit if the field activation signals for other banks in the deak are activated state and the field activation signal for the corresponding bank is in the active state.  

Whether the majority of the banks are each in the active state or are in the deactivated state, is always monitored, and when an operation mode instruction signal is supplied, a Operating mode designation signal for executing the operating mode delivered to a bank that that of the majority of banks that is in the active state. Accordingly, even if a bank address signal does not start with the operation mode instruction signal is supplied, a designated operating mode for the bank to be executed in the active state. There are no need to provide a bank address signal with the Operating mode instruction signal, an external controller will not to monitor a bank in which the operating mode is executed, a bank address signal is not required given simultaneously with an operation mode instruction signal and the burden of designating a bank becomes reduced. As a result, he will have easy bank control is enough and a multi-bank semiconductor memory device can be implemented, which is excellent in usability.

The foregoing and other features and advantages result from the following detailed description of Exec tion forms based on the figures. From the figures show:

Fig. 1 schematically shows an overall structure of a semiconductor memory device according to the first embodiment of the present invention;

Fig. 2 schematically shows a structure of a bank address signal input buffer shown in Fig. 1;

Fig. 3 schematically shows a structure of a command decoder shown in Fig. 1;

Fig. 4 is a timing chart illustrating an operation of the instruction decoder shown in Fig. 3;

Fig. 5 schematically shows a structure of a modification of the instruction decoder shown in Fig. 1;

Fig. 6 is a timing chart showing the instruction of an instruction decoder shown in Fig. 5;

FIG. 7 shows an example of a structure of a field activation instruction signal generation unit in a bank driver signal generation circuit shown in FIG. 1;

Fig. 8 is a timing chart showing an operation of the circuit shown in Fig. 7;

Fig. 9 schematically shows the structure of a portion related to row selection in the semiconductor memory device shown in Fig. 1;

Fig. 10 is a timing chart showing an operation of a bank driver circuit shown in Fig. 9;

FIG. 11 schematically shows a structure of a portion that generates an operation mode designation signal corresponding to a command other than the activation command in the bank driver signal generating circuit shown in FIG. 1;

Fig. 12 shows an example of a structure of the bank driver signal generating circuit shown in Fig. 11;

13 and 14 are timing charts showing operations of the bank driver generating circuit shown in Fig. 12;

Fig. 15 and 16 structures a first and a second modification of the database driver signal generating sschaltung shown in Fig. 11;

Fig. 17 specifically shows a structure of the bank driver signal generating circuit shown in Fig. 11;

Fig. 18 and 19 are timing charts, the operations of the database driver signal generating circuit show that shown in Fig. 17;

FIG. 20 schematically shows a structure of a portion related to data write / read in the semiconductor memory device shown in FIG. 1;

FIG. 21 schematically shows a whole structure of a semiconductor memory device according to the second embodiment of the invention;

Fig. 22 schematically shows a structure of a bank driver signal generating circuit shown in Fig. 21;

Fig. 23 shows an example of a structure of a bank driver signal generating circuit shown in Fig. 22;

Fig. 24 is a timing chart showing an operation of the bank driver signal generating circuit shown in Fig. 17;

Fig. 25 is a timing chart showing an operation at the time of data reading in a conventional synchronous semiconductor memory device;

Fig. 26 is a timing chart showing an operation at the time of data writing in the conventional synchronous semiconductor memory device; and

Fig. 27 schematically shows a structure of an internal Be triebsmodusbezeichnungssignalerzeugungsab section in the conventional synchronous semiconductor memory device.

(First embodiment)

Fig. 1 schematically shows an overall structure of a semiconductor memory device according to the first embodiment of the invention. Referring to Fig. 1, the semiconductor memory device has two banks #A and #B. Each of banks #A and #B has a plurality of memory cells arranged in rows and columns, a circuit for driving the rows and columns into a selected state, and a read / write circuit for writing / reading data . The structures of banks #A and #B will be described later in detail. Bank driver circuits 5 and 6 are respectively provided for banks #A and #B for controlling the operations of banks #A and #B in accordance with operation mode designation signals ΦA and ΦB provided by bank driver signal generation circuit 30 .

The bank driver circuits 5 and 6 , respectively, output field activation signals ACT # A and ACT # B, which drive and hold the corresponding banks #A and #B in an active state. Similarly, when the field activation signals ACT # A and ACT # B are in the active state, banks #A and #B are in the active state for enabling data write / read during the period in this state. The activation / deactivation of the field activation signals ACT # and ACT # B is controlled by the operating mode designation signal from the bank driver signal generation circuit 30 .

The bank driver signal generation circuit 30 outputs various operation mode designation signals corresponding to an operation mode instruction signal supplied from an instruction decoder 2 . In Fig. 1, the operating mode designation signal ΦA for bank #A and the operating mode designation signal ΦB for bank #B are shown representatively.

The bank driver signal generation circuit 30 receives the field activation signals ACT # A and ACT # B from the bank driver circuits 5 and 6 and generates an operation mode designation signal for a bank which is addressed in accordance with the bank address signals BAi and / BAi provided from the bank address signal input buffer 1 , if so field activation signals ACT # A and ACT # B are both in the active state. If only one of the field activation signals ACT # A and ACT # B is in the active state, the bank driver signal generation circuit 30 , when the operation mode instruction signal Φ is supplied from the command decoder 2 , outputs an operation mode designation signal corresponding to the operation mode instruction signal supplied to the bank in the active state . In this case, the bank address signals BAi and / BAi in the internal bank address signals are neglected by the bank address signal input buffer 1 .

If both field activation signals ACT # A and ACT # B are in the deactivated state, banks #A and #B are both in the deactivated state (inactive state). In this case, the bank driver signal generation circuit 30 outputs an operation mode instruction signal for activating a corresponding bank only when an operation mode instruction signal is supplied from the command decoder 2 , that is, when an activation command is supplied.

As described above, if only one bank in the is active state, there is no need for that Delivery of a bank address signal. It is not necessary that the bank address signal is provided when a value is in / out the bank is written / read and when the preload operation running for the bank. As a result, the Belas external control for bank control reduced.

The semiconductor memory device further comprises: an address signal input buffer 4 which receives an externally supplied address signal AD, generates an internal row address signal X and an internal column address signal Y and supplies them to the banks #A and #B; is an input / output circuit 7, the ge to the banks #A and #B via a common internal data bus 8 is coupled, which data (adress ierten) between a selected bank and an external device under the control of the bank drive signal generating circuit 30 inputs / off ; and a clock generating circuit 9 which generates the internal clock signal CLK in synchronism with the external clock signal extCLK. The internal clock signal CLK from the clock generating circuit 9 is supplied to each circuit, and an internal operation is carried out in synchronism with the internal clock signal CLK. The description of the structure of each unit is given next.

(Structure of bank address signal buffer)

Fig. 2 shows an example of a structure of the bank address signal input buffer 1 shown in Fig. 1. Referring to Fig. 2, the bank address signal input buffer 1 has: A transfer gate 1 a, which is formed by an n-channel MCS transistor and is made conductive when an inverted signal / CLK of the internal clock signal CLK on the H- Is level, and transmits the externally supplied clock address signal BA; two cascaded inverters 1 b and 1 c, which receive a bank address signal from the transmission gate 1 a and generate the internal bank address signal BAi; and an inverter 1 d that inverts a signal output from the inverter 1 b and supplies the inverted signal to the input portion of the inverter 1 b. A complementary internal bank address signal / BAi is generated by the inverter 1 b.

In the structure of Bankadreßsignaleingangspuffers 1 shown in Fig. 1, are obtained when the internal clock signal CLK to the H level is obtained, the inverted internal clock signal / CLK to the L level and the transfer gate 1 a comes into a nonconductive state. Accordingly, the externally supplied bank address signal BA is for locking by the inverters 1 b and added d 1, and the internal bank address signals BAi and / BAi achieve a defined state. The externally supplied bank address signal BA is recorded synchronously with a clock signal and the internal bank address signals BAi and / BAi can be generated in each clock cycle.

The address signal buffer 4 shown in FIG. 1 also has a structure similar to that of the bank address signal input buffer 1 shown in FIG. 2.

(Structure of the command decoder)

FIG. 3 schematically shows a structure of the command encoder 2 as shown in FIG. 1. Referring to Fig. 3, the instruction decoder 2 includes gate circuits 2 aa, 2 pa, 2 ra and 2 wa, each of which receives a set of the internal clock signal CLK, the Zeilenadreßaktivierungssignal address strobe signal ZRAS, the Spaltenadreßaktivie approximate signal ZCAS and the write enable signal ZWE on.

The gate circuit 2 aa outputs a signal at the H level when the row address activation signal ZRAS is at the L level and the internal clock signal CLK, the column address activation signal ZCAS and the write enable signal ZWE are at the H level.

The gate circuit 2 a outputs a signal at the H level when the row address activation signal ZRAS and the write enable signal ZWE are both at the L level and the internal clock signal CLK and the column address activation signal ZCAS are both at the H level.

The gate circuit 2 ra outputs a signal at the H level when the internal clock signal CLK, the row address activation signal ZRAS and the write enable signal ZWE are at the H level and the column address activation signal ZCAS is at the L level.

The gate circuit 2 wa outputs a signal at the H level when the internal clock signal CLK and the row address activation signal ZRAS are both at the H level and the column address activation signal ZCAS and the write enable signal ZWE are both at the L level.

In other words, the gate circuit 2 aa outputs a signal at the H level when an activation command is supplied, the gate circuit 2 pa outputs a signal at the H level when a precharge command is supplied, the gate circuit 2 ra inputs Signal at the H level when a read command is supplied, and the gate circuit 2 wa outputs a signal at the H level when a write command is supplied.

Pulse generating circuits 2 ab, 2 pb, 2 rb and 2 wb, each of which output a single-pulse signal with a prescribed time width in response to the rise of an output signal from a corresponding gate circuit, are accordingly the corresponding gate circuits 2 aa, 2 pa, 2 ra and 2 wa provided. A field activation instruction signal Φa is output from the pulse generation circuit 2 ab, a precharge instruction signal Φp is output from the pulse generation circuit 2 pb, a read operation instruction signal Φr is output from the pulse generation circuit 2 rb, and a write operation instruction signal Φw is output from the pulse generation circuit 2 wb.

Instructional operation is performed according to these signals Φa, Φp, Φr and Φw activated as operating mode instruction signals.

FIG. 4 is a timing chart illustrating an operation of the instruction decoder shown in FIG. 3. The description of an operation of the instruction decoder shown in FIG. 3 is given below with reference to FIG. 4.

When the activation command is supplied in clock cycle # 1, a signal output from the gate circuit 2 aa shown in Fig. 3 reaches the H level and the field deactivation instruction signal Φa from the pulse generating circuit 2 is off for a prescribed period at the H level. The other signals Φp, Φr and Φw remain in the deactivated state at the L level.

When the read command is supplied in clock cycle # 2, a signal output from the gate circuit 2 ra shown in Fig. 3 reaches the H level and the read operation instruction signal Φr from the pulse generating circuit 2 rb is for a prescribed one Period at the H level. The other signals Φa, Φw and Φp remain in the deactivated state at the L level.

When the write command is supplied in clock cycle # 3, it passes a signal output from the gate circuit 2 wa, the H level, and the write operation instruction signal Φw from the pulse generation circuit 2 wb is in the active state on the H- for a prescribed period. Level. The remaining signals Φa, Φr and Φp remain in the deactivated state at the L level.

When the precharge command is supplied in clock cycle # 4, a signal output from the gate circuit 2 pa goes to the H level and the precharge instruction signal Φp from the pulse generation circuit 2 pb is at the H level for a prescribed period. The signals Φa, Φr and Φw remain in the deactivated state at the L level.

By outputting an internal operation mode instruction signal corresponding to a combination of the logic states of the control signals on the rising edge of the internal clock signal CLK using the command decoder shown in FIG. 3, an internal operation mode on the rising edge of the internal clock signal CLK is designated. In this way, there is no need to take into account the scope for an asymmetry or a time offset of the external control signals ZRAS, ZCAS and ZWE, so that the internal operation can be started with a faster time. Furthermore, by outputting an operation mode instruction signal in the form of a one-time pulse signal using the pulse generation circuits 2 ab, 2 pb, 2 rb, and 2 wb, an operation mode instruction signal having a prescribed time latitude can be generated without errors.

(Modification of the command decoder)

FIG. 5 shows a structure of a modification of the instruction decoder shown in FIG. 1. A structure of only the part that generates the precharge operation instruction signal is shown in FIG. 5. The structures of the portions that generate the field activation instruction signal Φa, the read operation instruction signal Φr, and the write operation instruction signal Φw are similar to those of the instruction decoder shown in FIG. 3.

Referring to Fig. 5, the instruction decoder comprises: a gate circuit 2 pc which receives the internal clock signal CLK, the row address activation signal ZRAS, the column address activation signal ZCAS and a specific address signal bit A10; a burst length counter 2 pd which is activated in response to the activation of a signal output from the gate circuit 2 pc for counting a period of the burst length; a gate circuit 2 pa which receives the internal clock signal CLK, the row address activation signal ZRAS, the column address activation signal ZCAS and the write enable signal ZWE; an OR circuit 2 pe, which receives a Ausgangssig nal Φpp from the gate circuit 2 and a count-up signal pa Φap from the burst length counter 2 pd; and a pulser generating circuit 2 pb which is activated upon activation of a signal output from the OR circuit 2 pe for outputting the precharge instruction signal Φp which has a prescribed time width.

The structures of the gate circuit 2 pa and the pulse generation circuit 2 pb are similar or identical to those shown in FIG. 3. The gate circuit 2 pc outputs a signal in, the active state at the H level when the internal clock signal CLK and the row address activation signal ZRAS are at the H level, the column address activation signal ZCAS is at the L level, and the address signal bit A10 at the Is H level. The gate circuit 2 pc thus outputs a signal at the H level when the read command or the write command is supplied and the address signal bit A10 is set at the H level (when an automatic precharge command is supplied). The burst length counter 2 pd shifts (delays) a signal output from the gate circuit 2 pc by a period of the burst length and outputs the precharge instruction signal Φap when the burst length period has expired. The OR circuit 2 pe outputs a signal in the active state at H level when one of the signals, the signal Φpp from the gate circuit 2 pa or the signal Φap from the burst length counter 2pd, reaches the active state .

The precharge trigger signal Φp assumes the active state when the precharge command or the command for automatic precharge is delivered. An operation of the instruction decoder shown in FIG. 5 will be described with reference to FIG. 6, which shows the timing chart.

When the precharge command is supplied in clock cycle #a, the output signal Φpp from the gate circuit 2 pa goes to the H level, and a signal output from the OR circuit 2 pe goes to the H level accordingly. The pulse generation circuit 2 pb outputs in response to the activation of the output signal from the OR circuit 2 pe the Vorladean instruction signal Φp with a prescribed time width.

In clock cycle #b the row address activation signal ZRAS and the address signal bit A10 are set to the H level and the column address activation signal ZCAS is set to the L level. The write enable signal ZWE is set to the H or L level in accordance with the read or the write command. The combination of these signals is the automatic precharge, so that a signal that is output by the gate circuit 2 pc assumes the H level and the burst length counter 2 pd is activated. Assuming that the burst length is 4, the count-up signal Φap from the burst length counter 2 pd reaches the H level in clock cycle #c after four clock cycles have elapsed, and the precharge instruction signal Φp from the pulse generation circuit 2 pb is output, is at the H level for a prescribed period.

Using the automatic preload command the precharge command simultaneously with the creation of the read command or the write command, and the other command can be created in clock cycle #c. Furthermore there is for the external control no need the preload command to create again after the read or write operation is done, which in a simplification of the command application quenz results.

(Structure of Bank Driver Signal Generation Circuit 1)

Fig. 7 schematically shows a structure of a portion relating a field activation instruction signal tivierung to the Pc of the field generated in the nalerzeugungsschaltung Banktreibersig 30th Referring to Fig. 7, the bank driver signal generating circuit 30 includes: a one-time pulse generating circuit 30 aa which generates a bank designation signal Φba from a one-time pulse signal when the bank address signal BAi is at H level; a one-time pulse generation circuit 30 which outputs a bank designation signal Φbb from a one-time pulse signal when the bank address signal / BAi is at the H level; a NAND circuit 30 ac that receives the bank designation signal Φba from the one-time pulse generation circuit 30 aa and the field activation instruction signal Φa from the command decoder and outputs a field activation trigger signal Φaa for the bank #A; and a NAND circuit 30 ad that receives the bank designation signal Φbb from the one-time pulse generation circuit 30 and receives the field activation instruction signal Φa and outputs a field deactivation trigger signal Φab for the bank #B. An operation of the field activation trigger signal generating section shown in FIG. 7 will now be described with reference to the timing chart of FIG. 8.

Referring to Figure 8, an activation command for bank #A is provided in clock cycle #a. Bank #A is designated when the bank address signal BAi is at the H level. The bank designation signal Φba from the one-time pulse generation circuit 30 aa is at the H level for a prescribed period. The bank designation signal Φbb from the single-pulse generation circuit 30 remains at the L level. Since the activation command is provided, the field activation instruction signal Φaa is driven by the NAND circuit 30 ac into the active state at the L level in accordance with the field activation instruction signal Φa provided by the instruction decoder. The active state of the field activation trigger signal is set to the L level in order to follow the structure of the circuit section for the field activation in the bank driver circuit.

An activation command for bank #B is provided in clock cycle #b. Bank #B is designated when the bank address signal BAi is at the L level. The bank designation signal Φbb is driven by the one-time pulse generation circuit 30 down to the H level corresponding to the complementary bank address signal / BAi at the H level. The command decoder drives the field activation instruction signal Φa to H level for a prescribed period in accordance with the activation command. As a result, the field activation trigger signal Φab is output from the NAND circuit 30 ad in the active state at the L level for a prescribed period.

The activation command is always issued simultaneously with the bank address signal supplied. As will be described in detail later, whether the bank address signal is valid / invalid becomes corresponding the number of banks that are in the active state, esp as for an operating mode instruction signal sent to the Bank is delivered in the active state.

(Structure of the row-related circuit part of the bank)

Fig. 9 schematically shows a structure of a section related to the row selection of the bank driver circuits 5 and 6 for the banks #A and #B. Since banks #A and #B have a similar or identical structure, a structure of bank #A is shown in FIG. 9. Referring to FIG. 9, bank #A has a memory cell array 50 that has a plurality of memory cells MC arranged in rows and columns. The memory cell array 50 has a word line WL corresponding to each row of memory cells MC, to which memory cells of a corresponding row are connected, and a plurality of bit line pairs BLP, which are arranged corresponding to corresponding columns of memory cells and to which the memory cells are connected in corresponding columns are on. FIG. 9 representatively shows a bit line pair BLP, a word line WL and a memory cell MC which is arranged corresponding to the crossing point of the bit line pair BLP and the word line WL. The memory cell MC has the structure of a dynamic memory cell of the one-transistor-one-capacitor type.

Bank #A further includes: a row address latch 52 which latches row address signal X provided by the address signal input buffer shown in Figure 1 when activated; a row selection circuit 54 which drives a word line corresponding to an addressed row in the memory cell array 50 to the selected state in accordance with the internal row address signal which is latched by the row address latch 52 when activated; a sense amplifier circuit 58 which detects, amplifies and latches data from the memory cells connected to the selected word line when activated; and a bit line equalization circuit 56 that precharges the potential of each bit line of the bit line pair BLP and equalizes it to a prescribed potential when it is activated. Row select circuit 54 includes a decode circuit that decodes the internal row address signal latched by row address latch 52 , and a word line driver circuit that drives a corresponding word line in the selected state in accordance with a signal output from the decode circuit . The sense amplifier circuit 58 has a plurality of sense amplifiers, which are provided corresponding to the corresponding bit line pairs, which differentially amplify the potential on the corresponding bit line pairs. The bit line equalization circuit 56 has a bit line precharge / equalization circuit, which is provided corresponding to each bit line pair, for precharging and equalizing each bit line of the corresponding bit line pair to a prescribed potential.

The bank driver circuit 5 , which is provided for the bank #A, has a set / reset flip-flop 5 a, which is provided in response to the activation of the field activation trigger signal Φaa, which is provided by the bank driver signal generating circuit shown in FIG. 1 , set and reset in response to the precharge trigger signal Φpa, for outputting the field activation signal ACT # A and also a line-related control circuit 5 b, which is a control signal for controlling the operation of a line-related circuit of bank #A in accordance with the activation of the field activation signal ACT #A outputs from the set / reset flip-flop 5 a. The row-related control circuit 5 b controls the activation / deactivation of the row address latch 52 , the row selection circuit 54 , the bit line compensation circuit 56 and the sense amplifier circuit 58 . The structure of the row-related control circuit 5 b is equivalent to the structure for locking the row address signal, decoding of the row, driving the word line in the selected state and activating the Le sever stärkers in a prescribed sequence according to the activation of the internal Zeilenadreßaktivierungssignals RAS in a standard DRAM . Bit line equalization circuit 56 is maintained in the deactivated state when field activation signal ACT # A is activated.

The set / reset flip-flop 5 a has a NAND circuit NA1, which receives the field activation trigger signal Φaa at one input and outputs the field activation signal ACT # A, and a NAND circuit NA2, which has the precharge trigger signal Φpa, via a Inverter IV is supplied, and the field activation signal ACT # A receives and supplies the output signal to the other input of the NAND circuit NA1.

The bank driver circuit 6 for bank #B has a set / reset flip-flop 6 a, which receives the field activation trigger signal alab at a set input S and the precharge trigger signal Φpb at a reset input R and outputs the field activation signal ACT # B from an output Q. , and a line-related control circuit 6 b, which activates the line-related circuit of bank #B in a prescribed sequence in response to the activation of the field activation signal ACT # B by the set / reset flip-flop 6 a. Referring to the timing diagram of Fig. 10, an operation of the bank is driving circuit shown in Fig. 9, described below. One difference between the bank driver circuit 5 and the bank driver circuit 6 is that they receive different trigger signals. In Fig. 10, an operation of the bank driver circuit 5 for the bank #A is shown. In clock cycle #a, an activation command for bank #A is provided and the field activation trigger signal Φaa from bank driver signal generating circuit 30 shown in FIG. 7 maintains the active state at the L level for a prescribed period of time. When the field activation trigger signal Φaa receives the L level, the field activation signal ACT # A from the NAND circuit NA1 reaches the active state at the H level in the set / reset flip-flop 5 a, which is contained in the bank driver circuit 5 . Accordingly, the line-related control circuit 5 b is activated, the supplied row address signal X is locked by the row address lock 52 , the row selection circuit 54 is activated and the sense amplifier circuit 58 is activated. The bit line equalization circuit 56 is driven into the deactivated state in accordance with the activation of the field activation signal ACT # A.

Although the field activation trigger signal Φaa returns from the H level to the L level, the precharge trigger signal Φpa is still in the deactivated state to the L level and a signal output from the NAND circuit NA2 is on the H- Level. Therefore, the field activation signal ACT # A is locked by the set / reset flip-flop 5 a and kept at the H level.

In clock cycle #b, a precharge command for bank #A is provided, or alternatively, an automatic precharge command is provided in the previous cycle, and precharge trigger signal Φpa from bank driver signal generation circuit 30 is driven high for a prescribed period of time, such as will be described later. A signal that is output from the inverter TV thus receives the L level, a signal that is output from the NAND circuit NA1, it reaches the H level, and the field activation signal ACT # A from the NAND circuit NA1 is accordingly driven to the L level in the deactivated state. In response to the deactivation of the field activation signal ACT # A, the row-related control circuit 5 b drives the row selection circuit 54 and the sense amplifier circuit 58 into the deactivated state and drives the bit line equalization circuit 56 into the active state. The row address latch 52 is reset. As a result, bank #A is deactivated.

When bank #B is activated, the field activation sig nal ACT # B according to the activation of the field activation Striggersignals Φab activated. The completion of the field Activation in bank #B is done by activating the preload trigger signals Φpb reached.

The state in which a word line is driven into the selected state and data in a memory cell connected to the selected row is detected, amplified and locked by the sense amplifier circuit 58 is referred to as "bank activation".

As shown in Fig. 9, if the field activation trigger is provided, the bank remains in its active state until the precharge instruction signal is next delivered to it. The field activation trigger signal Φa and the Vorladean instruction signal Φp are generated in the form of the one-time pulse signal. Therefore banks #A and #B can be activated / deactivated independently of each other in each clock cycle.

(Structure of the bank driver signal generation circuit for the line-related circuit)

Fig. 11 schematically shows a structure of a portion, which is other than the portion that generates the activation field striggersignal, the bank drive signal generating TIC 30, which is shown in FIG. 1. Referring to FIG. 11, the bank driver signal generation circuit 30 includes: a determination circuit 30 b that receives the field activation signals ACT # A and ACT # B from the bank driver circuits 5 and 6 shown in FIG. 9 determines whether the banks #A and #B are both in the active state or not, and outputs a signal indicating the result of the determination; a bank decision circuit 30 c which receives a signal indicating the result of the determination by the determination circuit 30 b as well as the bank designation signals Φba and Φbb and decides a bank to be selected according to the determination; and operation mode designating signal generation circuits 30 output d and 30 e, the operation mode designation signals ØA and ØB for the banks #A and #B corresponding to the operation mode instruction signal Φ from the instruction decoder and the bank designation signal from the bank decision circuit 30 c. Although the operation mode designation signals ΦA and ΦB are shown representatively, the designation signals include a read operation designation signal, a write operation designation signal, and a precharge operation designation signal, as will be described later.

The bank decision circuit 30 selects c one of the operation mode designating signal generating circuits 30 d and 30 e accordingly the bank designating signals Φba and Φbb of, if the determination circuit 30 b indicates that both banks #A and #B are in the active state. If the determination circuit 30 b signals that only one bank is in the active state, the bank decision circuit 30 c selects an operation mode designation signal generating circuit which is provided for the bank in the active state. Furthermore, the bank decision circuit 30 c sets both operating mode designation signal generation circuits 30 d and 30 e to the unselected state if the determination circuit 30 signals that both banks #A and #B are in the deactivated state. The reason is that any significant operation for banks #A and #B is not carried out even if an operation mode designation signal is supplied to the bank in the deactivated state.

(Specific Structure of Bank Driver Signal Generation Circuit)

FIG. 12 shows a specific structure of the bank driver signal generating circuit 30 shown in FIG. 11. Referring to FIG. 12, the determination circuit 30 b has a NAND circuit 30 ba that receives the field activation signals ACT # A and ACT # B, and an inverter 30 bb that has a signal output from the NAND circuit 30 ba will receive on. Selection signals ZBAS and BAS, which indicates whether the banks #A and #B are both in the active state or not, is output from the determination circuit 30 b, the Feldaktivierungssig dimensional ACT # A and ACT # B, one in the active state See for trei Bende bank are also processing from the determination scarf 30 b outputted, and these signals from the determination circuit 30 b of the decision circuit 30 are supplied bank c.

The bank decision circuit 30 c has: a CMOS transmission gate Taa which becomes conductive when the Auswahlsig dimensional ZBAS and BAS b from the determination circuit 30 are in the Deak TiVi Erten state and at least one bank is shown as being in the deactivated state to the Feldak tivierungssignal ACT # A by the determination circuit 30 b by adding; a CMOS transfer gate Tab which becomes conductive when the selection signals ZBA5 and BA5 are in the active state, indicating that both banks are in the active state to pass the bank designation signal Φba designating the bank #A; a CMOS transmission gate TBA which becomes conductive in response to the deactivated state of the selection signals ZBA5 and BAS to array activation signal ACT # B of the Bes timmungsschaltung by adding 30 b; and a CMOS transfer gate Tbb which becomes conductive when the selection signals ZBAS and BAS are in the active state to pass the bank designation signal Φbb denoting bank #B.

The selection signals ZBAS and BAS are at the L level and the H level set in the active state when the field activation tion signals ACT # A and ACT # B both at the H level in the ak tive condition.

The operation mode designation signal generation circuit 30 d has an AND circuit 30 which outputs the operation mode designation signal ΦA for the bank #A in accordance with the operation mode instruction signal Φ from the command decoder and a signal output from one of the CMOS transmission gates Taa and Tab. The operation mode designation signal generating circuit 30 e outputs the operation mode designation signal ΦB for the bank #B in accordance with the operation mode instruction signal Φ from the command decoder and a signal supplied from one of the transmission gates Tba and Tbb. Operation of the bank driver signal generating circuit shown in FIG. 12 will now be described with reference to the timing diagrams shown in FIGS . 13 and 14.

Referring first to FIG. 13, an operation of the bank driver signal generating circuit 30 when only one bank is in the active state will be described.

In clock cycle # 0, banks #A and #B are both in the deak activated state and the field activation signals ACT # A and ACT # B are both at L level.

In clock cycle # 1, an activation command for bank #A is provided. Since the bank #A is designated when the bank address signal BA is at the H level, the bank designation signal Φba which designates the bank #A reaches the H level and the field activation instruction signal Φa from the command decoder receives the active state on the H level for a prescribed period. As has been described with reference to FIGS . 9 and 10, the field activation trigger signal Φaa for bank #A reaches the H level and the field activation signal ACT # A accordingly reaches the H level. In clock cycle # 3, an instruction other than the activation instruction is delivered. In clock cycle # 3, the selection signals ZBAS and BAS are b from the determination circuit 30 shown in Fig. 12, at the L level and the H level, and the CMOS transmission gate Taa and TBA, the Feldak tivierungssignale ACT # A and B select ACT #, c in the conductive state in the bank decision circuit 30th Since the array activation signal ACT # A is at H level, and the Fel daktivierungssignal ACT # B at the L level, the loading operation mode designation signal .phi.A of the operation mode identifier is voltage signal generating circuit 30 d in the active state at the H level for a prescribed period for the command that is different from the activation command.

Accordingly, a designated mode of operation is executed in bank #A. If the command provided in clock cycle # 3 is the precharge command, the field enable signal ACT # A is driven low, as shown by the dashed line in FIG. 13.

Operation when banks #A and #B are both in the active state will now be described with reference to FIG. 14. In clock cycle # 0, banks #A and #B are both in the deactivated state.

In clock cycle # 1, an activation command for bank #A is provided. Accordingly, the field activation signal ACT # A receives the active state, comparable to the operation shown in FIG. 13.

Next, in clock cycle # 3, an activation command for bank #B is provided and bank activation signal ACT # B is driven into the active state. Since the field activation signals ACT # A and ACT # B are both at the H level, the selection signal ZBAS from the determination circuit 30 b is in the active state at the L level and the selection signal BAS is in the active state at the H -Level. As a result, the CMOS transmission gate tab and Tbb be in the Bankentschei decision circuit 30 c conductive and the bank designating signals ba and bb are the operation mode designation signal generating circuits 30 d and 30 e delivered.

In clock cycle # 6, an instruction other than the activation instruction (read or write instruction in Fig. 14) is provided for bank #A. At this time, the bank address signal BA is at the H level, the bank #A is designated, and the bank designation signal Φba is in the active state at the H level for a prescribed period. According to the command supplied in clock cycle # 6, the operation mode instruction signal Φ receives the active state at the H level, the operation mode designation signal Φa from the operation mode designation generation circuit 30 d accordingly receives the H level, and a designated operation mode becomes in the bank #A executed.

The instruction in clock cycle # 6 is the other instruction that differs from distinguishes between the activation command and the precharge command, and the field activation signals ACT # A and ACT # B are both in the kept active state.

In clock cycle # 10, an instruction other than the Ak activation command and the precharge command is (read and write commands), for bank #B and the bank address signal BA is set to L level to designate bank #B. In in this case the bank designation signal Φbb receives the active one State at the H level and the operation mode designation signal ΦB for bank #B maintains the active state at the H level corresponding to the operation mode designation signal Φ which is in the active state according to the designated operating mode ge sets is.

If the banks #A and #B are both in the active state, an operation mode designation signal for a bank is outputted, which is indicated by the bank address signal BA, which is provided simultaneously with the command. If only one bank is in the active state, an operating mode designation signal is provided for the bank in the active state. If the banks #A and #B are both in the deactivated state, the selection signal ZBAS reaches the H level and the bank decision circuit 30 c selects the field activation signals ACT # A and ACT # B and delivers them to the operating mode designating signal generation circuits 30 a and 30 e. In this state, the field activation signals ACT # A and ACT # B are both at the L level, so that if the operating mode instruction signal erhält receives the active state, even if a command other than the activation command is incorrectly delivered, the operating mode designation signals ΦA and ΦB maintain the deactivated state and the banks #A and #B do not carry out any operation. Accordingly, unnecessary power consumption can be prevented.

As described above, if only one bank in the ak tive state is an operating mode designation signal automatically for the bank in the active state regardless of the Bank address signal delivered when one command, another than the activation command is delivered. The structure, implementing the above operation allows a external control doesn't need to deliver one Bank address signal simultaneously with a command, and reduces the burden on the controller when selecting one Bank.

(Modification 1 of the Bank Driver Signal Generation Circuit)

FIG. 15 shows a structure of a modification of the bank driver signal generation circuit 30 shown in FIG. 11. The structures of the bank decision circuit 30 c and the operation mode designation signal generation circuits 30 d and 30 e are shown in FIG. 15. The structure of the determination circuit 30 b is similar to that shown in FIG. 12.

. Referring to Figure 15, the bank decision circuit 30 c comprises: a NAND circuit 30 about which the selection signal BAS from the determination circuit 30 b in Fig 12 and the bank designation signal Φba which is supplied via an inverter 30 cf receives. ; a NAND circuit 30 cb which receives the selection signal BAS and the bank designation signal Φbb, which is supplied via an inverter 30 cg; an AND circuit 30 cd which receives the field activation signal ACT # A and a signal which is output from the NAND circuit 30 ca; and an AND circuit 30 ce which receives a signal output from the NAND circuit 30 cb and the field activation signal ACT # B. The operation mode designation signal generation circuit 30 d has a NAND circuit 30 db that supplies the operation mode instruction signal Φ and a signal output from the AND circuit 30 cd, and an inverter 30 dc that receives a signal that is output from the NAND circuit 30 db is output, receives and outputs the operation mode designation signal ΦA. The operation mode designation signal generating circuit 30 e includes a NAND circuit 30 ea that receives the operation mode instruction signal Φ and a signal output from the AND circuit 30 ce, and an inverter 30 eb that receives a signal that is output from the NAND circuit 30 ea is output, receives and outputs the operating mode designation signal Φb. Accordingly, these operation mode designation signal generation circuits 30 d and 30 e are substantially equivalent to the AND circuits and have structures equivalent to those shown in FIG. 12.

In the structure shown in Fig. 15, a logic circuit is used in place of the CMOS transmission gate. If the field activation signals ACT # A and ACT # B are both in the active state at the H level, the selection signal BAS is in the active state at the H level (see FIG. 12) and the NAND circuits 30 ca and 30 cb work as an inverter. If the bank designation signal Φba reaches the H level, the signal output from the inverter 30 cf becomes the L level, the signal output from the NAND circuit 30 ca becomes the H level, and that Accordingly, the signal output from the AND circuit 30 cb becomes the H level. As a result, the operation mode designation signal ΦA reaches the H level in the active state in accordance with the operation mode instruction signal Φ.

If at least one bank is in the deactivated state, the selection BAS receives the L level and the signals which are output by the NAND circuits 30 ca and 30 cb are fixed at the H level. In this state, the logic levels of the output signals from the AND circuits 30 cd and 30 ce are decided according to the states of the field activation signals ACT # A and ACT # B regardless of the state of the bank designation signals Φba and Φbb. If the field activation signal ACT # a is in the active state, the signal which is output from the AND circuit 30 cd reaches the H level, so that the operating mode designation signal ΦA is driven to the active state in accordance with the operating mode instruction signal Φ. If the field activation signal ACT # B is at the H level in the active state, the signal which is output from the AND circuit 30 ce reaches the H level, so that the operating mode designation signal ΦB is in the active state accordingly Operating mode instruction signal Φ is driven. If the field activation signals ACT # A and ACT # B are both in the deactivated state, the signals output by the AND circuits 30 cd and 30 ce are both set to the L level in the deactivated state, so that the Operating mode designation signals ΦA and ΦB are kept at the L level in the deactivated state.

As shown in Fig. 15, although the bank decision circuit is composed of the logic gates when only one bank is in the active state, the operation mode designation signal can be supplied to the bank in the active state regardless of the state of the bank address signal.

(Modification 2 of the Bank Driver Signal Generation Circuit)

FIG. 16 shows a structure of modification 2 of the bank driver signal generation circuit 30 shown in FIG. 1. The bank driver signal generation circuit 30 shown in FIG. 16 also outputs operation mode designation signals ΦA and ΦB in accordance with a command other than the activation command. . Referring to Figure 16, the bank drive signal generating circuit 30 comprises a bank determination / - decision circuit 30 f, which receives the bank activation signals ACT # A and ACT # B and the bank designating signals Φba and Φbb determined whether the bank #A and the bank .phi.B both are in the active state or not, decides whether the bank designation signals Φba and Φbb are valid / invalid according to the determination, and decides on a Frank to be selected. The bank drive signal generating circuit 30 further has the operation mode designation signal generating circuits 30 d and 30 e to which the operation mode designation signals ØA and ØB for the banks #A or #B corresponding to a signal / decision circuit of the bank determination is output 30f, to output.

The bank determination / decision circuit 30f has an inverter 30 fa that receives the bank designation signal Φba, a NAND circuit 30 fb that receives the field activation signal ACT # B and a signal output from the inverter 30 fa, an AND circuit 30 fc which receives the field activation signal ACT # A and a signal which is output by the NAND circuit 30 fb, an inverter 30 fd which receives the bank designation signal Φbb, a NAND circuit 30 fe which a signal which is output from the inverter 30 fd and receives the field activation signal ACT # A, and an AND circuit 30 ff which receives a signal which is output by the NAND circuit 30 fe and the field activation signal ACT # B, on.

The operation mode designation signal generation circuit 30 d includes a NAND circuit 30 db that receives a signal output from the AND circuit 30 fc and the operation mode instruction signal Φ, and an inverter 30 dc that receives the signal from the NAND circuit 30 db is output, inverted and the operating mode designation signal A outputs. The operation mode designation signal generation circuit 30 e has a NAND circuit 30 ea that receives a signal output from the AND circuit 30 ff and the operation mode instruction signal Φ, and an inverter 30 eb that receives the signal from the NAND circuit 30 ea is output, inverted and outputs the operating mode designation signal ΦB. If the field activation signal ACT # B is at the L level in the deactivated state, the signal output from the NAND circuit 30 fb is fixed at the H level and the AND circuit 30 fc functions as a buffer so that a bank designation signal for bank #A is output in accordance with the field activation signal ACT # A. If the field activation signal ACT # B is in the active state, the NAND circuit 30 fb operates as an inverter, so that a bank designation signal for the bank #A corresponding to the bank designation signal Φba and the field activation signal ACT # A is output.

Looking at the bank #B, if the field activation signal ACT # A is in the active state and the bank #A is in the active state, the NAND circuit 30 fe operates as an inverter so that a bank designation signal for the bank #B is corresponding of the bank designation signal Φbb and the field activation signal ACT # B is output. If the field activation signal ACT # A is at the L level in the deactivated state, the signal which is output by the NAND circuit 30 fe is fixed at the H level, so that the bank designation signal for the bank #B is corresponding of the field activation signal ACT # B is output.

Accordingly, in the structure of the bank determination / decision circuit shown in Fig. 16, if the field activation signals ACT # A and ACT # B are both at the H level in the active state and the banks #A and #B are both in are active, the bank designation signals for banks #A and #B are output in accordance with bank designation signals Φba and Φbb. If one of the field activation signals ACT # A and ACT # B is in the deactivated state and the other bank is in the active state, the bank designation signals Φba and Φbb are invalidated for the bank in the active state (do not care = don't care) so that the bank designation signal corresponding to the field activation signal for the bank is output in the active state. If both of the field activation signals ACT # A and ACT # B are in the deactivated state, the signals output from the AND circuits 30 fc and 30 ff are fixed at the L level, and the operation mode designation signals ΦA and ΦB are in that deactivated state fixed at the L level, so that the operating mode is not designated.

In the two-bank structure, if one bank is in the active state, the bank designation signal is valid for the other bank, and a bank selection signal for the other bank is outputted in accordance with the valid bank designation signal and the field activation signal for the other bank. Therefore, if a plurality of banks are kept in the active state at the same time, a bank is selected in accordance with the bank designation signal. If one bank is in the active state, the bank designation signal for another bank is invalidated and the bank designation signal for the other bank is generated in accordance with the field activation signal for the other bank. Accordingly, if only one bank is in the active state, the active bank is always selected. In the structure shown in Fig. 16, two operations are carried out simultaneously. More specifically, an operation is performed to determine whether or not a plurality of banks are kept in the active state at the same time, and the other operation is performed to determine whether a bank designation signal is valid or invalid according to the determination, and so on output the bank selection signal for the bank in the active state if only one bank is in the active state.

By using such a bank determination / decision circuit as shown in Fig. 16, the bank determination circuit and the bank decision circuit need not be provided separately, and a reduction in the signal propagation delay and the generation of bank selection signals at high speed is enabled.

(Specific Structure of Bank Driver Signal Generation Circuit)

Fig. 17 shows a structure of the particular Banktreibersig nalerzeugungsschaltung. Referring to Fig. 17, the bank drive signal generation circuit 30 includes: a bank selection control circuit 30 g which controls the validity / invalidation of the bank designation signal Φba in accordance with the bank designation signal Φba and the field activation signal ACT # B; a bank selection control circuit 30 h which decides whether the bank designation signal Φbb is valid or invalid according to the field activation signal ACT # A and the bank designation signal Φbb; a Vorladetriggersignalerzeugungsschaltung 30 i which the Feldak tivierungssignal ACT # A and the Vorladebetriebsanweisungssignals Φp outputs a signal which is outputted from the bank selection control circuit 30 g, corresponding to a Vorladebetriebsbezeichnungssignal (Vorladetriggersignal) Φpa for the bank #A; which a read trigger signal for the bank #A Φra Le sebetriebsmodusanweisungssignals .phi.R, the Feldaktivierungssig Nals ACT # A and a signal circuit of the bank selection control output corresponding to 30 g of a read trigger signal generating circuit 30 j, outputs; and a write trigger signal generation circuit 30 k which selects a write trigger signal Φwa indicating a data write operation for the bank #A in accordance with the write operation instruction signal Φw, the field activation signal ACT # A, and a signal output from the selection control circuit 30 g. The trigger signal generation circuits 30 i, 30 j and 30 k are enabled if the field activation signal ACT # A is in the active state and the signal which is output by the bank selection control circuit 30 g is in the active state at the H level, to output a trigger signal that designates an operating mode corresponding to the supplied operating mode instruction signal.

The bank drive signal generating circuit 30 further includes: a Vorladetriggersignalerzeugungsschaltung 30 m, the designating an on charging trigger signal Φpb, a precharging operation for the bank #B according to the Vorladebetriebsanweisungssignals Φp, which is issued from the selection control circuit 30 h of a signal, and array activation signal ACT # B , out there; a read trigger signal generating circuit 30 n, which a read trigger signal Φrb which a data read operation for the bank #B according to the read operation instruction signal .phi.R, the Fel daktivierungssignals ACT # B and a signal of the kauswahlsteuerschaltung of the Ban 30 is output h is, from there; and a write trigger signal generating circuit 30 p, which indicates a write trigger signal Φwb that Φw, array activation signal ACT # B and a signal is issued from the selection control circuit 30 hours a data writing operation for the bank #B according to the Schreibbetriebsmodusanweisungssig Nalles outputs.

The trigger signal generating circuits 30 m, 30 n and p 30 is released when the signal circuit of the bank selection control output 30 h, is in the active state at the H level and the array activation signal ACT # B is in the active state to to output a corresponding operating mode designation signal (trigger signal) in accordance with the supplied operating mode instruction signal.

The bank selection control circuit 30 g has an inverter 30 ga that receives the bank designation signal Φba and a NAND circuit 30 gb that receives a signal output from the inverter 30 ga and the field activation signal ACT # B. The bank selection control circuit 30 h includes an inverter 30 ha, receives the bank designation signal Φbb, and a NAND circuit 30 hb, which receives a signal which is output from the inverter 30 ha, and array activation signal ACT # A, to. The signals for selecting the banks are output from the 30 gb and 30 hb NAND circuits. The bank selection control circuits 30 g and 30 h correspond to the structures of the inverters 30 fa and the NAND circuit 30 fb and the inverters 30 fd and the NAND circuit 30 fe shown in FIG. 16. The precharge trigger signal generation circuit 30 i has a 3-input NAND circuit 30 ia which contains the precharge instruction signal Φp, the field activation signal ACT # A and a signal which is output by the NAND circuit 30 gb, and an inverter 30 ib which generates a signal , which is output by the NAND circuit 30 , is inverted and outputs the precharge trigger signal Φpa for the bank #A.

The read trigger signal generation circuit 30 j for the bank #A has a 3-input NAND circuit 30 yes which receives the read operation instruction signal Φr, the field activation signal ACT # A and a signal which is output by the NAND circuit 30 gb, and an inverter 30 jb that inverts a signal output from the NAND circuit 30 and outputs the read trigger signal Φra for the bank #A.

The write trigger signal generation circuit 30 k has a 3-input NAND circuit 30 ka which receives the write operation instruction signal Φw, the field activation signal ACT # A and a signal output from the NAND circuit 30 gb, and an inverter 30 kb which inverts a signal output from the NAND circuit 30 ka and outputs the write trigger signal Φwa for the bank #A. The Vorladetriggersignalerzeugungsschaltung 30 m for the bank #B includes a 3-input NAND circuit 30 ma contained the Vorladebe drive instruction signal Φp, which is output from the NAND circuit 30 hb a signal, the circuit in the bank selection control 30 h , and receives the field activation signal ACT # B, and an inverter 30 mb that inverts a signal output from the NAND circuit 30 ma and outputs the precharge trigger signal Φpb for the bank #B. The read trigger signal generation circuit 30 n for the bank #B has a 3-input NAND circuit 30 na which receives the read operation instruction signal Φr, the field activation signal ACT # B and a signal which is output by the NAND circuit 30 hb, and an inverter 30 nb that inverts a signal output from the NAND circuit 30 na and outputs the live trigger signal Φrb that designates the read operation mode for the bank #B.

The write trigger signal generating circuit 30 p for the bank #B includes a 3-input NAND circuit 30 pa which the Schreibbe receives a signal from the NAND circuit 30 hb is output drive instruction signal Φw and array activation signal ACT # B, and an inverter 30 pb which inverts a signal output from the NAND circuit 30 pa and outputs the write trigger signal Φwb which designates the write operation mode for the bank #B.

The trigger signal generation circuits 30 m, 30 n and 30 p are enabled if the field activation signal ACT # B is in the active state and the signal output by the bank selection control circuit 30 h is in the active state to generate a corresponding operating mode designation signal ( Trigger signal) according to the supplied operating mode instruction signa 34204 00070 552 001000280000000200012000285913409300040 0002019821215 00004 34085ls. The structures of the trigger signal generation circuits 30 i, 30 j, 30 k, 30 m, 30 n and 30 p correspond to the structures of the AND circuits 30 fc and 30 ff, and the operating mode designation signal generation circuits 30 d and 30 e shown in FIG. 16 are shown.

In the structure shown in Fig. 17, the trigger signal generation circuits 30 i to 30 k and 30 m to 30 p implement the function of determining whether or not only a corresponding bank is in the active state. If the other bank is in the deactivated state, the bank selection control circuits 30 g and 30 h deactivate the bank designation signal, since only one bank that corresponds to this can be in the active state. If the other bank is in the active state, a plurality of banks could be in the active state at the same time, so that the bank selection control circuits 30 g and 30 h validate the bank designation signals Φba and Φbb and the states of the output signals corresponding to the bank designation signals Φba and Put Φbb.

Referring to the timing charts shown in Figs. 18 and 19, an operation of the bank driver signal generating circuit shown in Fig. 17 will be described below.

First, referring to Fig. 18, an operation performed if the read command is supplied when only one bank is driven to the active state will be described. In clock cycle # 0, banks #A and #B are both in the deactivated state and field activation signals ACT # A and ACT # B are both in the deactivated state at the L level. In this state, the signals output from the bank selection control circuits 30 g and 30 h are at the H level. However, since the trigger signal generation circuits 30 i to 30 k and 30 m to 30 p supply the field activation signals ACT # A and ACT # B, respectively, the trigger signals are in the deactivated state at the L level.

In clock cycle # 1, the bank address signal BA is set to the H level and an activation command is provided. The bank activation instruction signal Φa is in the active state at the H level for a prescribed period and the bank designation signal signalba is in the active state at the H level for a prescribed period. Accordingly, the field deactivation signal ACT # A for bank #A is driven to the H level in the active state, as is apparent from the structure shown in FIG. 10.

A read command is provided in clock cycle # 4. In this case, the field activation signal ACT # A is in the active state at the H level and the field activation signal ACT # B is in the deactivated state at the L level. As a result, the trigger signals from the trigger signal generating circuits 30 m to 30 p for the bank #B are all kept at the L level in the deactivated state. In the bank selection control circuit 30 g, the signal output therefrom is at the H level, and the field activation signal ACT # A is in the active state at the H level, so that the trigger signal generation circuits 30 i to 30 k for the Bank #A are all released. As a result, if the read command is supplied and the read operation instruction signal Φr is driven to the active state at the H level for a prescribed period, the read trigger signal Φra from the read trigger signal generation circuit 30 j is in the active state at the H level for one prescribed period and a data reading mode for bank #A is designated. In clock cycle # 4, the status of the bank address signal BA is arbitrary or freely selectable and the states of the bank designation signals Φba and Φbb are also arbitrary or freely selectable. Regardless of the state of the bank address signal BA, only the trigger signal generating circuit for the bank #A is released.

A precharge command is provided in clock cycle # 9. The state of the bank address signal BA is also arbitrary or freely selectable. According to the precharge command, the precharge instruction signal Φp is in the active state at the H level for a prescribed period. In clock cycle # 9, the signal output from the bank selection control circuit 30 g is at the H level, the field activation signal ACT # A is also at the H level, and only the trigger signal generation circuits 30 i to 30 k for the bank #A are released. Accordingly, if the precharge instruction signal Φp is in the active state at the H level for a prescribed period corresponding to the precharge command, the precharge trigger signal Φpa from the precharge trigger signal generating circuit 30 i is in the active state at the H level for a prescribed period, so that the field activation signal ACT # A is driven into the deactivated state at the L level according to the structure shown in FIG. 6. In cycle # 9, the state of the bank address signal BA is also arbitrary or freely selectable.

As described above, if only one bank in the ak tive state, an operating mode corresponding to a Command for the bank in the active state. In and after clock cycle # 10, banks #A and #B are again in that disabled state and in the state of waiting for the next command entry.

Next, referring to Fig. 19, an operation that is performed when banks #A and #B are simultaneously driven in the active state will be described. In clock cycle # 0, both banks #A and #B are in the deactivated state. In clock cycle # 1, the bank address signal BA is set to the H level and an activation command is provided. Accordingly, the bank activation instruction signal Φa is in the active state at the H level for a prescribed period of time, the field activation instruction signal Φba for the bank #A is at the H level for a prescribed period and the field activation signal ACT # A for the bank #A becomes demented speaking driven to the active state at the H level. In clock cycle # 3, the bank address signal BA is set to L level and an activation command is provided. In the state in which the bank address signal BA is at the L level, the bank #B is designated. The bank activation instruction signal Φa is activated and the bank designation signal Φbb is driven into the active state at the H level for a prescribed period. Accordingly, the field activation signal ACT # B for bank #B is driven into the active state. In clock cycle # 3, the field activation signals ACT # A and ACT # B are both in the active state at the H level. In this state, signals are outputted from the bank selection control circuits 30 g and 30 h, decided by the bank designating signals and Φba Φbb (since the NAND circuits 30 and 30 ga hb as an inverter to work).

In clock cycle # 5, the bank address signal BA is set to the H level and a read command is provided. According to the bank address signal BA at the H level, the bank designation signal Φba is at the H level for a prescribed period and a read operation instruction signal Φr is at the H level for a prescribed period in accordance with the read command. As a result, a signal control circuit of the bank selection is issued 30 g is reached, the H level and the Trig gersignalerzeugungsschaltungen 30 i k for the bank #A who released until the 30th According to the read operation instruction signal Φr, the read trigger signal generation circuit 30 j drives the read trigger signal Φra, which designates the read operation mode for the bank #A, to the active state. For bank #B, since the bank designation signal Φbb is at the L level, the trigger signal generating circuits 30 m to 30 p are all in the deactivated state. Data reading operation is carried out in bank #A.

Next, in clock cycle # 9, the bank address signal BA is set to L level and a read command is provided. Accordingly, the bank address signal BA at the L level, the bank designation signal Φbb is set in the active state at the H level for a prescribed period of time and a signal which is output by the bank selection control circuit 30 h, it accordingly reaches the H level, so that the trigger signaler generating circuits 30 m to 30 p are released for bank #B. According to the read command, the read operation instruction signal Φr is driven into the active state at the H level for a prescribed period, the read trigger signal Φrd from the read trigger signal generating circuit 30 n is in the active state at the H level for a prescribed period, and the data read mode for bank #B is called net.

While a value in bank #B is being read out, in clock cycle # 11, bank address signal BA is set to H level and a precharge command is provided. As a result, the precharge instruction signal Φp and the bank designation signal Φba are set in the active state at the H level for a prescribed period, the precharge trigger signal Φpa from the precharge trigger signal generating circuit 30 i is at the H level for a prescribed period, and the precharge operation mode for bank #A is labeled. According to the activation of the precharge trigger signal Φpa, the field activation signal ACT # A is driven to the deactivated state at the L level.

If the field activation signal ACT # A receives the deactivated state at the L level, a signal which is output from the bank selection control circuit 30 h is kept at the H level regardless of the state of the bank designation signal Φbb, and the trigger signal generating circuits 30 m up to 30 p for bank #B are released.

In clock cycle # 13, data reading in bank #B is completed and a precharge command is provided. At this point in time, the bank address signal BA is in a freely selectable or arbitrary state (since only one bank is kept in the active state). According to the precharge command, the precharge instruction signal Φp is driven to the H level for a prescribed period. Since the field activation signal ACT # A is at the L level in the deactivated state and the field activation signal ACT # B is at the H level in the active state, the precharge trigger signal generation circuit 30 m is released for the bank #B, and the precharge trigger signal Φpb for bank #B is driven into the active state at the H level for a prescribed period of time and the field activation signal ACT # B is accordingly driven into the deactivated state at the L level, regardless of the states of the bank designation signals Φba and Φbb.

As described above, in the operating mode, in where two banks are in the active state at the same time, one Bank for which an operation is carried out according to an instruction is designated by the externally supplied bank address signal BA net. Therefore, the bank address signal can be set to the L level and bank #B can be designated in clock cycle # 13 to the address designation in this operating mode to keep constant.

The above description relates to the data reading operation. However, if the write command is provided, it is determined whether the Bank designation signal is valid or invalid, selectively depending on whether bank #A and bank #B are activated at the same time or not, and the clerk drive mode is called.

FIG. 20 schematically shows a structure of the bank driver circuit of the semiconductor memory device shown in FIG. 1 and a portion related to data read / write (column related circuit) of the bank. Banks #A and #B have the same structure, and bank driver circuit 5 for bank #A and bank driver circuit 6 for bank #B have the same structure, so that only the structures of bank #A and bank driver circuit 5 in FIG. 20 are shown. The bank driver circuit 5 has: a column selection control circuit 5 c, which reacts to the activation of a signal, the read trigger signal Φra or the write trigger signal Φwa, for controlling a column selection operation in the memory cell array 50 of bank #A; a read control circuit 5 d, which is activated in response to the activation of the read trigger signal Φra, for controlling the operating sequences necessary for reading data in accordance with a prescribed sequence; and a write control circuit 5 e, which reacts to the activation of the write trigger signal Φwa, for controlling the operational sequences necessary for data writing. The read control circuit 5 d and the write control circuit 5 e inherently have burst length counter, and control the operations such that data is read with the burst length and written when the read trigger signal Φra or the write trigger signal Φwa in the active state. The read control circuit 5 a further has a CAS latency counter and controls the operation such that a valid effective value is output after the CAS latency has expired.

The bank #A comprises: a Spaltenadreßverriegelung 60, c is tivated ak under the control of the column select control circuit 5 for latching a column address, which is (not shown) from a Adreßsignaleingangspuffer supplied; a column selection circuit 62 , which is activated under the control of the column selection control circuit 5 c, for selecting a column in the memory cell array 50 ; a read circuit 64 , which is activated under the control of the read control circuit 5 d, for reading memory cell data appearing on a column selected by the column selection circuit 62 , for supplying the read data to an input / output circuit 7 ; and a write circuit 66 activated under the control of the write control circuit 5 e for transferring data supplied from the input / output circuit 7 to a column selected by the column selection circuit 62 .

Column selection circuit 62 includes: a column decoder that decodes an internal column address signal provided by column address latch 60 ; a column selection gate (IO gate) that connects a selected column in the memory cell array 50 to an internal data bus in accordance with a signal output from the column decoder; and a burst address counter, the column address successively with a column address signal is latched by the Spaltenadreßverriegelung 60, as a result the address in a prescribed sequence under the STEU of the column select control circuit 5 generates augmentation c. The read circuit 64 has a preamplifier, which is also activated under the control of the read control circuit 5 d, and amplifies data in a memory cell, which is selected by the column selection circuit 62 , and a transmission circuit, the data which is amplified by the preamplifier, transmits sequentially to the input / output circuit 7 . The write circuit 66 has a write driver, which receives data sequentially supplied from the input / output circuit 7 , for writing the transferred write data into a selected memory cell when it is activated.

The read circuit and the write circuit in bank #B are also coupled together with the input / output circuit 7 . The bank driver circuit 6 has a structure which is similar or identical to that of the bank driver circuit 5 , and carries out the control in a similar or identical sequence in accordance with the activation of the read trigger signal Φrb and the write trigger signal Φwb.

The input / output circuit 7 is provided with an output control circuit 70 which activates an output buffer circuit provided in the input / output circuit 7 for a period of the burst length after the CAS latency has elapsed is, corresponding to the activation of the read operation instruction signal Φr. An input circuit included in the input / output circuit 7 is enabled when the bank activation instruction signal (activation command) is supplied because the value that is applied when the write command is supplied should be included.

As shown in Fig. 20, a designated operation mode is executed in a selected bank in accordance with the read trigger signals Φra and Φrb and the write trigger signals Φwa and Φwb.

According to the first embodiment of the invention, if only one of the two banks is in the active state, on Operating mode designation signal to the bank in the active state tand delivered. As a result, there is no need a bank address signal simultaneously with the delivery of a command les that differs from the activation command deliver, and the control for the bank name is united fold.

(Second embodiment)

Fig. 21 schematically shows a whole structure of a semiconductor memory device according to the second embodiment of the invention. As shown in Fig. 21, four banks #A, #B, #C and #D are provided. For these banks #A, #B, #C and #D, a bank address signal input buffer 100 that receives a bank address signal that designates a bank and generates an internal bank address signal is a command decoder 102 that receives a command that specifies an operating mode, which is to be executed, and outputs an internal operation mode instruction signal Φ, and an address signal input buffer 104 which receives an address signal indicating a location of a selected memory cell and generates internal row and address signals X and Y, is provided. The instruction decoder 102 has a structure similar to that of the first embodiment, determines an operation mode corresponding to a combination of the states of the external control signals ZRAS, ZCAS and ZWE (not shown) on the rising edge of the clock signal CLK, and outputs the operating mode instruction signal Φ instructing an operating mode instructed according to the determination. The bank address signal input buffer 100 receives a 2-bit bank address signal and generates complementary internal bank address signals. The 2-bit bank address signal denotes a bank. The address signal input buffer 104 has a structure similar to that of the first embodiment.

The semiconductor memory device further includes bank driver circuits 110 , 112 , 114 and 116 which are provided corresponding to banks #A to #D for driving the respective banks, and a bank driver signal generating circuit 118 which generates operation mode designation signals ΦA, ΦB, ΦC and ΦD which each designate an operating mode, and supplies them accordingly to the bank driver circuits 110 , 112 , 114 and 116 for a designated bank in accordance with the internal bank address signal BAi from the bank address signal input buffer 100 and the operating mode instruction signal Φ from the command decoder 102 .

The bank driver signal generation circuit 118 receives field activation signals ACT # A, ACT # B, ACT # C and ACT # D from the bank driver circuits 110 , 112 , 114 and 116 and outputs an operating mode designation signal for an addressed bank in accordance with a bank address signal when a plurality of banks are in the active state at the same time. The bank driver signal generation circuit 118 outputs an operation mode designation signal corresponding to an operation mode instruction signal for a bank that is the only bank in the active state.

FIG. 22 schematically shows a structure of the bank driver signal generating circuit 118 shown in FIG. 21. Referring to FIG. 22, the bank driver signal generation circuit 118 includes a bank determination / decision circuit 120 which receives bank designation signals Φba, Φbb, Φbc and Φbd as well as the field activation signals ACT # A, ACT # B, ACT # C and ACT # D if a plurality of banks in the active state, and decides whether a bank designation signal is also made valid or invalid, in accordance with the He gebnisses determining and Betriebsmodusbezeichnungssig nalerzeugungsschaltungen 122 a, 122 b, 122 c and 122 d, the selec tive are activated in accordance with an output signal from the bank determination / decision circuit 120 , and outputs the operation mode designation signals ΦA, ΦB, ΦC and ΦD, which designate an operation mode instructed in accordance with the operation mode instruction signal Φ, when it is activated. The bank determination / decision circuit 120 , if only one bank is in the active state, activates an operating mode designation signal generation circuit provided corresponding to the bank that is in the active state. If a plurality of banks are in the active state, the bank determination / decision circuit 120 activates an operation mode designation signal generation circuit which is provided corresponding to a bank designated by a bank designation signal.

FIG. 23 shows an example of a structure of a section for bank #A in the bank driver signal generating circuit 118 shown in FIG. 21. Similar or identical structures are provided for banks #B to #D.

. Referring to Figure 23, the bank drive signal generating sschaltung 118 comprises: an OR circuit 118A for receiving the bank activation signals ACT # B, ACT and ACT # C # D; an inverter 118 b that receives the bank designation signal Φba; a NAND circuit 118 c, which receives a signal that is output from the OR circuit 118 a and a signal that is output from the inverter 118 b; a 3-input NAND circuit 118 d, which receives a signal from the NAND circuit 118 c, the field activation signal ACT # A and the operating mode instruction signal Φ; and an inverter 118 e that inverts a signal output from the NAND circuit 118 d to output the operation mode instruction signal ΦA. The bank designation signal Φba rises to the H level in the active state for a prescribed period when the bank #A is designated.

In the structure shown in FIG. 23, the OR circuit 118 a, the inverter 118 b, the NAND circuit 118 c and a part of the NAND circuit 118 d correspond to the bank determination / decision section in FIG. 22, and a part of the NAND circuit 118 d and the inverter 118 e correspond to the operation mode designation signal generating section shown in FIG. 22. The NAND circuit 118 d is enabled if both the array activation signal ACT # A as the output from the NAND circuit 118 c and the signal, are at the H level, and outputs the operation mode designation signal .phi.A via the inverter 118 e according to the operating mode instruction ignals signal.

The inverter 118 b, the OR circuit 118 a and the NAND circuit 118 c decide whether the bank designation signal Φba is valid or invalid for bank #A. An operation of the bank driver signal generating circuit 118 shown in FIG. 23 will now be described with reference to the timing chart shown in FIG. 24. An activation command is provided in clock cycle #a and the bank address signal BA is set to a state which designates bank #A. When the activation command is provided, the field activation signal for the bank addressed in accordance with the bank address signal is driven into the active state regardless of the states of the other banks. Accordingly, the field activation signal ACT # A is driven to the active state at the H level in clock cycle #a.

That a signal which is output from the OR circuit 118a is adopted at the H level, then at least one of the field activation signals ACT # B, ACT # C and ACT # D in the ak tive state at the H Level and at least one of the other banks is in the active state. In this state, bank #A and at least one other bank are in the active state and therefore a plurality of banks are in the active state.

In clock cycle #b, bank address signal BA is set to a state denoting bank #A and an instruction other than the activation instruction is provided. Accordingly, the bank address signal BA is the bank designation signal Φba in the active state at the H level for a prescribed period and the operating mode instruction signal Φ is in the active state at the H level for a prescribed period in accordance with the command supplied. A signal that is output from the OR circuit 118 a is at the H level, so that a signal that is output from the NAND circuit 118 c rises to the H level in accordance with the activation of the bank designation signal Φba. Accordingly, the NAND circuit 118 d is released and the operating mode designation signal ΦA for the bank #A is output accordingly to the operating mode instruction signal Φ. Fig. 24 shows a case in which the command supplied in clock cycle #d is a command other than the activation command. If a precharge command is provided in clock cycle #b, the field activation signal ACT # A is driven to the L level in the deactivated state.

Next, a case in which a signal output from the OR circuit 118 a falls to the L level will be described. In this state, the field activation signals ACT # B, ACT # C and ACT # D are all in the deactivated state at the L level and the other banks are all in the deactivated state. If the field activation signal ACT # A is in the active state, only bank #A is in the active state. In clock cycle #c, an instruction other than the activation instruction is delivered. A signal that is output from the OR circuit 118 a is at the L level, and a signal that is output from the NAND circuit 118 c is held at the H level, regardless of the logical state of the bank designation signal Φba. If the field activation signal ACT # A is in the active state at the H level, the NAND circuit 118 d is enabled. If the operation mode instruction signal Φ is in the active state at the H level for a prescribed period of time in accordance with the command supplied in clock cycle #c, the operation mode instruction signal ΦA for the bank #A is in the active state at the H- Level driven for a prescribed period by the NAND circuit 118 d and the inverter 118 e. In this case, if only the bank #A is in the active state, there is no need to set the bank address signal BA for the bank #A, and the state of the bank address signal is arbitrary. In the structure having four banks, if only one bank is in the active state, an operating mode designation signal is provided for the bank in the active state. Even in the four-bank structure, there is no need to put the bank address signal in a state that designates a bank in an active state simultaneously with the delivery of the command other than the activation command and the controller the bank address signal is simplified as in the first embodiment.

As described above, the semiconductors storage device having four banks is in the second embodiment of the invention structured as follows. If only one bank is in the active state, a Be Drive mode designation signal for the bank in the active state tand delivered. As a result, control becomes easier realized to designate a bank.

(Other applications)

Although the number of banks in the above description is two or four, the number of banks is freely selectable. In the structure shown in Fig. 23, by using a structure in which it is determined in accordance with the state of the field activation signals for other banks and a field activation signal for a corresponding bank, whether a bank address designation signal is supplied to a corresponding bank becomes valid / invalid, and it is determined according to the result of the previous determination whether to make a corresponding operation mode instruction signal active or inactive, the structure of the present invention on a multi-bank semiconductor memory device (multi-bank semiconductor memory device) easily be applied.

In the above first and second embodiments, a syn chron semiconductor memory device which is an externally supplied Picks up signal on the rising edge of the clock signal, described. However, the present invention is based on a syn chron semiconductor memory device applicable that the extern delivered signal on both the falling edge and the on the rising edge of the clock signal.  

The present invention is also applicable to a Semiconductor memory device having a multi-bank structure in which an operation mode instruction signal and a Bank address signal can be supplied externally, even if the half circuit storage device is not of the synchronous type. (Of the Command decoder is not necessary).

According to the present invention is the semiconductor storage device having a plurality of banks, so structures that if only one bank is in the active state is the operating mode designation signal for the active bank in the active state regardless of the state of the bank address nals is driven. As a result, the bank address signal not be set when the operation mode instruction signal is supplied, and easier control of the bank address nals is achieved. Furthermore, there is no need to drive the bank address signal into a prescribed state when a command is delivered, and loading and unloading the bank address signal transmission line need not be executed be what results in a reduction in the Stromver of the overall system results.

Although the present invention is described in detail and il has been illustrated, it is clear to understand that the same thing only serves for the purpose of illustration and example and not can be understood as a limitation. The scope of the present End invention is only by the terms of the appended An sayings limited.

Claims (11)

1. A semiconductor memory device with a plurality of banks (#A, #B; # A- # D) which can be activated and deactivated independently of one another and which have a plurality of bank driver means ( 5 , 6 ; 110 , 112 , 114 , 116 ), corresponding to the plurality of banks for driving a corresponding bank in accordance with a supplied operation mode instruction signal, and drive signal generating means ( 30 ; 118 ) connected to the plurality of bank driver means for determining whether each of the plurality of banks is in the active State, and for outputting, if a result of the determination indicates that one of the plurality of banks is in the active state, the operating mode designation signal corresponding to an applied operating mode instruction signal to the bank in the active state. 2. The semiconductor memory device according to claim 1, wherein the drive signal generating means ( 30 ; 118 )
gate means ( 30 fb; 30 fe; 30 g, 30 h) provided corresponding to the respective one of the plurality of banks for receiving a bank activation signal indicating an active or deactivated state of a bank other than a corresponding bank displays
bank selection means ( 30 fc, 30 ff; 30 g, 30 h) provided corresponding to each of the plurality of banks for holding a bank designation signal designating the corresponding bank in the active state when a signal corresponding to one is outputted, indicates that no bank activation signal received by the corresponding gate means is in the active state, and
a generating means ( 30 d, 30 e; 30 i- 30 k, 30 m- 30 n, 30 p), which is provided in accordance with each of the plurality of banks, for receiving a signal output from a corresponding bank selection means, the Operating mode instruction signals and a bank activation signal for a corresponding bank, for generating the operating mode instruction signal for the corresponding bank,
having. 3. The semiconductor memory device according to claim 1 or 2, which further
generating means ( 30 ac, 30 ad) receiving a bank address signal designating one of the plurality of banks and an externally supplied bank activation instruction signal for generating a bank activation signal which drives an addressed bank into the active state at which the Bank driver means ( 5 , 6 ; 110 , 112 , 114 , 116 ) each have a generating means ( 5 a, 6 a) which reacts to the bank activation signal for generating a field activation signal which activates a corresponding bank, and
the drive signal generating means (30; 118) includes means (30 b, 30 f) for determining whether each of the banks in the active state or in the deactivated state, in accordance with an array activation signal for each comprising one of the plurality of banks. 4. The semiconductor memory device according to one of claims 1 to 3, wherein the drive signal generating means ( 30 ; 118 ) further means ( 30 b; 30 c; 30 f, 30 d, 30 e) for outputting if a result of the determination indicates that at least two banks are in the active state having an operating mode designation signal corresponding to the operating mode instruction signal to an addressed bank corresponding to a bank address signal provided concurrently with the operating mode instruction signal. 5. The semiconductor memory device according to one of claims 1 to 4, at the the operation mode instruction signal indicates a write mode instruction signal that instructs the writing of data. 6. The semiconductor memory device according to one of claims 1 to 4, at the the operation mode instruction signal is a read mode instruction signal that instructs reading data. 7. The semiconductor memory device according to one of claims 1 to 4, at the the operation mode instruction signal is a precharge instruction signal is that a bank in the active state in the deactivated State sets. 8. A semiconductor memory device that operates in synchronism with a clock signal
a plurality of banks (#A, #B; # A- # D) which can be driven independently into an active state and a deactivated state,
bank selection means ( 1 ; 100 ) which receives a bank address signal supplied in synchronization with the clock signal for generating a bank designation signal which designates a bank designated by the received bank address signal,
bank activation means ( 5 , 6 ; 110 , 112 , 114 , 116 ) receiving a bank activation instruction signal provided concurrently with the bank address signal in synchronism with the clock signal for outputting a field activation signal to a bank by the bank designation signal from the bank selection means is designated
internal instruction signal generating means ( 2 ; 102 ) receiving an operation mode instruction signal different from the bank activation instruction signal supplied concurrently with the clock signal, for generating an internal instruction signal corresponding to the received operation module instruction signal and
a plurality of control means ( 30 b- 30 e; 30 c- 30 e; 30 f, 30 d, 30 e; 30 g, 30 h, 30 i- 30 k, 30 m, 30 n, 30 p; 120 , 122 a- 122 d) which of the plurality are provided in correspondence of banks in accordance with, for receiving a bank designation signal from the bank selection means and array activation signals for an ent speaking and other banks of the bank activation means for providing, if the field activation signal for the corresponding bank in the active Is state and the field activation signals for the other banks are in the deactivated state, an operating mode activation signal corresponding to the internal instruction signal for the corresponding bank, while the bank designation signal is neglected by the bank selection means. 9. The semiconductor memory device according to claim 8, wherein the operation mode instruction signal indicates a write mode instruction signal that instructs writing data. 10. The semiconductor memory device according to claim 8, wherein the operation mode instruction signal is a read mode instruction signal that instructs reading data. 11. The semiconductor memory device according to claim 8, wherein the operation mode instruction signal is a precharge instruction signal to put a bank in the active state in the deactivated condition.